Including Differential Amplifier Patents (Class 330/252)
  • Publication number: 20140203872
    Abstract: A differential cross-coupled common-source or common-emitter low-noise amplifier having capacitive degeneration is disclosed. Further, a radio receiver comprising such a low-noise amplifier is disclosed. Further, a method of controlling switched capacitive networks of an amplifier is disclosed. The method comprises controlling capacitances of the switched degeneration capacitor networks and/or the switched cross-coupling capacitor networks. Further, a computer program for implementing the method is disclosed.
    Type: Application
    Filed: July 10, 2012
    Publication date: July 24, 2014
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventor: Henrik Sjöland
  • Publication number: 20140203958
    Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 24, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA, Takashi OSHIMA, Tatsuji MATSUURA
  • Patent number: 8766610
    Abstract: Provided is a voltage regulator capable of reducing an influence of an offset to obtain an accurate output voltage. The voltage regulator includes: a first stage amplifier for amplifying and outputting a difference between a reference voltage and a divided voltage obtained by dividing a voltage output by an output transistor, to thereby control a gate of the output transistor; and a cascode amplifier circuit, in which the first stage amplifier includes: a first high breakdown voltage NMOS transistor as an input transistor; and an NMOS transistor as a tail current source, and in which the cascode amplifier circuit includes a second high breakdown voltage NMOS transistor as a cascode transistor.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 1, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Imura
  • Publication number: 20140159812
    Abstract: A receiving apparatus in a wireless communication system includes: an antenna configured to receive a wireless frequency signal including a first frequency band signal and a second frequency band signal; a low noise amplifier (LNA) configured to amplify the wireless frequency signal, output the first frequency band signal as a differential phase signal, and output the second frequency band signal as a common phase signal; a differentiator configured to pass only the differential phase signal between the signals outputted from the LNA; and a combiner configured to pass only the common phase signal between the signals outputted from the LNA.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 12, 2014
    Applicant: KAIST (Korea Advanced Institute of Science and Technology)
    Inventors: Sang-Gug LEE, Yuna SHIM
  • Publication number: 20140159813
    Abstract: A transconductance circuit that improves linearity and output current over a wider range of input voltages than prior designs. The transconductance circuit may include first and second sets of paired differential transistors. In each set, emitters of the paired transistors may be commonly coupled to corresponding nodes of a common impedance, and collectors may be coupled to output terminals of the transconductance circuit. The circuit may further include first and second sets of doublet differential transistor pairs, each doublet pair having transistors of different sizes. Each doublet pair may have current sources coupled between commonly coupled emitters and a source potential. Respective collectors for each doublet pair may be coupled to the output terminals of the transconductance circuit. A pair of voltage followers may be provided to replicate corresponding input voltages across corresponding bases of the differential transistor pairs and the doublet transistor pairs.
    Type: Application
    Filed: February 18, 2014
    Publication date: June 12, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventor: Sandro HERRERA
  • Patent number: 8742852
    Abstract: A differential amplifier capable of canceling an input offset current and expanding a linearly operating range is disclosed. The differential amplifier, which is preferably applicable to an optical receiver to convert a photocurrent into a voltage signal, includes a trans-impedance amplifier and an offset canceller that detects output offset and extracts input current to cancel the output offset. Moreover, the extracted input current traces the average level of the input voltage to widen the linearly operating range of the trans-impedance amplifier.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: June 3, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yoshiyuki Sugimoto
  • Patent number: 8742845
    Abstract: Various embodiments of an amplifier circuit are provided. In one embodiment, the amplifier circuit includes an input differential circuitry configured to convert a pair of input differential voltage signals to a pair of differential current signals. The amplifier circuit includes a cascode circuitry operable to mirror the pair of differential current signals received from the first output terminal and the second output terminal to an output terminal of the first cascode transistor and an output terminal of the second cascode transistor. The amplifier circuit includes a current control circuit operable to divert an amount of bias current to reduce a current through the cascode circuitry, to thereby reduce a load of the amplifier circuit, the reduction in the load of the amplifier circuit allowing a reduction in current through the input differential circuitry for maintaining a predetermined bandwidth of the amplifier circuit.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: June 3, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Shagun Dusad, Lokesh Kumar Gupta, Visvesvaraya Pentakota
  • Publication number: 20140145789
    Abstract: An amplifier includes a first input terminal, a second input terminal, a TIA, and a compensation circuit. The TIA includes a first transistor, a second transistor, a first current source connected to the first input terminal and an emitter of the first transistor, a second current source connected to the second input terminal and an emitter of the second transistor, a first load resistor connected to a collector of the first transistor, and a second load resistor connected to a collector of the second transistor. A bias voltage is supplied to bases of the first and second transistors, the compensation circuit adjusts a first load current and a second load current based on voltage signals, and the TIA outputs the voltage signals based on collector voltages of the first and second transistors.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 29, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Yoshiyuki SUGIMOTO
  • Publication number: 20140140144
    Abstract: A sense amplifier circuit includes first and second signal lines and first and second inverters. Each inverter includes an input terminal, an output terminal, and a power source terminal. A second signal line potential is supplied to the first inverter input terminal. The second inverter input terminal is connected to the first inverter output terminal, and the second inverter output terminal is connected to the first inverter input terminal. A first signal line potential is supplied to the second inverter input terminal. A first switch transistor is connected to the first inverter power source terminal and has a gate connected to the second signal line. A switch second transistor is connected to the second inverter power source terminal and has a gate connected to the first signal line.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 22, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takaaki NAKAZATO
  • Publication number: 20140126312
    Abstract: Embodiments of a sense amplifier test circuit are disclosed that may allow for detecting soft failures. The sense amplifier test circuit may include a voltage generator circuit, a sense amplifier, and a detection circuit. The voltage generator may be operable to controllably supply different differential voltages to the sense amplifier, and the detection circuit may be operable to detect an analog voltage on the output of the sense amplifier.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: APPLE INC.
    Inventors: Greg M. Hess, James E. Burnette, II
  • Patent number: 8704596
    Abstract: An amplifier arrangement constituted of: a first input lead; a second input lead; a difference amplifier; a first buffer, the input of the first buffer coupled to the first input lead, the output of the first buffer coupled to a first input of the difference amplifier; a second buffer, the input of the second buffer coupled to the second input lead, the output of the second buffer coupled to a second input of the difference amplifier; and a transconductance amplifier, the non-inverting input and the non-inverted output of the transconductance amplifier coupled to the first input of the difference amplifier, the inverting input and the inverted output of the transconductance amplifier coupled to the second input of the difference amplifier. The input signals are thus buffered and the offset of the buffers are compensated for.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: April 22, 2014
    Assignee: Microsemi Corporation
    Inventors: Kai Kwan, Peter Kim
  • Publication number: 20140097896
    Abstract: Apparatus and methods are disclosed related to trimming an input offset current of an amplifier. One such apparatus can include auxiliary bipolar transistors connected in parallel with bases of respective bipolar transistors of an input stage of an amplifier. The auxiliary bipolar transistors can be biased such that the base currents of the auxiliary bipolar transistors compensate for a mismatch in base currents of the bipolar transistors of the input stage of an amplifier. The offset current at an input of an amplifier can be reduced independent of an offset voltage at the input of the amplifier.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: Analog Devices, Inc.
    Inventors: Moshe Gerstenhaber, Rayal Johnson
  • Patent number: 8692616
    Abstract: A folded cascode operational amplifier includes a constant current source to output a constant current; a differential input stage to output a part of the constant current as a differential current based on a voltage difference between voltages input to an inverting input terminal and a non-inverting input terminal, and connected to the constant current source; and an output stage to output a remaining current obtained by subtracting the differential current from the constant current as an output stage current, and connected parallel to the differential input stage facing the constant current source.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: April 8, 2014
    Assignee: Fujitsu Limited
    Inventor: Kunihiko Gotoh
  • Patent number: 8692583
    Abstract: An apparatus, system, and method are provided for a differential integrated input circuit. The apparatus includes n-type semiconductor devices and p-type semiconductor devices. The p-type semiconductor devices are cross-coupled with the n-type semiconductor devices. Each of the p-type semiconductor devices biases a corresponding n-type semiconductor device.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: April 8, 2014
    Assignee: NXP B.V.
    Inventors: Aloysius Johannes Maria Boomkamp, Stefan Butselaar, Ben Gelissen, Mehdi El Ghorba, Cornelis Klaas Waardenburg
  • Patent number: 8692615
    Abstract: A transconductance circuit that improves linearity and output current over a wider range of input voltages than prior designs. The transconductance circuit may include first and second sets of paired differential transistors. In each set, emitters of the paired transistors may be commonly coupled to corresponding nodes of a common impedance, and collectors may be coupled to output terminals of the transconductance circuit. The circuit may further include first and second sets of doublet differential transistor pairs, each doublet pair having transistors of different sizes. Each doublet pair may have current sources coupled between commonly coupled emitters and a source potential. Respective collectors for each doublet pair may be coupled to the output terminals of the transconductance circuit. A pair of voltage followers may be provided to replicate corresponding input voltages across corresponding bases of the differential transistor pairs and the doublet transistor pairs.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: April 8, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Sandro Herrera
  • Publication number: 20140085003
    Abstract: A circuit includes an amplifier including a differential input stage including a first input terminal and a second input terminal. The circuit further includes a differential input line coupled to the first input terminal and the second input terminal, and shielding at least partially encompassing the differential input line. The shielding is connected to a node of the differential input stage of the amplifier.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: XILINX, INC.
    Inventor: Xilinx, Inc.
  • Patent number: 8680938
    Abstract: Apparatus and methods for equalization are provided. In one embodiment, an apparatus for equalizing an input voltage includes a first capacitor and a first resistor having a first end and a second end, the first end configured to receive the input voltage. The apparatus further includes a second resistor having a first end electrically connected to the second end of the first resistor at an output node. The apparatus further includes an inverting voltage buffer for substantially inverting the input voltage to generate an inverted input voltage. The apparatus further includes a transconductance buffer for receiving the inverted input voltage and for generating a current from a first end of the first capacitor to the output node having a magnitude equal to about the magnitude of the input voltage signal divided by the impedance of the first capacitor.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: March 25, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Michael St. Germain, Jennifer Lloyd, Kimo Tam
  • Patent number: 8674764
    Abstract: The present invention provides a high-frequency power amplifying device capable of transmitting output power at high efficiency. For example, a high-frequency power amplifying device has first and second differential amplifiers and a transformer for matching output impedances of the differential amplifiers. Between differential output nodes of the first differential amplifier, an inductor, a switch, and an inductor are coupled in series. When the second differential amplifier is in an operating state and the first differential amplifier is in a non-operating state, the switch is controlled to be on. In this case, due to “off capacitance” in transistors of a differential pair included in the first differential amplifier, impedance on the first differential amplifier side seen from both ends of primary coils becomes a high impedance state (parallel resonance state) and, equivalently, the primary coils do not exert influence on the operation of the second differential amplifier.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: March 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Masao Kondo
  • Publication number: 20140070845
    Abstract: Disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 13, 2014
    Inventors: Kathy Tian, Harry Muljono
  • Patent number: 8669810
    Abstract: When a time difference is amplified by a time difference amplifier, slew rates of internal output voltages are changed according to a phase combination of digital input signals so that a time gain is determined by a ratio between the slew rates and the slew rates can be controlled from an outside. After a voltage is charged to the level of a power supply voltage in first and second charging capacitors, the charged voltage of the first charging capacitor is decreased with a first slew rate when a first digital input signal transitions, and both charged voltages of the first and second charging capacitors are decreased with a second slew rate when a second digital input signal transitions so that both first and second digital input signals are changed from initial phases, while being compared with a reference voltage to generate first and second digital output signals.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: March 11, 2014
    Assignee: Postech Academy-Industry Foundation
    Inventors: Hye Jung Kwon, Hong June Park
  • Publication number: 20140055200
    Abstract: The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to a differential input signal, a first power supply and a ground. The output signal may have a rail-to-rail voltage with a magnitude between the first power supply and the ground. The first circuit may also be configured to source an intermediate differential signal in response to the differential input signal, the first power supply and ground. The second circuit may be configured to sink the differential intermediate signal in response to the differential input signal, the first power supply, ground and a second power supply. The second circuit may flatten the transconductance of the first circuit relative to a common mode voltage of the differential input signal.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Inventor: Kishan Pradhan
  • Patent number: 8659322
    Abstract: An integrated circuit includes a memory cell and a sense amplifier coupled to the memory cell via a first bit line and a second bit line. The sense amplifier includes first and second inverters cross-coupled to provide a latch. The first inverter is responsive to a first data signal provided by the memory cell over the first bit line. The second inverter is responsive to a second data signal as provided by the memory cell over the second bit line. A first negative bias temperature instability (NBTI) compensation transistor includes a source electrode coupled to receive a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to the first data signal.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: February 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alexander B. Hoefler, James D. Burnett, Scott I. Remington
  • Patent number: 8653894
    Abstract: A push-pull amplifier is provided for amplifying an input signal, having first and second amplifier elements. Each of the amplifier elements has a current-emitting electrode, a current-collecting electrode, and a current-controlling electrode. The input signal is supplied to the current-controlling electrodes of the amplifier elements via a respective input connection and a respective input inductor arranged between the respective input connection and the respective current-controlling electrode. The current-collecting electrodes are connected via a respective supply inductor having a common supply voltage. The current-emitting electrode of each amplifier element is connected to the current-collecting electrode of the other amplifier element via a respective capacitor. The current-emitting electrodes are connected to output connections on which the output signal can be picked up, and to a reference potential via a respective output inductor.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: February 18, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventor: Oliver Heid
  • Patent number: 8649749
    Abstract: A voltage sampling RF receiver in which an impedance control circuit controls the input impedance, by using a mixer stage which generates a feedback voltage, which is coupled to the RF input by a feedback resistor. A biasing arrangement can be used to adjust the feedback path so that local oscillator leakage signals are suppressed.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: February 11, 2014
    Assignee: NXP B.V.
    Inventor: Xin He
  • Patent number: 8633770
    Abstract: An amplifier configuration including first and second amplifier inputs and a bias input adapted to receive a common mode signal indicative of a common mode input voltage. First and second amplifier input stage sections, each having first and second inputs coupled to respective ones of the first and second amplifier inputs, are provided. Operating mode circuitry switches the amplifier configuration between first and second operating modes in response to the common mode signal, where in the first operating mode the first and second amplifier input stage sections are active and inactive, respectfully and where in the second operating mode the first and second amplifier input stage sections are inactive and active, respectfully. The active first and second amplifier input stage sections are capable of operating with common mode voltages in excess of the upper and lower power supply rails, respectively.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: January 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Alberto Danioni
  • Patent number: 8629727
    Abstract: A power amplifier includes a first transistor and a first inductor disposed between the first transistor and a voltage source. A first node between the first transistor and the first inductor is an output node. The power amplifier further includes a second inductor disposed between the first transistor and ground The power amplifier further includes a third inductor coupled to a gate of the first transistor and configured as a first AC input. The power amplifier further includes a first phase conditioner inductively coupled to the second inductor and the third inductor and configured to set phases of AC signals across the first inductor and the second inductor in phase. The second inductor is configured to release energy into the first inductor to raise a voltage of the AC signal and raise a power output at the output node.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 14, 2014
    Assignee: Marvell Internatonal Ltd.
    Inventors: Sehat Sutardja, Poh Boon Leong, Ping Song, Nuntha Kumar Krishnasamy Maniam
  • Patent number: 8624671
    Abstract: An amplifying circuit includes a first circuit component configured to receive and amplify first and second input voltages to generate an output voltage. The first circuit component is formed by a first amplifier and a second amplifier. A second circuit component is configured to provide a first offset current that is associated with a first input current of the first amplifier. The first offset current compensates for variation in the first input current. A third circuit component is configured to provide a second offset current that is associated with a second input current of the second amplifier. The second offset current compensates for variation in the second input current.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: January 7, 2014
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.
    Inventors: GuoHua Zhong, XiangSheng Li
  • Publication number: 20140002192
    Abstract: In accordance with an embodiment, a system includes a first transistor and a second transistor. The first transistor has a first input node coupled to a first signal input, a first output node coupled to a first common node, and a first reference node coupled to a first reference voltage, and the second transistor has a second input node coupled to second signal input, a second output node coupled to an output of the system, and a second reference node coupled to the first common node. The system further includes a first switch switchably coupling the first common node to a second reference voltage.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: David Seebacher, Peter Singerl, Christian Schuberth, Martin Mataln
  • Patent number: 8619838
    Abstract: An electric repeater for use in transmission line based electric fences. The electric repeater comprises a forward amplifier, a backward amplifier, a quad pole quad throw signal switch, and a monostable circuit. The short forward electric pulse in the transmission line is amplified by the forward amplifier, and the amplified electric pulse trigger the monostable circuit. The monostable circuit then outputs a n electric pulse with predetermined width. This electric pulse operates the quad pole quad throw signal switch such that the wire pair of the transmission line is connected to the backward amplifier and disconnected from the forward amplifier as soon as the forward electric pulse has passed through the forward amplifier. DC electric power is supplied to the forward amplifier and backward amplifier by the transmission line metal wire pair, and two pairs of capacitors are used to block this DC electric power from entering the input and output of the forward and backward amplifiers.
    Type: Grant
    Filed: March 5, 2011
    Date of Patent: December 31, 2013
    Inventors: Jin Hao, Xuekang Shan
  • Publication number: 20130342273
    Abstract: An electronic circuit has a differential amplifier with a differential transistor pair having two transistors. The electronic circuit also has two digital-to-analog converters, a respective one of the two digital-to-analog converters coupled to each respective one of the two transistors. Control bits adjust the DACs to provide an offset voltage adjustment of the differential amplifier.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 26, 2013
    Applicant: ALLEGRO MICROSYSTEMS, INC.
    Inventor: Craig S. Petrie
  • Publication number: 20130342274
    Abstract: Techniques are disclosed relating to peak detection. In one embodiment, an apparatus is disclosed that includes an amplifier configured to amplify a signal. The apparatus further includes a peak detector DC coupled to an output of the amplifier. The peak detector includes a first comparator stage configured to perform subtraction of a threshold signal from the amplified signal. The peak detector further includes a second comparator stage is configured to amplify a differential output signal of the first comparator stage indicative of a result of the subtraction. In some embodiments, the amplifier and peak detector are included within automatic gain control system in a path for an in-phase or quadrature channel of the receiver chain.
    Type: Application
    Filed: June 25, 2012
    Publication date: December 26, 2013
    Inventors: Abdulkarim Coban, Wenhuan Yu
  • Publication number: 20130335144
    Abstract: Apparatus and methods for notch filtering are provided. In certain implementations, an amplifier includes amplification stages for providing signal amplification, chopper circuitry for generating a chopped signal by chopping an amplified signal associated with the amplification stages at a chopping frequency, and a time-interleaved finite impulse response (FIR) notch filter for notching frequency components of the chopped signal near the chopping frequency. The time-interleaved FIR notch filter includes a plurality of FIR filters configured to sample the chopped signal at a sampling rate of about twice the chopping frequency. The FIR filters are interleaved in time to reduce sampling error. Additionally, the time-interleaved FIR notch filter includes an infinite impulse response (IIR) filter configured to average samples taken by respective ones of the FIR filters and to integrate the averaged samples to generate the time-interleaved FIR notch filter's output signal.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Applicant: Analog Devices, Inc.
    Inventor: Fazil Ahmad
  • Patent number: 8611466
    Abstract: Provided is a discrete time receiver having a structure capable of processing various broadband signals. The discrete time receiver uses a discrete time filter having a sampling frequency in a constant range so as to process a signal having an input frequency in a wide range and a wide bandwidth, so that it is possible to reduce current consumption and the area of the discrete time receiver. Since the discrete time receiver is easily integrated with a digital device, it is easy to design a chip using system on chip (SoC).
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: December 17, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young-Jae Lee, Byung Hun Min, Nguyen Hoai Nam
  • Publication number: 20130308893
    Abstract: A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd1) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd1). The driver circuit may include a cascode stage (M3) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd2) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M5, M6) to couple a control terminal of an active load transistor (M9) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).
    Type: Application
    Filed: December 1, 2011
    Publication date: November 21, 2013
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Maurizio Zuffada, Massimo Pozzoni, Angelo Contini
  • Publication number: 20130307619
    Abstract: A traveling wave amplifier (TWA) with suppressed jitter is disclosed. The TWA includes a plurality of unit amplifiers with the differential arrangement comprised of a pair of transistors and a cascade transistors connected in series to the switching transistors. The unit amplifiers further includes current sources to provide idle currents to the cascade transistors. Even when the switching transistors fully turn off, the idle currents are provided to the cascade transistors, which set the operating point of the cascade transistor in a region where an increase of the base-emitter resistance is suppressed.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 21, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Taizo TATSUMI, Keiji TANAKA, Sosaku SAWADA
  • Patent number: 8582787
    Abstract: Described herein is a preamplifier circuit for a capacitive acoustic transducer provided with a MEMS detection structure that generates a capacitive variation as a function of an acoustic signal to be detected, starting from a capacitance at rest; the preamplifier circuit is provided with an amplification stage that generates a differential output signal correlated to the capacitive variation. In particular, the amplification stage is an input stage of the preamplifier circuit and has a fully differential amplifier having a first differential input (INP) directly connected to the MEMS detection structure and a second differential input (INN) connected to a reference capacitive element, which has a value of capacitance equal to the capacitance at rest of the MEMS detection structure and fixed with respect to the acoustic signal to be detected; the fully differential amplifier amplifies the capacitive variation and generates the differential output signal.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: November 12, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Filippo David, Igino Padovani
  • Patent number: 8576214
    Abstract: A circuit that obtains a more accurate, output voltage from a plurality of input voltages is provided. A two-input single-output circuit includes a current source transistor allowing a predetermined current to flow, a cascode transistor section including two MOS transistors that are cascode-connected to the drain side of the current source transistor and have the same characteristics, a differential pair section having a first differential pair formed of a first input-side transistor and a first output-side transistor whose source lines are shared and a second differential pair formed of a second input-side transistor and a second output-side transistor whose source lines are shared, and a current mirror circuit section. Drain lines of the transistors of the cascade transistor section are respectively connected to the source lines of the first and second differential pairs.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: November 5, 2013
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hiroko Sehata, Kouichi Kotera, Yoshihiro Kotani, Shuuichirou Matsumoto
  • Publication number: 20130278335
    Abstract: A hard drive write preamplifier includes a first differential pair of PNP BJTs having a first PNP BJT and a second PNP BJT; a first tail current source coupled into emitter of the PNP BJTs of the first differential pair; a second differential pair of NPN BJTs having a first NPN BJT and a second NPN BJT; a second tail current source coupled into the emitters of the NPN BJTs of the second differential pair; wherein a collector of each of the PNP BJTs of the first differential pair are coupled to a corresponding collector the NPN BJTs of the second differential pair; a first shift up PNP BJT having emitter coupled to the collector of a first PNP BJT of the first differential pair; a second shift up PNP BJT having an emitter coupled to the collector of the second PNP BJT of the first differential pair.
    Type: Application
    Filed: August 9, 2012
    Publication date: October 24, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jeremy Robert Kuehlwein
  • Patent number: 8565675
    Abstract: A near field RF communicator has an antenna circuit (120) to receive a modulated radio frequency signal by inductive coupling and demodulation circuitry (130 or 131) to extract the modulation from a received modulated radio frequency signal inductively coupled to the antenna circuit. The demodulation circuitry has a virtual earth input comprising a current mirror. The demodulation circuitry may be formed by an amplifier (115 or 116) and a demodulator (114) coupled to an output of the amplifier. The amplifier may be a single input amplifier (116) coupled to an output of the antenna circuit or may be a differential amplifier (115) having first and second inputs to receive the modulated radio frequency signal from first and second outputs of the antenna circuit, with each amplifier input providing a virtual earth input.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: October 22, 2013
    Assignee: Broadcom Innovision Limited
    Inventors: Joakim Bangs, David Miles
  • Publication number: 20130265108
    Abstract: An Extremely High Frequency (EHF) dual-mode PA with a power combiner is designed using 40-nm bulk CMOS technology. One of the unit PAs can be switched off for the low power applications. In the design, circuit level optimization and trade-off are performed to ensure the good performance in both modes. The PA achieves a PSAT of 17.4 dBm with 29.3% PAE in high power mode and a PSAT of 12.6 dBm with 19.6% PAE in low power mode. The reliability measurements are also conducted and a lifetime of 80613 hours is estimated based on a commonly used empirical model. The excellent performance (e.g., highest reported PAE) achieved in this design further confirms the scaling of CMOS technology will continue to benefit the mm-wave transceiver design.
    Type: Application
    Filed: August 21, 2012
    Publication date: October 10, 2013
    Applicant: ST-Ericsson SA
    Inventors: Joos Dieter, Wim Philibert, Patrick Reynaert, Dixian Zhao
  • Patent number: 8554162
    Abstract: A power amplifier circuit utilizes a cross-coupled tapped cascade topology together with a technique of applying an RF injection current into a wideband node to provide a single-stage power amplifier with improved PAE, output power, and gain over a wide RF band. The amplifier circuit comprises a cross-coupled cascade transistor unit comprising a pair of cross-coupled cascode transistors, a cross-coupled switching transistor unit comprising a pair of cross-coupled switching transistors, and an RF current generator. RF current generator generates a differential RF injection current, while switching transistor unit amplifies the injection current to generate an amplified injection current at the wideband node of the amplifier circuit and the cascode transistor unit further amplifies the injection current to generate the desired amplified signal at the output of the amplifier circuit.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: October 8, 2013
    Assignee: ST-Ericsson SA
    Inventors: Jonas Lindstrand, Carl Bryant, Henrik Sjöland
  • Publication number: 20130257637
    Abstract: A folded cascode operational amplifier includes a constant current source to output a constant current; a differential input stage to output a part of the constant current as a differential current based on a voltage difference between voltages input to an inverting input terminal and a non-inverting input terminal, and connected to the constant current source; and an output stage to output a remaining current obtained by subtracting the differential current from the constant current as an output stage current, and connected parallel to the differential input stage facing the constant current source.
    Type: Application
    Filed: January 7, 2013
    Publication date: October 3, 2013
    Inventor: Kunihiko GOTOH
  • Publication number: 20130257534
    Abstract: An input receiver circuit including a single-to-differential amplifier and a semiconductor device including the input receiver circuit are disclosed. The input receiver circuit includes a first stage amplifier unit and a second stage amplifier unit. The first stage amplifier unit amplifies a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage. The second stage amplifier unit amplifies the differential output signal in a differential-to-single mode to generate a single output signal.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 3, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Chul CHO, Yoon-Joo EOM, Young-Jin JEON, Yong-Cheol BAE
  • Publication number: 20130249632
    Abstract: A transconductance circuit that improves linearity and output current over a wider range of input voltages than prior designs. The transconductance circuit may include first and second sets of paired differential transistors. In each set, emitters of the paired transistors may be commonly coupled to corresponding nodes of a common impedance, and collectors may be coupled to output terminals of the transconductance circuit. The circuit may further include first and second sets of doublet differential transistor pairs, each doublet pair having transistors of different sizes. Each doublet pair may have current sources coupled between commonly coupled emitters and a source potential. Respective collectors for each doublet pair may be coupled to the output terminals of the transconductance circuit. A pair of voltage followers may be provided to replicate corresponding input voltages across corresponding bases of the differential transistor pairs and the doublet transistor pairs.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventor: Sandro HERRERA
  • Patent number: 8536944
    Abstract: A programmable current driver provides de-emphasis capability. A number of identical transmitter slices, consisting of a unit current source and a unit differential pair, are connected in parallel to the termination resistors. As the transmitter slices are identical, the current density through the differential pairs are identical, and the VDS voltages across them (as well as the VDS voltages across the unit current sources) are the same, ensuring that the current through each slice is identical (within the limits of device matching). Biasing circuitry ensures that each unit current source sinks a current having a fixed proportion to the total current.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: September 17, 2013
    Assignee: Cavium, Inc.
    Inventor: Mark Spaeth
  • Patent number: 8536945
    Abstract: A differential output stage configured for receiving differential input signal comprising first and second signals, comprising a first output for providing a first output signal, and a second output providing a second output signal, the first and second output signals together forming a differential output signal, a first voltage buffer and first controlled current source each connected to the first output, the first voltage buffer being driven by a signal in-phase with the first input signal, the first controlled current source being driven by a signal in-phase with the second input signal, and a second voltage buffer and second controlled current source each connected to the second output, the second voltage buffer being driven by a signal in-phase with the second input signal, the second controlled current source being driven a signal in-phase with by the first input signal.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: September 17, 2013
    Assignee: NXP B.V.
    Inventor: Gian Hoogzaad
  • Patent number: 8519785
    Abstract: A differential amplifier replicates the input stage and cross-connects the inputs, so that the input-to-output delay will be balanced in an averaged sense. The outputs of each of the two input stages are then summed after an open loop delay matched inversion has taken place. The result is a reduction in the duty cycle distortion of the receiver amplifier over process voltage and temperature (PVT) variation. This is enabled by the fact that a full swing CMOS delay cell can be made to have good delay matching over PVT, whereas the input stage to a differential amplifier may, depending on architecture, have poor delay matching because of impedance mismatches within the amplifier.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: August 27, 2013
    Assignee: Cavium, Inc.
    Inventor: Scott Meninger
  • Patent number: 8521221
    Abstract: A dual mode RF transceiver is provided. The dual mode RF transceiver comprises an antenna, a differential low noise amplifier (LNA), a local oscillator and a dual mode differential mixer. The differential LNA receives an RF signal from the antenna to generate a differential amplified RF signal. The dual mode differential mixer comprises a switch module, a plurality of fundamental mixers and a plurality of sub-harmonic mixers. The fundamental mixers are activated in a first receiving mode to generate a first differential baseband signal according to a multiphase local oscillating (LO) signal from the local oscillator and the differential amplified RF signal. The sub-harmonic mixers are activated in a second receiving mode to generate a second differential baseband signal according to the multiphase LO signal from the local oscillator and the differential amplified RF signal. An RF signal receiving method is disclosed herein as well.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: August 27, 2013
    Assignee: National Taiwan University
    Inventors: Shey-Shi Lu, Hsien-Ku Chen
  • Publication number: 20130207719
    Abstract: The present disclosure relates, according to some embodiments, to a transformer power amplifier that allows for improved Q values and increased efficiency by reducing the capacitance coupling effect between metal layers and/or sidewalls of the same layer through carefully designed conductor structures in primary and secondary loops. A transformer power amplifier comprises a substrate, a conductor, a circular coil, a first amplifier, and a second amplifier, the conductor and the circular coil disposed on the substrate. A circular coil has a first input terminal and a second input terminal, in which the first input terminal and the second input terminal are spaced apart and opposite each other to form an opening. A first amplifier is connected to a first input terminal for receiving a first signal and a second amplifier is connected to a second input terminal for receiving a second signal, wherein the first signal and the second signal are differential signals.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 15, 2013
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventor: NATIONAL TAIWAN UNIVERSITY
  • Patent number: 8503960
    Abstract: An amplifier receives an input signal with an input node, provides an output signal in response, and includes a main branch and an auxiliary branch. The auxiliary branch is coupled between the input node and a splitting node for input matching of the input node. The main branch, also coupled to the splitting node, has an output node of current mode, and is arranged to output the output signal at the output node. An associated receiver is also disclosed.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: August 6, 2013
    Assignee: Mediatek Singapore PTE. Ltd.
    Inventors: Fei Song, Chun-Geik Tan