Including Differential Amplifier Patents (Class 330/252)
  • Patent number: 9236841
    Abstract: An integrated, fully-differential current-feedback transimpedance operational amplifier circuit is disclosed. The circuit can be configured as a class-AB, low-impedance input stage, followed by an inverter-based, rail-to-rail output stage. For enhancing the open-loop transimpedance gain of the amplifier without consuming additional DC power, the same bias current is used both in the input stage and in a gain-enhancement stage serving as its load. The gain-enhancement stage can be either DC- or AC-coupled to the input of the amplifier. In the case of DC coupling, an output common-mode feedback loop can be used to provide the proper operating voltages in the amplifier.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: January 12, 2016
    Assignee: Analog Devices, Inc.
    Inventor: Alexandru A. Ciubotaru
  • Patent number: 9236855
    Abstract: A comparator has a differential pair circuit and a current control circuit. The differential pair circuit has first and second comparator transistors, and is arranged to compare a first input and a second input according to a clock signal to generate a result indicating whether a difference of the first and second inputs exceeds an internal offset. The current control circuit is coupled in series with the differential pair circuit, and configured to provide unequal abilities of drawing currents for the first and second comparator transistors. An amplifier circuit is also disclosed, having a differential pair circuit, a current control circuit, an amplification circuit and a reset circuit.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: January 12, 2016
    Assignee: MEDIATEK INC.
    Inventor: Yun-Shiang Shu
  • Patent number: 9197195
    Abstract: A driver includes a first driver stage having a first T-coil structure. The first T-coil structure includes a first set of inductors each being operable to provide a first inductance. The first T-coil structure further includes a second set of inductors electrically coupled with the first set of inductors, wherein the second set of inductors each are operable to provide a second inductance.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: November 24, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Tao Wen Chung, Chan-Hong Chern, Chih-Chang Lin, Yuwen Swei, Chiang Pu
  • Patent number: 9179137
    Abstract: A gate driver and an organic light emitting diode (OLED) display including the gate driver are disclosed. The gate driver includes a shift register block including a plurality of cascade-connected shift registers, a selection block including a plurality of selection units, which are respectively connected to the plurality of shift registers, and a buffer block including a plurality of buffers, which are respectively connected to the plurality of selection units. Each of the shift registers outputs a scan pulse, whose a phase is shifted by one horizontal period, in response to a start voltage, a first clock, a second clock, and a third clock.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 3, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Hyunhaeng Lee, Kisu Park, Joongsun Yoon
  • Patent number: 9103860
    Abstract: A system for measuring electrical charge, comprising a capacitance detector (110) connected to a charge integrator (120) being an operational amplifier with a capacitance feedback (130), in which the input stage (121) of the charge integrator (120) comprises a pair of symmetrically connected JFET-type transistors (T1; T2), having gates connected to the input of the charge integrator (120).
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: August 11, 2015
    Assignee: UNIWERSYTET JAGIELLONSKI
    Inventors: Zbigniew Sosin, Maciej Sosin, Marek Adamczyk
  • Patent number: 9054657
    Abstract: In an amplifier, a first stage receives a differential input voltage, which is formed by first and second input voltages, and outputs a first differential current in response thereto on first and second lines having respective first and second line voltages. A second stage receives the first and second line voltages and outputs a second differential current in response thereto on third and fourth lines having respective third and fourth line voltages. A third stage receives the third and fourth line voltages and outputs an output voltage in response thereto. A slew boost circuit detects a slew condition, in which a threshold difference arises between the first and second input voltages, and outputs a slew current in response thereto for maintaining a slew rate of the output voltage during the slew condition. The first stage includes circuits for reducing a variable difference between the first and second line voltages.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: June 9, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vaibhav Kumar, Vadim Valerievich Ivanov
  • Publication number: 20150130539
    Abstract: A quasi-differential amplifier with an input port and an output port. The amplifier has a phase shifter network with a first port connected to the input port, a second port, and a third port. A first amplifier has an input connected to the second port of the phase shifter network, and an output, and a second amplifier has an input connected to the third port of the phase shifter network, and an output. A balun circuit includes a first differential port connected to an output of the first amplifier, a second differential port connected to an output of the second amplifier, and a single-ended port. An output matching network is connected to the single-ended port of the balun circuit and to the output port.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 14, 2015
    Inventor: OLEKSANDR GORBACHOV
  • Publication number: 20150130536
    Abstract: A mixer comprising a ladder having at least two resistances arranged in series and an input configured to receive an input signal and apply it across the ladder, said ladder including an output arrangement comprising at least three branches, a first branch branching from a first end of the ladder, a second branch branching from between the at least two resistances and a third branch branching from a second end of the ladder, opposite the first end, each branch including a switch for controlling a connection between its branch and an output.
    Type: Application
    Filed: October 28, 2014
    Publication date: May 14, 2015
    Inventor: Robert Hendrikus Margaretha van Veldhoven
  • Patent number: 9031517
    Abstract: The present invention discloses a transmit-receive (TR) front end. The TR front end includes a low-noise amplifier (LNA); a power amplifier (PA); a transformer, coupled to the PA, for increasing a voltage swing and a power transmission of the PA; and a TR switch, coupled between the transformer and the LNA. The LNA is single ended and there is no transformer between the LNA and the TR switch.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: May 12, 2015
    Assignee: Mediatek
    Inventors: Albert Chia-Wen Jerng, Wen-Kai Li, Chien-Cheng Lin
  • Patent number: 9019013
    Abstract: Provided is a power amplifier which includes: a first transistor and a second transistor each having a first end connected to a first power source supplying a first voltage and to which signals having a same size but opposite polarities are input; a third transistor and a fourth transistor having first ends respectively connected to the first ends of the first transistor and the second transistor; and a fifth transistor having a first end connected to second ends of the third and fourth transistors and controlling oscillation of the third or fourth transistor.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: April 28, 2015
    Assignee: Soongsil University Research Consortium Techno-Park
    Inventors: Jong Hoon Park, Chang Kun Park
  • Publication number: 20150109007
    Abstract: A differential amplifier is described that provides a high common mode rejection ration (CMRR) without requiring the use of precisely matched components. One variation employs a method of noise reduction to increase the SNR of the device. The differential amplifier may be used in an apparatus for measuring biopotentials of a patient, such as an electrode for measuring brain activity. The electrodes can communicate the measured biopotentials with a remote system for further processing, while providing electrical isolation to the patient.
    Type: Application
    Filed: March 29, 2012
    Publication date: April 23, 2015
    Inventor: George Townsend
  • Patent number: 9007096
    Abstract: An apparatus relating generally to voltage conversion includes an amplifier coupled to receive an input voltage and a reference voltage. First and second converters are coupled to the amplifier to receive a bias voltage. The first converter includes a first transconductor coupled to receive the bias voltage to adjust a first tail current, and a first differential input. A first inverter of the first converter has a first feedback device coupled input-to-output to provide a first transimpedance amplifier load. The first inverter is coupled to the first transconductor. The second converter includes a second transconductor coupled to receive the bias voltage to adjust a second tail current, and a second differential input. A second inverter of the second converter has a second feedback device coupled input-to-output to provide a second transimpedance amplifier load. The second inverter is coupled to the second transconductor.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: April 14, 2015
    Assignee: Xilinx, Inc.
    Inventors: Declan Carey, Thomas Mallard, Mark Smyth, James Hudner
  • Patent number: 9008332
    Abstract: A processing chip for a digital microphone and related input circuit and a digital microphone are described herein. In one aspect, the input circuit for a processing chip of a digital microphone includes: a PMOS transistor, a resistor, a current source, and a low-pass filter. The described processing chip possesses high anti high-frequency interference capabilities and the described input circuit possesses high high-frequency power supply rejection ratio.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 14, 2015
    Assignee: Beijing KT Micro, Ltd.
    Inventors: Wenjing Wang, Jianting Wang, Rongrong Bai, Jing Cao
  • Publication number: 20150092510
    Abstract: According to at least one example embodiment, a method and corresponding system for calibrating an amplifier offset include applying an input value to both input leads of an amplifier. The amplifier includes one or more digital-to-analog converters (DACs) used to calibrate an offset of the amplifier. A digital value, provided as input to the DAC, is updated over a number of iterations, by a control logic coupled to the amplifier, based on an output of the amplifier. A final value of the digital value being updated, e.g., associated with the last iteration, is employed as input to the DAC of the one or more DACs in the amplifier for calibrating the offset of the amplifier during a data reception phase.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: Cavium, Inc.
    Inventors: Omer O. Yildirim, David Lin, Scott E. Meninger
  • Patent number: 8994451
    Abstract: An RF amplifier suitable for use in an RF transceiver has a circuit including a first transistor pair with the collector of each coupled to one of the two differential output nodes and a common base. A pair of Ft doublers is provided with the emitter of each Ft doubler coupled to one of the transistors in the first transistor pair. Each Ft doubler has a common emitter and a base coupled to one of the differential input nodes. As such, the first transistor pair and the Ft doubler pair are cascode-coupled to provide a wide bandwidth, high gain, and high input impedance RF amplifier.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Rockwell Collins, Inc.
    Inventors: Russell D. Wyse, Michael L. Hageman, Max S. Hawkins, Jr.
  • Patent number: 8988173
    Abstract: A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as “non-Foster circuits.” The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: March 24, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Donald A. Hitko, Carson R. White, Michael W. Yung, David S. Matthews, Susan L. Morton, Jason W. May, Joseph S. Colburn
  • Patent number: 8988148
    Abstract: A transconductance amplifier has a pair of input terminals and a pair of output terminals. A first pair of transconductors is connected to the input terminals and the output terminals. A second pair of transconductors has inputs connected to output terminals, and outputs connected to the opposing output terminals. A third pair of transconductors has both its inputs and its outputs connected to the output terminals. One or more of the transconductors have a control port for a control signal to adjust its transconductance. The control signal may switch the transconductance of this or these transconductors between two or more values. One or more of the transconductors in the transconductance amplifier may include a tri-state inverter, which may be enabled or disabled through a control port.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 24, 2015
    Inventors: Julian Jenkins, Torsten Lehmann, James Paul Koeppe
  • Publication number: 20150078420
    Abstract: An amplification circuit (100) comprising a first filter (102) and an LNA (110). The first filter (102) comprising an input (104) for receiving an input signal; a first differential output (106); and a second differential output (108). The first filter (102) has a differential mode of operation for frequencies in its pass-band (706, 806) and a common mode of operation for frequencies outside its pass-band (706, 806), and may be an acoustic wave filter. The LNA (110) comprising a first differential input (112) connected to the first differential output (106) of the first filter (102); a second differential input (114) connected to the second differential output (108) of the first filter (102); and an output (116) for providing an amplified output signal.
    Type: Application
    Filed: July 29, 2014
    Publication date: March 19, 2015
    Inventors: Marcel Geurts, Louis Praamsma, Michel Groenewegen, Rainier Breunisse, Freek van Straten, Robert Buytenhuijs
  • Patent number: 8981798
    Abstract: An electronic system comprises a resistive sensor structure and an electronic circuit portion whose design is selected such that different resistive sensor structures may be combined within the same electronic circuit. To this end, the resistive sensor structure is used as a voltage/current converter that provides input currents to a current amplifier, which in turn provides an amplified output voltage on the basis of a difference of the input currents. The operating range of the current amplifier is adjusted on the basis of a programmable current source irrespective of the configuration of the resistive sensor structure.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: March 17, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Antonino Scuderi
  • Publication number: 20150063048
    Abstract: A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Lin, Hung-Chang Yu, Yue-Der Chih
  • Publication number: 20150016205
    Abstract: A semiconductor circuit includes a first input section into which a first input signal is inputted, a second input section into which a second input signal is inputted, an output generation circuit which is connected to the first and second input sections and generates an output signal based on the input signals, an output section which outputs the output signal, and a current source which is connected to connection nodes between the input sections and the output generation circuit.
    Type: Application
    Filed: February 25, 2014
    Publication date: January 15, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masatoshi KOHNO, Masami MASUDA, Mikihiko ITO, Masaru KOYANAGI
  • Patent number: 8933754
    Abstract: A differential amplifier provides an amplifier circuit including two differential pairs. A first differential pair is connected in series to a second differential pair. The second differential pair is connected in a crosswise manner at least indirectly to a differential output signal of the first differential pair. The first differential pair and the second differential pair form a first differential current path and a second differential current path. A first emulation device is connected in parallel to the first current path. A second emulation device is connected in parallel to the second current path.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: January 13, 2015
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Oliver Landolt
  • Publication number: 20150008981
    Abstract: A repair operational amplifier circuit including a repair operational amplifier and a slew rate enhancing module. The repair operational amplifier includes an input terminal and an output terminal. The input terminal is used to receive an input signal. The output terminal is used to output an output signal. The slew rate enhancing module is coupled to the input terminal and the output terminal of the repair operational amplifier and used to selectively control the repair operational amplifier to increase a slew rate of the output signal according to whether the slew rate of the output signal is smaller than a default slew rate.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 8, 2015
    Inventors: Po-Cheng LIN, Yu-Lung LO
  • Publication number: 20150002222
    Abstract: First and second transconductance amplifier input stages having first and second gain characteristics, respectively, are combined. The resulting combined input stage has a third gain characteristic with a linear range that is larger than a linear range of either of the first and second gain characteristics.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Sanjeev Manandhar, Gary S. Gibson
  • Publication number: 20140368371
    Abstract: An amplifier includes a common load suitable for outputting an output signal, a coarse input differential stage, coupled to the common load, suitable for amplifying a difference between an input signal and a coarse ramping signal to output a coarse conversion signal as a first output signal, when the coarse ramping signal is lower than the input signal, and a fine input differential stage, coupled to the common load, suitable for amplifying a difference between a fine ramping signal and a bias signal and compensating the first output signal to output a fine conversion signal as the output signal, when a zero crossing occurs by the compensated first output signal.
    Type: Application
    Filed: October 11, 2013
    Publication date: December 18, 2014
    Applicant: SK hynix Inc.
    Inventor: Si-Wook YOO
  • Publication number: 20140368270
    Abstract: A Marchand balun has a primary transmission line with a width smaller than the two secondary transmission lines. The two secondary transmission lines also have different widths and lengths. This arrangement provides an imbalance between the widths and lengths of the transmission lines. It has been found that this imbalance can enable improved amplitude unbalance and phase unbalance.
    Type: Application
    Filed: June 10, 2014
    Publication date: December 18, 2014
    Applicant: NXP B.V.
    Inventors: Gerard Jean-Louis Bouisse, Rajeev Busgeeth
  • Patent number: 8907725
    Abstract: Apparatus and methods for reducing load-induced non-linearity in amplifiers are provided. In certain implementations, an amplifier includes a current mirror, a buffer circuit, and an output stage. The buffer circuit can have a relatively high current gain and a voltage gain about equal to 1. The buffer circuit can amplify a mirrored current generated by the current mirror and provide the amplified mirrored current to the output stage, thereby helping to balance or equalize currents in the current mirror and avoiding the impact of load-induced offset error.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Moshe Gerstenhaber, Rayal Johnson
  • Publication number: 20140354357
    Abstract: An apparatus is provided that includes first and second ICs configured to communicate using a plurality of differential signal lines. The apparatus includes a common mode suppression circuit having a plurality of common mode voltage adjustment circuits, each configured to provide a low impedance path for common mode signals and a high impedance path for differential AC signaling, thereby suppressing the effect of common mode transients between the voltage domains. The plurality of common mode voltage adjustment circuits each have components that are impedance matched up to an impedance-tolerance specification. The common mode suppression circuit also includes an AC coupling circuit configured to be less dependent on impedance mismatch, beyond the impedance-tolerance specification, by cross coupling the impedance differentials from each of the differential signal lines through the AC coupling circuit and to one of the common mode voltage adjustment circuits.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Inventor: Rameswor Shrestha
  • Patent number: 8890051
    Abstract: A photodetecting device 1 includes a photodiode PD and an integrating circuit 10. The integrating circuit 10 includes an amplifier circuit 20, a capacitive element C, a first switch SW1, and a second switch SW2. The second switch SW2 is provided between a reference potential input terminal to which a reference potential Vref is input and a terminal of the capacitive element C on the inverting input terminal side of the amplifier circuit 20, and the second switch is opened or closed according to the level of a second reset signal Reset2, and is capable of applying the reference potential Vref to the terminal of the capacitive element. Thus, an integrating circuit and a photodetecting device capable of achieving both low power consumption and high speed can be realized.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: November 18, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Haruhiro Funakoshi, Shinya Ito
  • Patent number: 8878608
    Abstract: A comparator has a differential pair circuit, a current control circuit, and a latch. The differential pair circuit has first and second comparator transistors, and is arranged to compare a first input and a second input according to a clock signal to generate a result indicating whether a difference of the first and second inputs exceeds an internal offset. The current control circuit is coupled in series with the differential pair circuit, and configured to provide unequal abilities of drawing currents for the first and second comparator transistors.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 4, 2014
    Assignee: MediaTek Inc.
    Inventor: Yun-Shiang Shu
  • Patent number: 8872585
    Abstract: An amplifier for detecting photocurrents complementary to each other is disclosed. The optical receiver includes two trans-impedance amplifiers (TIAs) each having the single phase arrangement, a level detector to detect an average level between respective outputs of the TIAs, a controller to detect a difference between each of the output of the TIA, and an offset canceller to bypass each of the photocurrents to compensate the output offset between two TIAs depending on the average level and the difference between two levels.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yoshiyuki Sugimoto
  • Patent number: 8872587
    Abstract: Apparatuses for generating negative impedance compensation are provided. Embodiments include a differential amplifier having a first output and a second output; a capacitor coupled between the first output and the second output of the differential amplifier; a first negative impedance cross-coupled circuit having a first output and a second output; and a resistance control circuit coupled in series between the first output and the second output of the differential amplifier and the first output and the second output of the first negative impedance cross-coupled circuit.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Rajesh Cheeranthodi, John F. Ewen, Santhosh Madhavan, Giri N. K. Rangan, Umesh K. Shukla, Sarabjeet Singh
  • Patent number: 8860507
    Abstract: An amplifier includes a transformer and a first stage gain circuit. The transformer includes a primary coil and a secondary coil. The primary coil is utilized for receiving an input signal. The first stage gain circuit has a first input port, which is coupled to the primary coil. The first stage gain circuit is utilized for gaining the input signal so as to generate a first output.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 14, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hsien-Ku Chen, Chia-Jun Chang, Ka-Un Chan, Ying-Hsi Lin
  • Publication number: 20140292409
    Abstract: An amplification circuit that can reduce an area without using transistors with a high withstand voltage. The amplification circuit (100) includes: an operational amplifier with a first input terminal connected to a reference node; a first capacitor (CA1) provided between a first node and the reference node; a second capacitor (CA2) provided between a second node and the reference node; a switch element (SW1) provided between the first node and an input node of an input voltage; a switch element (SW2) provided between the first node and a supply node of a first analog reference voltage; a switch element (SW3) provided between the second node and an output node of an output voltage; a switch element (SW4) provided between the second node and a supply node of a second analog reference voltage; and a switch element (SW5) provided between the output node of the output voltage and the reference node.
    Type: Application
    Filed: March 18, 2014
    Publication date: October 2, 2014
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Motoaki NISHIMURA
  • Patent number: 8847812
    Abstract: In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from ?(2n-1?1) to +(2n-1?1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: September 30, 2014
    Assignee: Panasonic Corporation
    Inventors: Shiro Dosho, Takuji Miki
  • Patent number: 8841968
    Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of a radio frequency (RF) signal input, the RF signal input including an output of a radio such as a cellular transmitter (TX). The ED further includes multiple voltage amplifiers positioned serially in gain stages between the TX output and the ED core to provide a total linear voltage range of the envelope detector. A final voltage amplifier of the multiple voltage amplifiers drives the ED core and includes a class-AB RF amplifier configured to operate within a full linear voltage range of the ED core.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: September 23, 2014
    Assignee: Broadcom Corporation
    Inventors: Amir Hadji-Abdolhamid, Janice Chiu
  • Patent number: 8829991
    Abstract: This document discusses, among other things, an amplifier circuit including first and second amplifiers configured to receive an input signal and to provide a differential output signal using a feedback loop including a transconductance amplifier. A non-inverting input of a first amplifier can be configured to receive an input signal. The feedback loop can be configured to receive the outputs from the first and second amplifiers and to provide a feedback signal to the non-inverting input of the second amplifier, for example, to reduce a DC offset error or to increase a dynamic range of the amplifier circuit.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Andrew M. Jordan, Hrvoje Jasa
  • Publication number: 20140240041
    Abstract: Provided is an operational amplifier circuit capable of operating with lower current consumption. An amplifier stage, a FIR filter, and a sample and hold circuit are connected in series, thus enabling reduction of an input offset voltage and amplification of an input signal voltage without using an integral circuit. Current consumption of the operational amplifier circuit is reduced because the integral circuit is not used.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 28, 2014
    Applicant: Seiko Instruments Inc.
    Inventor: Tsutomu TOMIOKA
  • Publication number: 20140240044
    Abstract: An operational amplifier has two paths, a high frequency path and a low frequency path. In addition, it has three main sections of stages. A stage converts input voltage to an amplified output voltage, a stage converting an input voltage in to an output current and a final stage where the outputs of the two previous sections are supplied as inputs. Among them, the final stage acts as a voltage follower to a signal applied to its plus (+) input and as a transimpedance amplifier for a signal applied to its minus input (?). In this configuration, a path for low frequencies and a path for high frequencies are created in a single operational amplifier.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 28, 2014
    Inventor: Takashi NARITA
  • Publication number: 20140240278
    Abstract: A touch sensing apparatus is provided. The touch sensing apparatus includes a touch panel and a touch sensor configured to control the touch panel and sense a touch through the touch panel. The touch sensor includes a plurality of sensing units connected to the touch panel through a plurality of sensing lines respectively. Each of the plurality of sensing units includes at least an operational amplifier whose polarity varies in response to a clock signal.
    Type: Application
    Filed: December 19, 2013
    Publication date: August 28, 2014
    Inventors: Ki-Duk Kim, Junchul Park, San-Ho Byun, Minchul Lee, Ji-Sung Jung, Yoonkyung Choi
  • Publication number: 20140240042
    Abstract: There is provided an operational amplifier capable of detecting that an input terminal has been open circuited without restricting the voltage range of an input signal. The operational amplifier includes a first comparator which detects that an inverting input terminal of an operational amplifier has been open circuited, a second comparator which detects that a non-inverting input terminal of the operational amplifier has been open circuited, a first resistor and a first switch which are controlled by output signals of the first comparator and the second comparator and which are connected in series between the non-inverting input terminal and a ground terminal of the operational amplifier, and a second resistor and a second switch which are connected in series between the inverting input terminal and a supply terminal of the operational amplifier.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 28, 2014
    Applicant: Seiko Instruments Inc.
    Inventor: Toshiyuki TSUZAKI
  • Patent number: 8817670
    Abstract: Duplex communications are facilitated. In connection with various example embodiments, current sources are used to drive transistor-based circuits coupled across a first resistive circuit, to send signals on a communications medium. While driving the transistor-based circuits, the current sources are used to drive reference transistor-based circuits coupled across a second resistive circuit. A differential output signal based upon a power-related value across the first resistive circuit, less a power-related value across the second resistive circuit. This differential output signal characterizes a power-related value corresponding to a received signal on the communications medium, as gleaned from a total signal corresponding to both transmitted and received signals, less a signal corresponding to the transmitted signal.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: August 26, 2014
    Assignee: NXP B.V.
    Inventors: Sujan Pandey, Hubertus Gerardus Hendrikus Vermeulen, Abhijit Kumar Deb
  • Patent number: 8816773
    Abstract: Apparatus and methods are disclosed related to trimming an input offset current of an amplifier. One such apparatus can include auxiliary bipolar transistors connected in parallel with bases of respective bipolar transistors of an input stage of an amplifier. The auxiliary bipolar transistors can be biased such that the base currents of the auxiliary bipolar transistors compensate for a mismatch in base currents of the bipolar transistors of the input stage of an amplifier. The offset current at an input of an amplifier can be reduced independent of an offset voltage at the input of the amplifier.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: August 26, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Moshe Gerstenhaber, Rayal Johnson
  • Patent number: 8818302
    Abstract: Tank circuitry coupled to the output terminals of a differential power amplifier includes two trap circuits configured to divert harmonic signals away from the output terminals. A tank inductor is provided to form a tank circuit in conjunction with each one of the trap circuits. At certain harmonic frequencies of the input signal to the differential power amplifier, the trap circuits are resonant and present a substantially low impedance path to ground, thereby diverting harmonic signals away from the output terminals of the differential power amplifier. At the fundamental frequency of the input signal to the differential power amplifier, the trap circuits are resonant with the tank inductor and present a substantially high impedance compared to the load impedance presented at the output terminals of the differential power amplifier, thereby reducing the loading effect of the trap circuits at the fundamental frequency.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: August 26, 2014
    Assignee: RF Micro Devices, Inc.
    Inventor: Ali Tombak
  • Publication number: 20140232460
    Abstract: One embodiment relates to an apparatus configured to cancel charge injected on a node of a differential pair of nodes. A dummy circuit element can inject charge on an inverted node to cancel charge injected on a non-inverted node by a switch when the switch is switched off. In addition, another dummy circuit element can inject charge on the non-inverted node to cancel charge injected on the inverted node by another switch when the other switch is switched off. These dummy circuits elements can be cross-coupled.
    Type: Application
    Filed: February 15, 2013
    Publication date: August 21, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: Scott G. Bardsley, Peter Derounian, Franklin M. Murden
  • Publication number: 20140218110
    Abstract: A sensing amplifier using capacitive coupling and a dynamic reference voltage, where the sensing amplifier circuit includes a bit line, configured to receive charging and discharging signals; a sensing amplifier, connected to the bit line and configured to receive the bit line and a reference voltage for comparison and configured to enlarge the voltage difference between a high point and a low point; and a reference voltage generator, connected to the sensing amplifier to generate the reference voltage required for the sensing amplifier to compare. The sensing amplifier effectively enhances sensing margin of the sensing amplifier circuit; and in addition, to accelerate the access speed, the sensing amplifier can easily determine the correct stored data and further quickly solve the problems of high-speed storing the data by the storage units.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Jen Wu, Tun-Fei Chien, Meng-Fan Chang, Yu-Der Chih
  • Patent number: 8797100
    Abstract: Circuit unit (CU) comprising a heterojunction bipolar transistor and a long-gate pseudomorphic high-electron-mobility transistor. Either a source (S) or a drain (D) of the long-gate pseudomorphic high-electron-mobility transistor is electrically coupled with either a collector (C) or an emitter (E) of the heterojunction bipolar transistor.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: August 5, 2014
    Assignee: Epcos AG
    Inventors: Bart Balm, Jeroen Bouwman, Léon C. M. van den Oever
  • Patent number: 8797202
    Abstract: An intelligent electronic device (IED), e.g., an electrical power meter having circuitry for an input voltage structure with an adjusting voltage divider, resulting in a highly accurate power measurement, is provided. The IED includes a first voltage input for receiving a sensed voltage from a first phase of an electrical distribution system, the first voltage input being coupled to a first voltage divider; a second voltage input for receiving a sensed voltage from a neutral phase of the electrical distribution system, the second voltage input being coupled to a second voltage divider; and an inverting operational amplifier (op amp) coupled to the first and second voltage inputs for providing an output proportional to the voltage of the first phase referenced to the neutral phase, wherein the first voltage divider is adjustable to match a ratio of the first voltage divider to a ratio of the second voltage divider.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: August 5, 2014
    Assignee: Electro Industries/Gauge Tech
    Inventors: Hai Zhu, Tibor Banhegyesi
  • Patent number: 8791758
    Abstract: Apparatus and methods for buffer linearization are provided. In certain implementations, an amplifier includes a buffer circuit and a gain circuit. The buffer circuit includes a buffer transistor pair used to buffer a differential input signal to generate a differential buffered signal. Additionally, the gain circuit includes a gain transistor pair configured to amplify the buffered differential signal to generate an amplified differential signal. The buffer circuit can include a linearization transistor pair configured to decrease the buffer circuit's output impedance and to provide feedback that reduces changes in the voltage of the differential buffered signal in response to displacement currents associated with the CJC or CGD capacitances of the gain transistor pair.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: July 29, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Omid Foroudi
  • Publication number: 20140203872
    Abstract: A differential cross-coupled common-source or common-emitter low-noise amplifier having capacitive degeneration is disclosed. Further, a radio receiver comprising such a low-noise amplifier is disclosed. Further, a method of controlling switched capacitive networks of an amplifier is disclosed. The method comprises controlling capacitances of the switched degeneration capacitor networks and/or the switched cross-coupling capacitor networks. Further, a computer program for implementing the method is disclosed.
    Type: Application
    Filed: July 10, 2012
    Publication date: July 24, 2014
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventor: Henrik Sjöland