Abstract: An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.

Abstract: In a solid-state imaging element provided with a differential pair of transistors, noise of a signal from the differential pair is reduced. The semiconductor integrated circuit includes a pixel circuit and a pair of TFETs (Tunnel Field Effect Transistors). In the semiconductor integrated circuit, the pixel circuit photoelectrically converts incident light to generate a pixel signal. Further, in the semiconductor integrated circuit, the pair of TFETs amplifies the difference between the pixel signal generated by the pixel circuit and a predetermined reference signal that changes with time, and outputs the amplified difference as a differential amplification signal.

Abstract: A dry cask storage system for spent nuclear fuel includes a detection apparatus having a resonant electrical circuit, with resonant electrical circuit being situated within an interior region of a metallic vessel wherein the SNF is situated. The detection apparatus includes a transmitter that generates an excitation pulse that causes the resonant circuit to resonate and to generate a response pulse. The resonant circuit includes an inductor that is formed with a core whose magnetic permeability varies with temperature such that the frequency of the resonant circuit varies as a function of temperature. The response pulse is then used to determine the temperature within the interior of the vessel where the SNF is situated. Pressure detection is also provided.

Abstract: The present general inventive concept is directed to a method and system to generate a power signal, including summing a non-inverted reference signal and an inverted feedback signal to output a non-inverted first summation signal, summing an inverted reference signal and a non-inverted feedback signal to output an inverted second summation signal, receiving the first summation signal at a non-inverted input of a differential power output driver, and the second summation signal at an inverted input of the differential power output driver, outputting a non-inverted power signal to a first terminal of an impedance load from a non-inverted output of the differential power output driver, and outputting an inverted power signal to a second terminal of the load from an inverted output of the differential power output driver, the non-inverted power signal also being used as the non-inverted feedback signal, and the inverted power signal also being used as the inverted feedback signal.

Abstract: A system includes a pixel that emits light based on a signal provided to the pixel. The system may also include a buffer circuit having a differential pair stage, a cascade stage, and an output stage. The differential pair stage may receive a common mode voltage signal via a first switch in response to the first switch receiving a first signal that causes the first switch to close. The differential pair stage may couple a capacitor to the output stage via a second switch that operate based on a second signal, such that the capacitor reduces an offset provided by one or more circuit components in the differential pair stage, the cascade stage, the output stage, or any combination thereof. The differential pair stage may output the common mode voltage to the pixel via the output stage in response to the first signal being present.

Abstract: An operational amplifier 1 comprises transistors Q1 and Q2 forming an input stage, and input resistors R1 and R2 which form a filter together with parasitic capacitors C1 and C2 accompanying the transistors Q1 and Q2. Resistance values R of the resistors R1 and R2 may be set to R=1/(2?·fc·C), where C is the capacitance value of each of the parasitic capacitors C1 and C2, and fc is the target cutoff frequency of the filter. The operational amplifier 1 may also include a power supply resistor R0 which forms a filter together with a parasitic capacitor C0 accompanying a power supply line.

Abstract: A sensor failure prediction system is a sensor failure prediction system that predicts a failure of a physical quantity sensor including a vibrator element which is driven and vibrates by a drive signal and outputs a detection signal based on a physical quantity, and includes a memory that stores reference information on a reference value of the drive signal or the detection signal, and a processor that outputs prediction information on a stepwise or continuous state until the physical quantity sensor fails, based on signal information on a measurement value of the drive signal or the detection signal and the reference information.

Abstract: In one embodiment, an RF power amplifier includes a first transistor and a second transistor in parallel, wherein a gate of the first transistor and a gate of the second transistor are configured to be driven by an RF source. A third transistor comprising a drain is operably coupled to both a source of the first transistor and a source of the second transistor. A control circuit is operably coupled to a gate of the third transistor and configured to alter a gate-to-source voltage of the third transistor, thereby altering a drain current of each of the first transistor and the second transistor, thereby altering an output power of the RF power amplifier.

Abstract: A transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The transistor amplifier exhibits improved input impedance and improved linearity.

Abstract: Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.

Abstract: In some embodiments, a wireless local area network (WLAN) front-end can be implemented on a semiconductor die having a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to support the transmit and receive operations.

Abstract: A signal processing circuit includes a signal receiving circuit for generating a first input signal and a second input signal; a signal output circuit for generating a first output signal and a second output signal according to the first input signal and the second input signal; a negative impedance circuit, for amplifying the first input signal at the first input terminal to generate a first amplified input signal at the second output terminal, and for amplifying the second input signal at the second input terminal to generate a second amplified input signal at the first output terminal; a first capacitor; a second capacitor; wherein the first capacitor and the second capacitor have different DC voltage levels at both terminals, such that the impedance-signal variation rate of the negative impedance circuit is lower than a predetermined level.

Abstract: The present application provides an apparatus for processing signals of a high-voltage loop, a detector, a battery device, and a vehicle. The apparatus includes a filter circuit connected to an element to be detected and configured to filter signals from the element to be detected; a differential amplification circuit connected to the filter circuit and configured to amplify the filtered signals; and a processor connected to the differential amplification circuit and configured to process the amplified signals.

Abstract: A low voltage inverter-based amplifier includes a first inverter-based amplification module, a second inverter-based amplification module, an inverter-based feedforward module, and an inverter-based common mode detector. The first inverter-based amplification module receives an input signal. The second inverter-based amplification module receives the input signal through the inverter-based feedforward module, and receives a first output signal from the first inverter-based amplification module. The inverter-based common mode detector receives an amplified signal from the second inverter-based amplification module, and outputs a feedback signal to the second inverter-based amplification module. Since the first and the second inverter-based amplification modules are both inverter-based, the supply voltage of the low voltage inverter-based amplifier is provided to supply one PMOS and one NMOS for normal operation.

Abstract: An instrumentation amplifier configured for providing high common mode rejection is described and includes an input differential stage configured to receive a differential input voltage and a folded cascode amplifying stage configured to receive output current mode signals provided from the input differential pair. A plurality of feedback networks is provided to improve the input stage. The amplifier may operate to provide an enhanced common mode rejection ratio of a single gain block in the instrumentation amplifier. In some examples, the circuitry may have a differential folded cascode amplifying stage which permits high precision and low distortion of amplified signals without degrading the common mode rejection ratio.

Abstract: A negative-operand compatible subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes two sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of two sets of scaled capacitors electrically connected to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground. A control circuit of the subtractor is configured to, in conjunction with the reset circuit, draw the difference output node to a reset voltage.

Abstract: A circuit includes a first signal swapper including a first terminal coupled to a first current source, a second terminal coupled to a second current source, a third terminal coupled to a first current terminal of a first transistor, and a fourth terminal coupled to a third current terminal of a second transistor. The first signal swapper couples the first and second terminals to the third and fourth terminals responsive to a first control signal. First and second switches couple to a gate of the first transistor. The first switch receives the input oscillation signal and the second switch receives a first reference voltage. Third and fourth switches couple to a gate of the second transistor. The third switch receives the input oscillation signal and the fourth switch receives the first reference voltage. A second signal swapper couples to the first signal swapper and to the first and second transistors.

Abstract: A circuit for receiving signals in an integrated circuit device. The circuit comprises a first equalizer circuit having a first input for receiving a first input signal and generating an output signal at a first output; a second equalizer circuit having a second input for receiving the output signal generated at the first output of the first equalizer circuit and having a second output; and a control circuit having a control output coupled to the second output of the second equalizer circuit; wherein the control circuit provides an offset cancellation signal or a loopback signal to the second output of the second equalizer circuit. A method of receiving signals in an integrated circuit is also described.

Abstract: A preamplifier circuit includes a first transconductor and a floating transconductor. The first transconductor receives a differential voltage from a sample-and-hold circuit and drives the floating transconductor. The first and floating transconductors output amplified versions of the differential voltage that are not affected by capacitive division, which makes the preamplifier circuit fast. The preamplifier circuit also has a low input capacitance because the floating transconductor is not connected to any external circuitry.

Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.

Abstract: In a general aspect, a circuit can include an amplifier circuit including a first amplifier, a first feedback path, and a second feedback path. The first feedback path can provide a feedback path from a positive output of the first amplifier to a negative input of the first amplifier. The second feedback path can provide a feedback path from a negative output of the first amplifier to a positive input of the first amplifier, The circuit can also include a loop circuit including a second amplifier, The loop circuit can be configured to provide a local feedback loop for the first amplifier and configured to control current flow into the positive input of the first amplifier and into the negative input of the first amplifier.

Abstract: The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET) and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programmed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel/W/L of drain channel).

Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

Abstract: An operational amplifier with a constant transconductance bias circuit and a method thereof are introduced. The operational amplifier includes a differential difference amplifier and the constant transconductance bias circuit. The differential difference amplifier has at least one first differential transistor pair and at least one second differential transistor pair. The constant transconductance bias circuit is electrically connected to the differential difference amplifier, and configured to output a first bias voltage to bias the at least one first differential transistor pair and output a second bias voltage to bias the at least one second differential transistor pair. The first bias voltage and the second bias voltage are configured to maintain constant transconductance of the differential difference amplifier.

Abstract: The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET) and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programmed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel/W/L of drain channel).

Abstract: A low dropout (LDO) device with improved linear mode comprising an error amplifier, a programmable attenuation factor circuit coupled to said error amplifier, a feedback network whose input is electrically connected to said programmable attenuation factor circuit and whose output is electrically coupled to the negative input of said error amplifier, a high side (HS) pre-drive circuit whose input is a high impedance (HiZ) mode signal, a low side (LS) pre-drive circuit whose input is a low pull-down input mode signal, a high side (HS) output stage element electrically coupled to said high side (HS) pre-drive circuit, a low side (LS) output stage element electrically coupled to said low side (LS) pre-drive circuit, and a high side sense (HSENSE) output stage element whose gate is electrically coupled to said high side (HS) pre-drive circuit, and whose gate and source are electrically connected to the output of said error amplifier.

Abstract: A display device including a display unit which has a plurality of pixels and a plurality of driving lines for driving the plurality of pixels; a driving circuit which drives the plurality of pixels through the plurality of driving lines; and a control unit which adjusts a driving capability of the driving circuit according to the number of simultaneous driving lines of the driving circuit.

Abstract: Provided is an inductor structure. In embodiments of the invention, the inductor structure includes a first laminated stack. The first laminated stack includes layers of an insulating material alternating with layers of a first magnetic material. The inductor structure includes a laminated second stack formed on the first laminated stack. The second laminated stack includes layers of the insulating material alternating with layers of a second magnetic material. The second magnetic material has a greater permeability than does the first magnetic material.

Abstract: Radio frequency switch circuitry is disclosed having first and second port terminals, a switch branch having first and second branch terminals, and a branch control terminal, wherein the switch branch is configured to pass an RF signal between the first and second branch terminals in an on-state and block the RF signal from passing between the first and second branch terminals in an off-state in response to a control signal that is coupled with the RF signal and received at the first port terminal. Control signal decoupling circuitry has a control signal input terminal coupled to the first port terminal to receive the control signal coupled to the RF signal and a control signal output terminal coupled to the branch control terminal, wherein the control signal decoupling circuitry is configured to decouple the control signal from the RF signal and provide the control signal to the branch control terminal.

Abstract: A coil that includes compensation.

Abstract: An amplifying unit includes a converter and a feedback mechanism. The converter has a supply input coupled to a supply node. The converter further has an input terminal configured to receive an input signal. The converter is configured to amplify the input signal from the input terminal to generate an output signal. The feedback mechanism is coupled to the input terminal of the converter and is configured to cause a constant bias current to flow from the supply node through the converter based on the input signal.

Abstract: An amplifier system includes a main amplifier, a cross-over current detector and a controller. The main amplifier includes at least a first driving transistor and a second driving transistor serving as a differential pair, wherein the first driving transistor and the second driving transistor are arranged to receive a first input signal and a second input signal, respectively. The cross-over current detector is coupled to the main amplifier, and is arranged for detecting a cross-over current of the main amplifier, wherein the cross-over current of the main amplifier is an overlapped current from the differential pair. The controller is coupled to the main amplifier and the cross-over current detector, and is arranged for generating a control signal to control a gain of the main amplifier according to an output of the main amplifier and the cross-over current of the main amplifier.

Abstract: Certain aspects of the present disclosure generally relate to using cross-coupled transistors for source degeneration of an amplification stage. For example, the amplification stage generally includes a differential amplifier comprising transistors, cross-coupled transistors coupled to the differential amplifier, and an impedance coupled between drains of the cross-coupled transistors. In certain aspects, the differential amplifier comprises a push-pull amplifier, and the transistors of the push-pull amplifier comprise cascode-connected transistors.

Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.

Abstract: An apparatus and method and system therefor relates generally to decision threshold control. In such an apparatus, an ac-coupler circuit is configured as a high-pass circuit path for a first frequency range. A buffer amplifier circuit is coupled in parallel with the ac-coupler circuit. The buffer amplifier circuit is configured as a low-pass circuit path for a second frequency range. An offset injection circuit is coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.

Abstract: A semiconductor device is provided. Gates of first PMOS and NMOS transistors are coupled together for receiving an input signal. Gates of second PMOS and NMOS transistors are coupled together. Gates of third PMOS and NMOS transistors are coupled together. Gates of fourth PMOS and NMOS transistors are coupled together. Drains of fourth PMOS and NMOS transistors are coupled together for providing an output signal. When the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, the output signal is provided according to the input signal and a first logic function. When the first and second NMOS transistors are connected in serial and the first and second PMOS transistors are connected in serial, the output signal is provided according to the input signal and a second logic function.

Abstract: A display apparatus includes a timing controller, a data driver and a display panel. The data driver generates a positive polarity data voltage and a negative polarity data voltage based on image data compensated by the timing controller. The display panel includes a first pixel driven based on the positive polarity voltage and a second pixel driven based on the negative polarity voltage. The display panel receives a storage voltage applied to the first pixel and the second pixel. The timing controller compensates the image data when a variation on a level of the storage voltage occurs. The compensation shifts a level of the first data voltage from a first normal level to a first compensation level in a direction, and shifts a level of the second data voltage from a second normal level to a second compensation level in the same direction.

Abstract: Front-end integrated circuit for wireless local area network WLAN applications. In some embodiments, a semiconductor die can include a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to facilitate the transmit and receive operations.

Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.

Abstract: A circuit includes a differential input pair stage including bipolar transistors and configured to receive an RF input signal; a cascode stage coupled between the differential input pair stage and an output node, the cascode stage including bipolar transistors; and a current source including a first bipolar transistor coupled to a first output of the differential input pair stage and a second bipolar transistor coupled to a second output of the differential input pair stage.

Abstract: In the example of a voltage regulator outputting a negative voltage, its feedback voltage will also be negative. The feedback voltage is typically created using a resistor divider. A controller IC is powered by only a positive voltage and receives the negative feedback voltage at a high impedance input of an inverting amplifier. Therefore, the inverting amplifier does not load the resistor divider, resulting in an accurate regulated output voltage. The inverting amplifier converts the negative feedback voltage to a positive feedback voltage for further processing by the controller IC. An error amplifier and a power good monitor receive both the original feedback voltage and the inverted feedback voltage and use whichever feedback voltage is the more positive one. Therefore, the controller IC may be used in voltage regulators that generate either negative or positive output voltages.

Abstract: A differential circuit includes a first constant current circuit, a second constant current circuit having the same constant current value as the first constant current circuit, a current mirror including a first transistor having a current sink terminal connected to the first constant current circuit, a current drain terminal to which a first input voltage is applied, and a gate short-circuited to the current sink terminal, and a second transistor having a gate connected to the current sink terminal of the first transistor and a current drain terminal to which a second input voltage is applied, and a current output terminal connected to a connection node between a part in which a current based on an output current of the current mirror flows and the second constant current circuit.

Abstract: A buffer circuit may include an amplification circuit, a main load circuit, and a sub-load circuit. The amplification circuit and the main load circuit may generate first and second output signals by amplifying first and second input signals. The sub-load circuit may compensate mismatch between rising timing and falling timing of the first output signal based on the first input signal.

Abstract: A power amplifier circuit includes an input that receives a first input signal having a first phase and a second input signal having a second phase, a first transistor that includes a source that is supplied with a first voltage, and a gate that receives the first input signal, a second transistor that includes a source that is supplied with the first voltage, and a gate that receives the second input signal, a first neutralizing circuit that neutralizes a parasitic element, a second neutralizing circuit that neutralizes a parasitic element, N third transistors, N being an integer equal to or higher that 1, N fourth transistors, and an output that is connected between a drain of the N-th third transistor and a drain of the N-th fourth transistor and outputs a first output signal having a third phase and a second output signal having a fourth phase.

Abstract: An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.

Abstract: A sort-and-delay time-to-digital converter (TDC) is provided, made up of a plurality of serially connected sort-and-delay circuits. Each sort-and-delay circuit accepts a time-differential input signal with a first edge separated from a second edge by an input duration of time. The first and second edges are selectively routed as a time-differential output signal with a delayed edge separated from a trailing edge by an output duration of time representing a compression of the input duration of time. Each sort-and-delay circuit also supplies a TDC coded bit (e.g., Gray code) indicating the order in which the first and second edges are routed as leading and trailing edges. The TDC outputs a digital output signal representing the initial input duration of time associated with the initial time-differential input signal received by the initial sort-and-delay circuit. Associated TDC, sort-and-delay, and time amplification methods are also provided.

Abstract: A method for pre-amplifying an input voltage signal to a pre-amplified voltage signal. The method includes receiving the input voltage signal; obtaining a high-pass filtered voltage signal by applying a high-pass filter to the input voltage signal; processing the high-pass filtered voltage signal to a current signal that corresponds to the high-pass filtered voltage signal; transmitting the current signal through a differential transmission line; converting the transmitted current signal to a converted voltage signal that corresponds to the high-pass filtered voltage signal; and outputting the converted voltage signal as the pre-amplified voltage signal. An integrated circuit chip implementing the method is also disclosed.

Abstract: The present disclosure relates to a liquid crystal panel and the driving circuit. The liquid crystal panel includes a plurality of source driving circuits and a plurality of sub-pixel rows extending along a row direction. Each of the sub-pixel rows includes a plurality of sub-pixels of different colors and the sub-pixels are arranged periodically along the row direction. Within one scanning frame, polarity of driving voltage of at least one sub-pixel within the arranging period is opposite to that of other sub-pixels. Each of the source driving circuit includes at least two output ends respectively connecting to at least two sub-pixels having the same polarity of driving voltage within the same scanning frame to provide the driving voltage of the same polarity to the at least two sub-pixels. In this way, the power consumption of the source driving circuit may be reduced.

Abstract: There are provided a touch sensing device and a touchscreen device. The touch sensing device includes: a driving circuit applying a driving signal having a predetermined first period to a node capacitor; a buffer circuit converting capacitance of the node capacitor into a voltage signal; a buffer capacitor being charged and discharged depending on an output voltage from the buffer circuit; and an integration circuit integrating voltages charged in the buffer capacitor, wherein, in a normal touch mode, the buffer circuit integrates capacitance of the node capacitor to generate the voltage signal, and, in a proximity touch mode, the buffer circuit generates the voltage signal by following the voltages charged in the node capacitor.

Abstract: An analog amplifier is provided. The analog variable amplifier includes a first amplifier stage configured to amplify a bias current to output a first output voltage and a second output voltage that respectively depend on a magnitude of a first input voltage and a second input voltage, a second amplifier stage configured to receive the first output voltage and the second output voltage of the first amplifier stage as inputs and to amplify the received first output voltage and the second output voltage, and at least one auxiliary bias current source coupled to an electrical connection between the first amplifier stage and the second amplifier stage through which the second amplifier stage receives the first output voltage, and coupled to an electrical connection between the first amplifier stage and the second amplifier stage through which the second amplifier stage receives the second output voltage.