Including Differential Amplifier Patents (Class 330/252)
  • Patent number: 8503966
    Abstract: According to one embodiment, a semiconductor integrated circuit has a transconductance circuit, a first load circuit, and a second load circuit. The transconductance circuit has a first current generator configured to generate a first current depending on an input voltage, and a second current generator configured to generate a second current depending on the input voltage. The first load circuit has a first load configured to output a first output voltage depending on the first current from a first output terminal. The second load circuit has a second load configured to output a second output voltage depending on the second current from a second output terminal. At least one of the transconductance circuit, the first load circuit and the second load circuit comprises an impedance adjusting module configured to adjust impedance.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Oda, Jun Deguchi
  • Patent number: 8497709
    Abstract: An input/output circuit has a first load having one end coupled to a first standard voltage line, a first MOS transistor having a drain electrode coupled to another end of the first load, a second load having one end coupled to the first standard voltage line, a second MOS transistor having a drain electrode coupled to another end of the second load, a third MOS transistor having a source electrode each of which is coupled to source electrodes of the first and second MOS transistors, a first constant-current source coupled between the source electrode of the first MOS transistor and a second standard voltage line, and a second constant-current source coupled between the source electrode of the second MOS transistor and the second standard voltage line. The circuit size is reduced by transmitting a differential signal or a single-ended signal using a single input/output circuit.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Norihiko Fukuzumi, Toshie Kato
  • Publication number: 20130187714
    Abstract: A frequency quadrupler comprises a balanced topology which increases broadband odd harmonic suppression. The frequency quadrupler is constructed in a cascode configuration which is a two-stage amplifier composed of a transconductance amplifier followed by a current buffer. The cascode is constructed with common emitter (CE) and common base (CB) stages which further improves the multiplier frequency response. The cascode configuration enables a notch filter to be placed between the common emitter and common base stages to reduce 2nd harmonic generation and thereby increase 4th harmonic output power, generation efficiency and conversion gain. To cancel 4th harmonic components at the input that may destructively interfere with the output signal, capacitors are placed at the input of the common emitter stage, which in conjunction with the parasitic base wire inductance, form a notch filter to short the 4th harmonic.
    Type: Application
    Filed: January 22, 2012
    Publication date: July 25, 2013
    Applicant: International Business Machines Corporation
    Inventors: Roee Ben-Yishay, Roi Carmon, Danny Elad, Oded Katz, Benny Sheinman
  • Publication number: 20130187715
    Abstract: An amplifier includes a PWM converter that carries out pulse width modulation on differential input signals to generate differential PWM signals by comparing the differential input signals with sawtooth or triangular reference signal, and a power amplifier that carries out power amplification of the differential PWM signals to generate differential output signals. The power amplifier has a driver that drives a load with differential driving signals, a controller that sets a dead time in the differential driving signals to prevent current flow between power supply and ground terminals of the driver circuit, and a pre-delay compensator that generates the differential driving signals based on the differential PWM signals and sends the differential driving signals to the controller. The differential driving signals generated by the pre-delay compensator includes a pulse width for compensating for the dead time that is to be set in the differential driving signals by the controller.
    Type: Application
    Filed: September 7, 2012
    Publication date: July 25, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshikazu NAGASHIMA
  • Patent number: 8487699
    Abstract: Described is an inductive compensating network coupled between the differential inputs of an operational amplifier circuit. The inductive compensating network includes at least one inductive element having an inductance value selected so as to provide proper compensation of the operational amplifier circuit. Also described is a feedback compensation scheme which adjusts loop characteristics by introducing zeros into a system with the addition of inductive or capacitive elements in a feedback path.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 16, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Douglas Jay Kozak Adams, Rahul Sarpeshkar
  • Patent number: 8487921
    Abstract: In a display panel driver an output amplifier circuit includes a first output stage to receive a power supply voltage and a first voltage lower thereto and to output a drive voltage in a first voltage range defined between the power supply voltage and a middle power supply voltage; and a second output stage to receive the power supply and ground voltages and to output a drive voltage between the power supply and ground voltages. In a first mode that the first voltage is set as the middle power supply voltage, the first output stage outputs a first drive voltage in the first voltage range to one of first and second output terminals. In a second mode that the first voltage is set as the ground voltage, the second output stage outputs a first drive voltage in the first voltage range to one of the first and second output terminals.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: July 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Atsushi Shimatani
  • Patent number: 8482265
    Abstract: A current balance circuit includes a first branch and a second branch in parallel between a power supply unit and at least one load, which respectively include a switch. The current balance circuit detects and compares currents flowing through the first branch and the second branch. The current balance circuit also generates triangle waves and reversed triangle waves, compares voltage of a control pole of a first switch with the triangle waves, and compares voltage of the control pole of a second switch with the reversed triangle waves. Then the current balance circuit controls if the triangle waves and the reversed triangle waves are input to the first switch and the second switch according to the currents flowing through the first branch and the second branch to adjust impedance of the first switch and the second switch to balance the currents flowing through the first branch and the second branch.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: July 9, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Yi-Guo Chiu
  • Publication number: 20130169361
    Abstract: Disclosed are systems and methods to achieve a low noise, fully differential amplifier with controlled common mode voltages at each stage output but without the requirement of a common mode feedback loop. Common mode voltages are adjusted by adjusting the currents flowing through the load impedances (bias currents) wherein the currents are derived from one or more voltage-to-current converters based on an impedance that matches to the load impedances of the stages of the amplifier. The amplifier invented is primarily used for amplification of low frequency signals. The amplifier has one or more gain stages applying only one conduction type of transistors of an IC technology that has the lowest transition frequency between 1/f noise and white noise to achieve a low chopping or autozeroing frequency.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 4, 2013
    Applicant: DIALOG SEMICONDUCTOR GMBH
    Inventor: Dirk Killat
  • Publication number: 20130162352
    Abstract: Embodiments of the present disclosure relate to radio frequency (RF) transmitter circuitry, which includes non-inverting path power amplifier (PA) circuitry, inverting path PA circuitry, and RF transformer circuitry. The non-inverting path PA circuitry provides a non-inverting RF signal and a first power supply (PS) signal to the RF transformer circuitry, such that the first PS signal has a first ripple voltage. The inverting path PA circuitry provides an inverting RF signal and a second PS signal to the RF transformer circuitry, such that the second PS signal has a second ripple voltage. The RF transformer circuitry additively combines the non-inverting RF signal and the inverting RF signal to provide an RF output signal, such that effects of the first ripple voltage and the second ripple voltage are substantially cancelled from the RF output signal.
    Type: Application
    Filed: June 25, 2012
    Publication date: June 27, 2013
    Applicant: RF MICRO DEVICES, INC.
    Inventor: Nadim Khlat
  • Publication number: 20130154806
    Abstract: A calibrated gate biasing circuit according to one embodiment includes a switched capacitor precision resistor; and a voltage reference. An electronic circuit for initiating a change in state of a host device, according to another embodiment, includes a counter coupled to a host device, the counter counting at a fixed interval, wherein the counter is reset to zero upon receiving a command from a remote device, wherein the count is compared to a reference value, wherein the host device changes states if the count matches the reference value, wherein operation of the counter continues in spite of an interruption in power supply from a power source.
    Type: Application
    Filed: February 15, 2013
    Publication date: June 20, 2013
    Applicant: Intelleflex Corporation
    Inventor: Intelleflex Corporation
  • Patent number: 8466742
    Abstract: The present invention relates to a large time constant steering circuit for slowly changing a voltage on a node between at least two discrete voltage levels. The present invention further relates to a slow steering current DAC comprising said large time constant steering circuit. The present invention further relates to an instrumentation amplifier device comprising a current balancing instrumentation amplifier for amplifying an input signal to an amplified output signal and a DC servo-loop for removing a DC-component from the input signal. The present invention further relates to an EEG acquisition ASIC comprising said instrumentation amplifier device.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: June 18, 2013
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Refet Firat Yazicioglu, Patrick Merken
  • Publication number: 20130147553
    Abstract: In aspects of the invention, at normal operation, an operational amplifier circuit has feedback applied from the output thereof to the input thereof so that currents equal to each other flow in differential pair transistors, respectively. While, in order that currents equal to each other may flow in the differential pair transistors, respectively, for compensating the difference in threshold voltages in the differential pair transistors, a voltage lower by a certain voltage difference than the voltage applied to the gate terminal of the transistor must be applied to the gate terminal of the transistor. From this, the switching of switches, when a virtual short circuit occurs, can make the output voltage of the operational amplifier circuit become a signal in which positive and negative rectangular ripples, with the values thereof being proportional to the value of the certain voltage difference, are superimposed on a true value.
    Type: Application
    Filed: November 13, 2012
    Publication date: June 13, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: FUJI ELECTRIC CO., LTD.
  • Patent number: 8456235
    Abstract: The present invention is contrived to adopt a differential pair type amplifier circuit comprising a differential pair constituted by a first transistor receiving an input of a first signal and by a second transistor receiving an input of a third signal generated by outputting a second signal of which the voltage level is a power supply voltage. Elements requiring a matching are two transistors constituting the differential pair for the amplifier circuit. Because of this, the elements requiring a matching can be placed close to each other regardless of a layout between the amplifier circuits.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: June 4, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Suguru Tachibana, Kenta Aruga, Tatsuo Kato
  • Patent number: 8456197
    Abstract: A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: June 4, 2013
    Assignee: STMicroelectronics International N.V.
    Inventors: Prashant Dubey, Navneet Gupta, Shailesh Kumar Pathak, Kaushik Saha, Gagandeep Singh Sachdev
  • Publication number: 20130135048
    Abstract: A radio frequency receiver of the present invention removes out-of-band jamming signals and interference signals without SAW filters. The radio frequency receiver includes: a low noise amplifier amplifying a signal received through an antenna; a second order intermodulation cancellation unit removing second order intermodulation caused by an out-of-band jamming or interference signal included in the signal output from the low noise amplifier; a passive mixer unit converting a frequency of the signal output from the second order intermodulation cancellation unit; and a low pass filter unit removing an out-of-band jamming or interference signal included in the signal output from the passive mixer unit and delivering the signal with the out-of-band jamming or interference signal removed therefrom to a transimpedance amplifier.
    Type: Application
    Filed: June 5, 2012
    Publication date: May 30, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Seok-bong HYUN, Bong Hyuk Park, Yun Ho Choi, Jae Ho Jung
  • Publication number: 20130135047
    Abstract: An amplifier configuration including first and second amplifier inputs and a bias input adapted to receive a common mode signal indicative of a common mode input voltage. First and second amplifier input stage sections, each having first and second inputs coupled to respective ones of the first and second amplifier inputs, are provided. Operating mode circuitry switches the amplifier configuration between first and second operating modes in response to the common mode signal, where in the first operating mode the first and second amplifier input stage sections are active and inactive, respectfully and where in the second operating mode the first and second amplifier input stage sections are inactive and active, respectfully. The active first and second amplifier input stage sections are capable of operating with common mode voltages in excess of the upper and lower power supply rails, respectively.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Alberto Danioni
  • Publication number: 20130120064
    Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.
    Type: Application
    Filed: January 4, 2013
    Publication date: May 16, 2013
    Applicant: ParkerVision, Inc.
    Inventor: ParkerVision, Inc.
  • Publication number: 20130113562
    Abstract: A current reuse device including a first stage provided with a first input for a first input signal and a first output for a first output signal; a second stage comprising a second input for a second input signal and a direct current terminal operating as a ground terminal for alternate signals; a first inductor connected to a first output and to the direct current terminal so that the first and second stages share a direct current; a second inductor reciprocally coupled to the first inductor and connected to the second input in order to generate the second input signal as a function of the first output signal.
    Type: Application
    Filed: September 5, 2012
    Publication date: May 9, 2013
    Applicant: STMicroelectronics S.r.l.
    Inventors: Vittorio GIAMMELLO, Egidio RAGONESE, Giuseppe PALMISANO
  • Publication number: 20130106512
    Abstract: A folded cascode operational amplifier is disclosed. The folded cascode operational amplifier includes a first current source, a second current source, and a first voltage terminal connected to the first current source and the second current source. The folded cascode operational amplifier also includes a first input-transistor connected to the first current source in series, and a second input-transistor connected to the second current source in series. Further, the folded cascode operational amplifier includes a tail current source connected to a connection point between the first input-transistor and the second input-transistor, a load current source, and a second voltage terminal connected to the tail current source and the load current source. The folded cascode operational amplifier also includes an output-transistor connected to the load current source, and an output-terminal arranged between the second current source and the second input-transistor and connected to the output-transistor.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 2, 2013
    Inventor: Liang Cheng
  • Patent number: 8433259
    Abstract: Disclosed herein is a gyrator circuit, including, a first transconductance amplifier, a capacitor, and a second transconductance amplifier, wherein the differential input terminals of the first transconductance amplifier and the differential output terminals of the second transconductance amplifier being separated from each other.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: April 30, 2013
    Assignee: Sony Corporation
    Inventor: Shouichi Kuroki
  • Patent number: 8427355
    Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 23, 2013
    Assignee: University of Macau
    Inventors: Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti
  • Patent number: 8422981
    Abstract: An integrated circuit (IC) includes multiple circuits isolated with respect to one another. Each circuit of the multiple circuits includes an inductor pair formed in a loop pattern on a same layer as at least one other inductor pair from another circuit of the multiple circuits, such that the inductor pair surrounds and is isolated from the at least one other inductor pair.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 16, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Won Mun, Seong-Han Ryu, Il-Ku Nam
  • Publication number: 20130069720
    Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, a method amplifying a differential input voltage signal using a first NMOS transistor and a second NMOS transistor is provided. The method includes controlling a drain-source voltage of the first NMOS transistor using a first high voltage NMOS transistor and a first high voltage PMOS transistor. The first high voltage NMOS and PMOS transistors are electrically connected in parallel and to a drain of the first NMOS transistor. The method further includes controlling a drain-source voltage of the second NMOS transistor using a second high voltage NMOS transistor and a second high voltage PMOS transistor. The second high voltage NMOS and PMOS transistors are electrically connected in parallel and to a drain of the second NMOS transistor.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 21, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventor: Mark Reisiger
  • Patent number: 8400095
    Abstract: A speed-control circuit for a BLDC motor is provided. The speed-control circuit includes a pulse generator, a current source circuit, a filter circuit, an error amplification circuit and a PWM circuit. The pulse generator detects a speed signal of the BLDC motor to generate a pulse signal. The filter circuit is coupled to the current source circuit to generate an average signal. The error amplification circuit receives the average signal and a speed-reference signal for generating a speed-control signal. The PWM circuit generates a switching signal to drive the BLDC motor in response to the speed-control signal. A pulse width of the switching signal is determined by the speed-control signal.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: March 19, 2013
    Assignee: System General Corporation
    Inventors: Ta-Yung Yang, Ta-Hsu Huang, Chung-Hui Yeh, Pei-Sheng Tsu, Yi-Min Hsu, Shih-Jen Yang
  • Patent number: 8395451
    Abstract: A N-Channel HJ-FET cascode amplifier, with a High Frequency NPN Transistor differential error amplifier, having low 1/f noise, a DC to 12 GHz bandwidth, flat frequency response, excellent transient response, high linearity, and low input and output VSWR over a wide frequency range.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: March 12, 2013
    Inventor: Mark Scott Logue
  • Publication number: 20130057343
    Abstract: The present invention provides a high-frequency power amplifying device capable of transmitting output power at high efficiency. For example, a high-frequency power amplifying device has first and second differential amplifiers and a transformer for matching output impedances of the differential amplifiers. Between differential output nodes of the first differential amplifier, an inductor, a switch, and an inductor are coupled in series. When the second differential amplifier is in an operating state and the first differential amplifier is in a non-operating state, the switch is controlled to be on. In this case, due to “off capacitance” in transistors of a differential pair included in the first differential amplifier, impedance on the first differential amplifier side seen from both ends of primary coils becomes a high impedance state (parallel resonance state) and, equivalently, the primary coils do not exert influence on the operation of the second differential amplifier.
    Type: Application
    Filed: July 25, 2012
    Publication date: March 7, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Masao KONDO
  • Publication number: 20130057344
    Abstract: An RF amplifier including first and second branches coupled in parallel between first and second supply voltage terminals, and a differential pair including first and second transistors each having first and second main current terminals, the second main current terminal of the first transistor being coupled by a first capacitor to the first main current terminal of the second transistor, and the second main current terminal of the second transistor being coupled by a second capacitor to the first main current terminal of the first transistor, wherein the first branch includes a first resistor coupled between the first main current terminal to of the first transistor and the second capacitor, and the second branch includes a second resistor; coupled between the first main current terminal of the second transistor and the first capacitor.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 7, 2013
    Applicant: STMicroelectronics (Grenoble) SAS
    Inventors: Olivier Touzard, Fabien Sordet
  • Publication number: 20130043946
    Abstract: Multiple low noise amplifiers (LNAs) with combined outputs are disclosed. In an exemplary design, an apparatus includes a front-end module and an integrated circuit (IC). The front-end module includes a plurality of LNAs having outputs that are combined. The IC includes receive circuits coupled to the plurality of LNAs via a single interconnection. In an exemplary design, each of the plurality of LNAs may be enabled or disabled via a respective control signal for that LNA. The front-end module may also include receive filters coupled to the plurality of LNAs and a switchplexer coupled to the receive filters. The front-end module may further include at least one power amplifier, and the IC may further include transmit circuits coupled to the at least one power amplifier.
    Type: Application
    Filed: February 6, 2012
    Publication date: February 21, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Aristotele Hadjichristos, Gurkanwal Singh Sahota
  • Publication number: 20130038341
    Abstract: In one possible implementation, a method is provided for determining contactor health including measuring a differential voltage between a first utility line voltage and a second utility line voltage on a primary side of a contactor and on a secondary side of the contactor. The measuring is performed with both an unloaded current and with a load current. The unloaded and loaded measurements are performed at the primary side and the secondary side, and are made with the contactor closed. It includes determining a difference between a secondary unloaded voltage and a secondary loaded voltage and subtracting a difference between a primary unloaded voltage and a primary loaded voltage to provide a contactor voltage drop. The contactor resistance is determined by dividing the contactor voltage drop by the loaded current.
    Type: Application
    Filed: October 18, 2012
    Publication date: February 14, 2013
    Inventor: Albert Flack
  • Patent number: 8373503
    Abstract: A mixer in an RF demodulator includes a transconductance amplifier that converts an RF input voltage (Vin), applied to the base of a first bipolar transistor, to a first output current. The first output current contains third order intermodulation (IM3) products. An IM3 canceller is connected in parallel with the transconductance amplifier. The base of a second bipolar transistor in the IM3 canceller is coupled to the DC component of Vin, and the AC component of Vin is coupled to the emitter of the second bipolar transistor, such that the currents though the first bipolar transistor and the currents through the second bipolar transistor change oppositely. The collectors of the transistors are coupled together. The values of components in the IM3 canceller are set so that the current generated by the IM3 canceller substantially cancels IM3 distortion in the first current or other current generated in a demodulator of Vin.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: February 12, 2013
    Assignee: Linear Technology Corporation
    Inventors: John P. Myers, Petrus M. Stroet
  • Publication number: 20130033323
    Abstract: An electronic system comprises a resistive sensor structure and an electronic circuit portion whose design is selected such that different resistive sensor structures may be combined within the same electronic circuit. To this end, the resistive sensor structure is used as a voltage/current converter that provides input currents to a current amplifier, which in turn provides an amplified output voltage on the basis of a difference of the input currents. The operating range of the current amplifier is adjusted on the basis of a programmable current source irrespective of the configuration of the resistive sensor structure.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 7, 2013
    Applicant: STMicroelectronics S.r.l
    Inventor: Antonino Scuderi
  • Publication number: 20130033320
    Abstract: Provided herein are a circuit and method for dynamically controlling operational amplifier (op-amp) offset for photodetector applications using a variable trimming circuit coupled to a test node and an op-amp.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 7, 2013
    Applicant: TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC.
    Inventor: GONGGUI XU
  • Publication number: 20130033322
    Abstract: Circuit unit (CU) comprising a heterojunction bipolar transistor and a long-gate pseudomorphic high-electron-mobility transistor. Either a source (S) or a drain (D) of the long-gate pseudomorphic high-electron-mobility transistor is electrically coupled with either a collector (C) or an emitter (E) of the heterojunction bipolar transistor.
    Type: Application
    Filed: March 5, 2010
    Publication date: February 7, 2013
    Inventors: Bart Balm, Jeroen Bouwman, Léon C.M. van den Oever
  • Patent number: 8368467
    Abstract: An amplifier circuit for current amplification. An input stage is adapted to receive an input signal. At least one current multiplication stage is connected to the input stage. The current multiplication stage is adapted to receive a current signal from the input stage and to produce a multiplied output current signal at an output of the amplifier circuit. The current multiplication stage includes at least two current multiplication circuits connected to each other. Each current multiplication circuit is adapted to produce an output current signal essentially equal to the current signal from the input stage, such that the output current signal at an output of the amplifier circuit includes a sum of the current signals received at each current multiplication circuit. A method of improving linearity in an amplification circuit.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: February 5, 2013
    Assignee: SAAB AB
    Inventor: Håkan Berg
  • Patent number: 8369818
    Abstract: Embodiments of a radio frequency (RF) receiver implementing one or more forms of protection to protect devices of the RF receiver from in-band interferers is provided. The RF receiver includes an integrated circuit terminal configured to couple a RF signal received at an antenna to a RF signal path, and a low noise amplifier (LNA) coupled to the RF signal path and configured to amplify the RF signal to provide an amplified RF signal. To protect the LNA from in-band interferers, the RF receiver can further include one or more clamping circuits and/or an over-voltage detector to determine if a peak of the RF signal exceeds an acceptable level.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: February 5, 2013
    Assignee: Broadcom Corporation
    Inventors: Yuyu Chang, Hooman Darabi
  • Patent number: 8362939
    Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (IS) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: January 29, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Berry Anthony Johannus Buter, Hans Van De Vel
  • Publication number: 20130021097
    Abstract: Described is an inductive compensating network coupled between the differential inputs of an operational amplifier circuit. The inductive compensating network includes at least one inductive element having an inductance value selected so as to provide proper compensation of the operational amplifier circuit. Also described is a feedback compensation scheme which adjusts loop characteristics by introducing zeros into a system with the addition of inductive or capacitive elements in a feedback path.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 24, 2013
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Douglas Jay Kozak Adams, Rahul Sarpeshkar
  • Patent number: 8354887
    Abstract: In accordance with the teachings described herein, systems and methods are provided for charge compensation. A system may include an operational transconductance amplifier including an input terminal and an output terminal, a transistor network, and a capacitive circuit. The transistor network may be coupled in a feedback loop between the input terminal and the output terminal. The capacitive circuit may be configured to compensate a charge built on a parasitic capacitance of the transistor network during operation.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: January 15, 2013
    Assignee: Marvell International Ltd.
    Inventors: Hao Zhou, Yonghua Song, Jie Jiang, Tao Shui
  • Publication number: 20130009704
    Abstract: An integrated circuit is disclosed, including a balun, a transistor pair, and a degeneration inductor winding. The balun has an outer boundary, and comprises a primary winding and a secondary winding. The primary winding is adapted to receive an input signal. The secondary winding is magnetically coupled to the primary winding, and adapted to convert the input signal into a differential form. The transistor pair is connected to the secondary winding and adapted to amplify the input signal. The degeneration inductor winding is connected to the transistor pair and located within the outer boundary of the balun.
    Type: Application
    Filed: December 1, 2011
    Publication date: January 10, 2013
    Applicant: MEDIATEK INC.
    Inventor: Chih-Fan Liao
  • Publication number: 20120326786
    Abstract: Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages.
    Type: Application
    Filed: September 6, 2012
    Publication date: December 27, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Aaron Willey
  • Publication number: 20120326785
    Abstract: An amplifier arrangement constituted of: a first input lead; a second input lead; a difference amplifier; a first buffer, the input of the first buffer coupled to the first input lead, the output of the first buffer coupled to a first input of the difference amplifier; a second buffer, the input of the second buffer coupled to the second input lead, the output of the second buffer coupled to a second input of the difference amplifier; and a transconductance amplifier, the non-inverting input and the non-inverted output of the transconductance amplifier coupled to the first input of the difference amplifier, the inverting input and the inverted output of the transconductance amplifier coupled to the second input of the difference amplifier. The input signals are thus buffered and the offset of the buffers are compensated for.
    Type: Application
    Filed: May 3, 2012
    Publication date: December 27, 2012
    Applicant: MICROSEMI CORPORATION
    Inventors: Kai KWAN, Peter KIM
  • Patent number: 8339296
    Abstract: An amplifying circuit includes a pair of MOS transistors; an amplifier that amplify a difference between potentials of differential output nodes coupled to drains of the pair of MOS transistors; cancel circuits that cause cancel current to flow to one of the differential output nodes when the amplifier amplifies a voltage between the differential output nodes and that shut off, after the amplifier performs the amplification operation, inflow of the cancel current; and a controller that performs setting so that a potential of first one of the differential input signals is equal to a potential of another one of the differential input signals, that compares, before the inflow of the cancel current, potentials generated at differential output nodes when the difference between potentials of the differential output nodes is amplified, and that sets the cancel current so that the potentials are reversed after the inflow of the cancel current.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Limited
    Inventor: Takumi Danjo
  • Patent number: 8339198
    Abstract: Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 25, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Peter J. Mole, Philip V. Golden
  • Patent number: 8339197
    Abstract: Matched bipolar transistor pairs for use in differential transistor pair circuitry, current mirror transistor pair circuitry and voltage reference transistor pair circuitry are disclosed. Each transistor in the pair includes a base, emitter and a collector region and a doped polysilicon emitter contact, a metal emitter contact and an metal emitter interconnect which makes an electrical connection to the emitter region by way of the metal emitter contact and the polysilicon emitter contact. The metal emitter interconnect is displaced latterly away from the emitter region so that no part of the metal emitter interconnect overlies any portion of the emitter region.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: December 25, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Kwok-Fu Chiu, Yih-Chyi Chong, Michael E. Haslam
  • Publication number: 20120319777
    Abstract: An amplifier comprises: an input stage for receiving incoming signals; a high gain stage coupled to the input stage and providing driving signals in response to the incoming signals to an output driver stage; and an output terminal coupled to the output driver stage. The output driver stage comprises a high side driver circuit having a first terminal receiving a first driving signal pdrive from the high gain stage, a second terminal coupled VDD through a first voltage drop, and a third terminal coupled to the output terminal of the amplifier.
    Type: Application
    Filed: September 20, 2011
    Publication date: December 20, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventor: Aidan Cahalane
  • Patent number: 8330500
    Abstract: A comparator comprises a current mirror, a differential input pair, and a auxiliary circuit. The current mirror has a biasing end coupled to a power voltage, a first end, and a current outputting end coupled to an output node of the comparator. The differential input pair has a first and second input ends for respectively receiving a first voltage and a second voltage, a second and third ends, and a ground end, wherein the third end is coupled to the first end. The auxiliary circuit is coupled between the output node and the second end, and provides a minimum voltage of a comparison result output at the output node. The comparison result is the power voltage when the first voltage is larger than the second voltage, and the comparison result is the minimum voltage when the first voltage is less than the second voltage.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: December 11, 2012
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Yi-Heng Liu
  • Patent number: 8331890
    Abstract: A FM receiver comprises an IF filter, a demodulator and a decoder. The IF filter generates an RSSI and a FM modulated signal in response to a FM signal. The demodulator comprises a duty-to-voltage amplifier for amplifying a peak of a MPX signal. The duty-to-voltage amplifier comprises a current source, a switch and a current splitter. The current source generates a current. The switch controls a flow of the first current in response to a PWM signal. The current splitter splits the flow of the current into a sub-flow in response to the RSSI. The peak of the MPX signal is proportional to the sub-flow. The decoder receives the MPX signal to generate an audio signal to play sound.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: December 11, 2012
    Assignee: MediaTek Inc.
    Inventors: Hsiang-Hui Chang, Chieh Hung Chen
  • Patent number: 8324555
    Abstract: A multiple transistor differential amplifier is implemented on a segment of a single graphene nanoribbon. Differential amplifier field effect transistors are formed on the graphene nanoribbon from a first group of electrical conductors in contact with the graphene nanoribbon and a second group of electrical conductors insulated from, but exerting electric fields on, the graphene nanoribbon thereby forming the gates of the field effect transistors. A transistor in one portion of the graphene nanoribbon and a transistor in another portion of the graphene nanoribbon are responsive to respective incoming electrical signals. A current source, also formed on the graphene nanoribbon, is connected with the differential amplifier, and the current source and the differential amplifier operating together generate an outgoing signal responsive to the incoming electrical signal. In an example application, the resulting circuit can be used to interface with electrical signals of nanoscale sensors and actuators.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: December 4, 2012
    Assignee: Pike Group LLC
    Inventor: Lester F. Ludwig
  • Patent number: 8319552
    Abstract: An amplifier having an imbalance between pull-up and pull-down sections may include a counterpart section to balance the output sections and/or enable them to be driven by balanced drive signals. In one embodiment, a rail-to-rail output stage may include a current minor to drive one side of the circuit. The other side may be driven by a transistor having a counterpart transistor to balance the circuit. A drive section may include a balance point to facilitate balancing the drive signals.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: November 27, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 8319551
    Abstract: Apparatus and method for a limiting amplifier with improved phase noise. The improved limiting amplifier includes an input port, an output port, and one or more cascaded gain stages. The input of a first gain stage is connected to the input port of the limiting amplifier. The output of a last gain stage is connected to the output port of the limiting amplifier. Among the cascaded gain stages, an output of each gain stage is connected to an input of an adjacent gain stage. Each gain stage i, 1<i<n?1, is configured so that it is capable of selecting at least one lowpass filter corner frequency ?pi, and thereby reducing the phase noise of the gain stage through the broadband noise reduction for frequencies greater than ?pi. Here, ?pi is selected from a plurality of values associated with the gain stage to optimize the phase noise of the limiting amplifier by trading off reducing the broadband noise of the gain stage versus maintaining a sufficient output slew-rate of the gain stage.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: November 27, 2012
    Assignee: Linear Technology Corporation
    Inventor: Leslie Catherine Muscha