Abstract: An integrated circuit includes a memory cell and a sense amplifier coupled to the memory cell via a first bit line and a second bit line. The sense amplifier includes first and second inverters cross-coupled to provide a latch. The first inverter is responsive to a first data signal provided by the memory cell over the first bit line. The second inverter is responsive to a second data signal as provided by the memory cell over the second bit line. A first negative bias temperature instability (NBTI) compensation transistor includes a source electrode coupled to receive a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to the first data signal.

Abstract: A push-pull amplifier is provided for amplifying an input signal, having first and second amplifier elements. Each of the amplifier elements has a current-emitting electrode, a current-collecting electrode, and a current-controlling electrode. The input signal is supplied to the current-controlling electrodes of the amplifier elements via a respective input connection and a respective input inductor arranged between the respective input connection and the respective current-controlling electrode. The current-collecting electrodes are connected via a respective supply inductor having a common supply voltage. The current-emitting electrode of each amplifier element is connected to the current-collecting electrode of the other amplifier element via a respective capacitor. The current-emitting electrodes are connected to output connections on which the output signal can be picked up, and to a reference potential via a respective output inductor.

Abstract: A voltage sampling RF receiver in which an impedance control circuit controls the input impedance, by using a mixer stage which generates a feedback voltage, which is coupled to the RF input by a feedback resistor. A biasing arrangement can be used to adjust the feedback path so that local oscillator leakage signals are suppressed.

Abstract: An amplifier configuration including first and second amplifier inputs and a bias input adapted to receive a common mode signal indicative of a common mode input voltage. First and second amplifier input stage sections, each having first and second inputs coupled to respective ones of the first and second amplifier inputs, are provided. Operating mode circuitry switches the amplifier configuration between first and second operating modes in response to the common mode signal, where in the first operating mode the first and second amplifier input stage sections are active and inactive, respectfully and where in the second operating mode the first and second amplifier input stage sections are inactive and active, respectfully. The active first and second amplifier input stage sections are capable of operating with common mode voltages in excess of the upper and lower power supply rails, respectively.

Abstract: A power amplifier includes a first transistor and a first inductor disposed between the first transistor and a voltage source. A first node between the first transistor and the first inductor is an output node. The power amplifier further includes a second inductor disposed between the first transistor and ground The power amplifier further includes a third inductor coupled to a gate of the first transistor and configured as a first AC input. The power amplifier further includes a first phase conditioner inductively coupled to the second inductor and the third inductor and configured to set phases of AC signals across the first inductor and the second inductor in phase. The second inductor is configured to release energy into the first inductor to raise a voltage of the AC signal and raise a power output at the output node.

Abstract: An amplifying circuit includes a first circuit component configured to receive and amplify first and second input voltages to generate an output voltage. The first circuit component is formed by a first amplifier and a second amplifier. A second circuit component is configured to provide a first offset current that is associated with a first input current of the first amplifier. The first offset current compensates for variation in the first input current. A third circuit component is configured to provide a second offset current that is associated with a second input current of the second amplifier. The second offset current compensates for variation in the second input current.

Abstract: In accordance with an embodiment, a system includes a first transistor and a second transistor. The first transistor has a first input node coupled to a first signal input, a first output node coupled to a first common node, and a first reference node coupled to a first reference voltage, and the second transistor has a second input node coupled to second signal input, a second output node coupled to an output of the system, and a second reference node coupled to the first common node. The system further includes a first switch switchably coupling the first common node to a second reference voltage.

Abstract: An electric repeater for use in transmission line based electric fences. The electric repeater comprises a forward amplifier, a backward amplifier, a quad pole quad throw signal switch, and a monostable circuit. The short forward electric pulse in the transmission line is amplified by the forward amplifier, and the amplified electric pulse trigger the monostable circuit. The monostable circuit then outputs a n electric pulse with predetermined width. This electric pulse operates the quad pole quad throw signal switch such that the wire pair of the transmission line is connected to the backward amplifier and disconnected from the forward amplifier as soon as the forward electric pulse has passed through the forward amplifier. DC electric power is supplied to the forward amplifier and backward amplifier by the transmission line metal wire pair, and two pairs of capacitors are used to block this DC electric power from entering the input and output of the forward and backward amplifiers.

Abstract: Techniques are disclosed relating to peak detection. In one embodiment, an apparatus is disclosed that includes an amplifier configured to amplify a signal. The apparatus further includes a peak detector DC coupled to an output of the amplifier. The peak detector includes a first comparator stage configured to perform subtraction of a threshold signal from the amplified signal. The peak detector further includes a second comparator stage is configured to amplify a differential output signal of the first comparator stage indicative of a result of the subtraction. In some embodiments, the amplifier and peak detector are included within automatic gain control system in a path for an in-phase or quadrature channel of the receiver chain.

Abstract: An electronic circuit has a differential amplifier with a differential transistor pair having two transistors. The electronic circuit also has two digital-to-analog converters, a respective one of the two digital-to-analog converters coupled to each respective one of the two transistors. Control bits adjust the DACs to provide an offset voltage adjustment of the differential amplifier.

Abstract: Apparatus and methods for notch filtering are provided. In certain implementations, an amplifier includes amplification stages for providing signal amplification, chopper circuitry for generating a chopped signal by chopping an amplified signal associated with the amplification stages at a chopping frequency, and a time-interleaved finite impulse response (FIR) notch filter for notching frequency components of the chopped signal near the chopping frequency. The time-interleaved FIR notch filter includes a plurality of FIR filters configured to sample the chopped signal at a sampling rate of about twice the chopping frequency. The FIR filters are interleaved in time to reduce sampling error. Additionally, the time-interleaved FIR notch filter includes an infinite impulse response (IIR) filter configured to average samples taken by respective ones of the FIR filters and to integrate the averaged samples to generate the time-interleaved FIR notch filter's output signal.

Abstract: Provided is a discrete time receiver having a structure capable of processing various broadband signals. The discrete time receiver uses a discrete time filter having a sampling frequency in a constant range so as to process a signal having an input frequency in a wide range and a wide bandwidth, so that it is possible to reduce current consumption and the area of the discrete time receiver. Since the discrete time receiver is easily integrated with a digital device, it is easy to design a chip using system on chip (SoC).

Abstract: A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd1) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd1). The driver circuit may include a cascode stage (M3) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd2) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M5, M6) to couple a control terminal of an active load transistor (M9) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).

Abstract: A traveling wave amplifier (TWA) with suppressed jitter is disclosed. The TWA includes a plurality of unit amplifiers with the differential arrangement comprised of a pair of transistors and a cascade transistors connected in series to the switching transistors. The unit amplifiers further includes current sources to provide idle currents to the cascade transistors. Even when the switching transistors fully turn off, the idle currents are provided to the cascade transistors, which set the operating point of the cascade transistor in a region where an increase of the base-emitter resistance is suppressed.

Abstract: Described herein is a preamplifier circuit for a capacitive acoustic transducer provided with a MEMS detection structure that generates a capacitive variation as a function of an acoustic signal to be detected, starting from a capacitance at rest; the preamplifier circuit is provided with an amplification stage that generates a differential output signal correlated to the capacitive variation. In particular, the amplification stage is an input stage of the preamplifier circuit and has a fully differential amplifier having a first differential input (INP) directly connected to the MEMS detection structure and a second differential input (INN) connected to a reference capacitive element, which has a value of capacitance equal to the capacitance at rest of the MEMS detection structure and fixed with respect to the acoustic signal to be detected; the fully differential amplifier amplifies the capacitive variation and generates the differential output signal.

Abstract: A circuit that obtains a more accurate, output voltage from a plurality of input voltages is provided. A two-input single-output circuit includes a current source transistor allowing a predetermined current to flow, a cascode transistor section including two MOS transistors that are cascode-connected to the drain side of the current source transistor and have the same characteristics, a differential pair section having a first differential pair formed of a first input-side transistor and a first output-side transistor whose source lines are shared and a second differential pair formed of a second input-side transistor and a second output-side transistor whose source lines are shared, and a current mirror circuit section. Drain lines of the transistors of the cascade transistor section are respectively connected to the source lines of the first and second differential pairs.

Abstract: A hard drive write preamplifier includes a first differential pair of PNP BJTs having a first PNP BJT and a second PNP BJT; a first tail current source coupled into emitter of the PNP BJTs of the first differential pair; a second differential pair of NPN BJTs having a first NPN BJT and a second NPN BJT; a second tail current source coupled into the emitters of the NPN BJTs of the second differential pair; wherein a collector of each of the PNP BJTs of the first differential pair are coupled to a corresponding collector the NPN BJTs of the second differential pair; a first shift up PNP BJT having emitter coupled to the collector of a first PNP BJT of the first differential pair; a second shift up PNP BJT having an emitter coupled to the collector of the second PNP BJT of the first differential pair.

Abstract: A near field RF communicator has an antenna circuit (120) to receive a modulated radio frequency signal by inductive coupling and demodulation circuitry (130 or 131) to extract the modulation from a received modulated radio frequency signal inductively coupled to the antenna circuit. The demodulation circuitry has a virtual earth input comprising a current mirror. The demodulation circuitry may be formed by an amplifier (115 or 116) and a demodulator (114) coupled to an output of the amplifier. The amplifier may be a single input amplifier (116) coupled to an output of the antenna circuit or may be a differential amplifier (115) having first and second inputs to receive the modulated radio frequency signal from first and second outputs of the antenna circuit, with each amplifier input providing a virtual earth input.

Abstract: An Extremely High Frequency (EHF) dual-mode PA with a power combiner is designed using 40-nm bulk CMOS technology. One of the unit PAs can be switched off for the low power applications. In the design, circuit level optimization and trade-off are performed to ensure the good performance in both modes. The PA achieves a PSAT of 17.4 dBm with 29.3% PAE in high power mode and a PSAT of 12.6 dBm with 19.6% PAE in low power mode. The reliability measurements are also conducted and a lifetime of 80613 hours is estimated based on a commonly used empirical model. The excellent performance (e.g., highest reported PAE) achieved in this design further confirms the scaling of CMOS technology will continue to benefit the mm-wave transceiver design.

Abstract: A power amplifier circuit utilizes a cross-coupled tapped cascade topology together with a technique of applying an RF injection current into a wideband node to provide a single-stage power amplifier with improved PAE, output power, and gain over a wide RF band. The amplifier circuit comprises a cross-coupled cascade transistor unit comprising a pair of cross-coupled cascode transistors, a cross-coupled switching transistor unit comprising a pair of cross-coupled switching transistors, and an RF current generator. RF current generator generates a differential RF injection current, while switching transistor unit amplifies the injection current to generate an amplified injection current at the wideband node of the amplifier circuit and the cascode transistor unit further amplifies the injection current to generate the desired amplified signal at the output of the amplifier circuit.

Abstract: A folded cascode operational amplifier includes a constant current source to output a constant current; a differential input stage to output a part of the constant current as a differential current based on a voltage difference between voltages input to an inverting input terminal and a non-inverting input terminal, and connected to the constant current source; and an output stage to output a remaining current obtained by subtracting the differential current from the constant current as an output stage current, and connected parallel to the differential input stage facing the constant current source.

Abstract: An input receiver circuit including a single-to-differential amplifier and a semiconductor device including the input receiver circuit are disclosed. The input receiver circuit includes a first stage amplifier unit and a second stage amplifier unit. The first stage amplifier unit amplifies a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage. The second stage amplifier unit amplifies the differential output signal in a differential-to-single mode to generate a single output signal.

Abstract: A transconductance circuit that improves linearity and output current over a wider range of input voltages than prior designs. The transconductance circuit may include first and second sets of paired differential transistors. In each set, emitters of the paired transistors may be commonly coupled to corresponding nodes of a common impedance, and collectors may be coupled to output terminals of the transconductance circuit. The circuit may further include first and second sets of doublet differential transistor pairs, each doublet pair having transistors of different sizes. Each doublet pair may have current sources coupled between commonly coupled emitters and a source potential. Respective collectors for each doublet pair may be coupled to the output terminals of the transconductance circuit. A pair of voltage followers may be provided to replicate corresponding input voltages across corresponding bases of the differential transistor pairs and the doublet transistor pairs.

Abstract: A differential output stage configured for receiving differential input signal comprising first and second signals, comprising a first output for providing a first output signal, and a second output providing a second output signal, the first and second output signals together forming a differential output signal, a first voltage buffer and first controlled current source each connected to the first output, the first voltage buffer being driven by a signal in-phase with the first input signal, the first controlled current source being driven by a signal in-phase with the second input signal, and a second voltage buffer and second controlled current source each connected to the second output, the second voltage buffer being driven by a signal in-phase with the second input signal, the second controlled current source being driven a signal in-phase with by the first input signal.

Abstract: A programmable current driver provides de-emphasis capability. A number of identical transmitter slices, consisting of a unit current source and a unit differential pair, are connected in parallel to the termination resistors. As the transmitter slices are identical, the current density through the differential pairs are identical, and the VDS voltages across them (as well as the VDS voltages across the unit current sources) are the same, ensuring that the current through each slice is identical (within the limits of device matching). Biasing circuitry ensures that each unit current source sinks a current having a fixed proportion to the total current.

Abstract: A differential amplifier replicates the input stage and cross-connects the inputs, so that the input-to-output delay will be balanced in an averaged sense. The outputs of each of the two input stages are then summed after an open loop delay matched inversion has taken place. The result is a reduction in the duty cycle distortion of the receiver amplifier over process voltage and temperature (PVT) variation. This is enabled by the fact that a full swing CMOS delay cell can be made to have good delay matching over PVT, whereas the input stage to a differential amplifier may, depending on architecture, have poor delay matching because of impedance mismatches within the amplifier.

Abstract: A dual mode RF transceiver is provided. The dual mode RF transceiver comprises an antenna, a differential low noise amplifier (LNA), a local oscillator and a dual mode differential mixer. The differential LNA receives an RF signal from the antenna to generate a differential amplified RF signal. The dual mode differential mixer comprises a switch module, a plurality of fundamental mixers and a plurality of sub-harmonic mixers. The fundamental mixers are activated in a first receiving mode to generate a first differential baseband signal according to a multiphase local oscillating (LO) signal from the local oscillator and the differential amplified RF signal. The sub-harmonic mixers are activated in a second receiving mode to generate a second differential baseband signal according to the multiphase LO signal from the local oscillator and the differential amplified RF signal. An RF signal receiving method is disclosed herein as well.

Abstract: The present disclosure relates, according to some embodiments, to a transformer power amplifier that allows for improved Q values and increased efficiency by reducing the capacitance coupling effect between metal layers and/or sidewalls of the same layer through carefully designed conductor structures in primary and secondary loops. A transformer power amplifier comprises a substrate, a conductor, a circular coil, a first amplifier, and a second amplifier, the conductor and the circular coil disposed on the substrate. A circular coil has a first input terminal and a second input terminal, in which the first input terminal and the second input terminal are spaced apart and opposite each other to form an opening. A first amplifier is connected to a first input terminal for receiving a first signal and a second amplifier is connected to a second input terminal for receiving a second signal, wherein the first signal and the second signal are differential signals.

Abstract: According to one embodiment, a semiconductor integrated circuit has a transconductance circuit, a first load circuit, and a second load circuit. The transconductance circuit has a first current generator configured to generate a first current depending on an input voltage, and a second current generator configured to generate a second current depending on the input voltage. The first load circuit has a first load configured to output a first output voltage depending on the first current from a first output terminal. The second load circuit has a second load configured to output a second output voltage depending on the second current from a second output terminal. At least one of the transconductance circuit, the first load circuit and the second load circuit comprises an impedance adjusting module configured to adjust impedance.

Abstract: An amplifier receives an input signal with an input node, provides an output signal in response, and includes a main branch and an auxiliary branch. The auxiliary branch is coupled between the input node and a splitting node for input matching of the input node. The main branch, also coupled to the splitting node, has an output node of current mode, and is arranged to output the output signal at the output node. An associated receiver is also disclosed.

Abstract: An input/output circuit has a first load having one end coupled to a first standard voltage line, a first MOS transistor having a drain electrode coupled to another end of the first load, a second load having one end coupled to the first standard voltage line, a second MOS transistor having a drain electrode coupled to another end of the second load, a third MOS transistor having a source electrode each of which is coupled to source electrodes of the first and second MOS transistors, a first constant-current source coupled between the source electrode of the first MOS transistor and a second standard voltage line, and a second constant-current source coupled between the source electrode of the second MOS transistor and the second standard voltage line. The circuit size is reduced by transmitting a differential signal or a single-ended signal using a single input/output circuit.

Abstract: A frequency quadrupler comprises a balanced topology which increases broadband odd harmonic suppression. The frequency quadrupler is constructed in a cascode configuration which is a two-stage amplifier composed of a transconductance amplifier followed by a current buffer. The cascode is constructed with common emitter (CE) and common base (CB) stages which further improves the multiplier frequency response. The cascode configuration enables a notch filter to be placed between the common emitter and common base stages to reduce 2nd harmonic generation and thereby increase 4th harmonic output power, generation efficiency and conversion gain. To cancel 4th harmonic components at the input that may destructively interfere with the output signal, capacitors are placed at the input of the common emitter stage, which in conjunction with the parasitic base wire inductance, form a notch filter to short the 4th harmonic.

Abstract: An amplifier includes a PWM converter that carries out pulse width modulation on differential input signals to generate differential PWM signals by comparing the differential input signals with sawtooth or triangular reference signal, and a power amplifier that carries out power amplification of the differential PWM signals to generate differential output signals. The power amplifier has a driver that drives a load with differential driving signals, a controller that sets a dead time in the differential driving signals to prevent current flow between power supply and ground terminals of the driver circuit, and a pre-delay compensator that generates the differential driving signals based on the differential PWM signals and sends the differential driving signals to the controller. The differential driving signals generated by the pre-delay compensator includes a pulse width for compensating for the dead time that is to be set in the differential driving signals by the controller.

Abstract: Described is an inductive compensating network coupled between the differential inputs of an operational amplifier circuit. The inductive compensating network includes at least one inductive element having an inductance value selected so as to provide proper compensation of the operational amplifier circuit. Also described is a feedback compensation scheme which adjusts loop characteristics by introducing zeros into a system with the addition of inductive or capacitive elements in a feedback path.

Abstract: In a display panel driver an output amplifier circuit includes a first output stage to receive a power supply voltage and a first voltage lower thereto and to output a drive voltage in a first voltage range defined between the power supply voltage and a middle power supply voltage; and a second output stage to receive the power supply and ground voltages and to output a drive voltage between the power supply and ground voltages. In a first mode that the first voltage is set as the middle power supply voltage, the first output stage outputs a first drive voltage in the first voltage range to one of first and second output terminals. In a second mode that the first voltage is set as the ground voltage, the second output stage outputs a first drive voltage in the first voltage range to one of the first and second output terminals.

Abstract: A current balance circuit includes a first branch and a second branch in parallel between a power supply unit and at least one load, which respectively include a switch. The current balance circuit detects and compares currents flowing through the first branch and the second branch. The current balance circuit also generates triangle waves and reversed triangle waves, compares voltage of a control pole of a first switch with the triangle waves, and compares voltage of the control pole of a second switch with the reversed triangle waves. Then the current balance circuit controls if the triangle waves and the reversed triangle waves are input to the first switch and the second switch according to the currents flowing through the first branch and the second branch to adjust impedance of the first switch and the second switch to balance the currents flowing through the first branch and the second branch.

Abstract: Disclosed are systems and methods to achieve a low noise, fully differential amplifier with controlled common mode voltages at each stage output but without the requirement of a common mode feedback loop. Common mode voltages are adjusted by adjusting the currents flowing through the load impedances (bias currents) wherein the currents are derived from one or more voltage-to-current converters based on an impedance that matches to the load impedances of the stages of the amplifier. The amplifier invented is primarily used for amplification of low frequency signals. The amplifier has one or more gain stages applying only one conduction type of transistors of an IC technology that has the lowest transition frequency between 1/f noise and white noise to achieve a low chopping or autozeroing frequency.

Abstract: Embodiments of the present disclosure relate to radio frequency (RF) transmitter circuitry, which includes non-inverting path power amplifier (PA) circuitry, inverting path PA circuitry, and RF transformer circuitry. The non-inverting path PA circuitry provides a non-inverting RF signal and a first power supply (PS) signal to the RF transformer circuitry, such that the first PS signal has a first ripple voltage. The inverting path PA circuitry provides an inverting RF signal and a second PS signal to the RF transformer circuitry, such that the second PS signal has a second ripple voltage. The RF transformer circuitry additively combines the non-inverting RF signal and the inverting RF signal to provide an RF output signal, such that effects of the first ripple voltage and the second ripple voltage are substantially cancelled from the RF output signal.

Abstract: A calibrated gate biasing circuit according to one embodiment includes a switched capacitor precision resistor; and a voltage reference. An electronic circuit for initiating a change in state of a host device, according to another embodiment, includes a counter coupled to a host device, the counter counting at a fixed interval, wherein the counter is reset to zero upon receiving a command from a remote device, wherein the count is compared to a reference value, wherein the host device changes states if the count matches the reference value, wherein operation of the counter continues in spite of an interruption in power supply from a power source.

Abstract: The present invention relates to a large time constant steering circuit for slowly changing a voltage on a node between at least two discrete voltage levels. The present invention further relates to a slow steering current DAC comprising said large time constant steering circuit. The present invention further relates to an instrumentation amplifier device comprising a current balancing instrumentation amplifier for amplifying an input signal to an amplified output signal and a DC servo-loop for removing a DC-component from the input signal. The present invention further relates to an EEG acquisition ASIC comprising said instrumentation amplifier device.

Abstract: In aspects of the invention, at normal operation, an operational amplifier circuit has feedback applied from the output thereof to the input thereof so that currents equal to each other flow in differential pair transistors, respectively. While, in order that currents equal to each other may flow in the differential pair transistors, respectively, for compensating the difference in threshold voltages in the differential pair transistors, a voltage lower by a certain voltage difference than the voltage applied to the gate terminal of the transistor must be applied to the gate terminal of the transistor. From this, the switching of switches, when a virtual short circuit occurs, can make the output voltage of the operational amplifier circuit become a signal in which positive and negative rectangular ripples, with the values thereof being proportional to the value of the certain voltage difference, are superimposed on a true value.

Abstract: A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Abstract: The present invention is contrived to adopt a differential pair type amplifier circuit comprising a differential pair constituted by a first transistor receiving an input of a first signal and by a second transistor receiving an input of a third signal generated by outputting a second signal of which the voltage level is a power supply voltage. Elements requiring a matching are two transistors constituting the differential pair for the amplifier circuit. Because of this, the elements requiring a matching can be placed close to each other regardless of a layout between the amplifier circuits.

Abstract: An amplifier configuration including first and second amplifier inputs and a bias input adapted to receive a common mode signal indicative of a common mode input voltage. First and second amplifier input stage sections, each having first and second inputs coupled to respective ones of the first and second amplifier inputs, are provided. Operating mode circuitry switches the amplifier configuration between first and second operating modes in response to the common mode signal, where in the first operating mode the first and second amplifier input stage sections are active and inactive, respectfully and where in the second operating mode the first and second amplifier input stage sections are inactive and active, respectfully. The active first and second amplifier input stage sections are capable of operating with common mode voltages in excess of the upper and lower power supply rails, respectively.

Abstract: A radio frequency receiver of the present invention removes out-of-band jamming signals and interference signals without SAW filters. The radio frequency receiver includes: a low noise amplifier amplifying a signal received through an antenna; a second order intermodulation cancellation unit removing second order intermodulation caused by an out-of-band jamming or interference signal included in the signal output from the low noise amplifier; a passive mixer unit converting a frequency of the signal output from the second order intermodulation cancellation unit; and a low pass filter unit removing an out-of-band jamming or interference signal included in the signal output from the passive mixer unit and delivering the signal with the out-of-band jamming or interference signal removed therefrom to a transimpedance amplifier.

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: A current reuse device including a first stage provided with a first input for a first input signal and a first output for a first output signal; a second stage comprising a second input for a second input signal and a direct current terminal operating as a ground terminal for alternate signals; a first inductor connected to a first output and to the direct current terminal so that the first and second stages share a direct current; a second inductor reciprocally coupled to the first inductor and connected to the second input in order to generate the second input signal as a function of the first output signal.

Abstract: A folded cascode operational amplifier is disclosed. The folded cascode operational amplifier includes a first current source, a second current source, and a first voltage terminal connected to the first current source and the second current source. The folded cascode operational amplifier also includes a first input-transistor connected to the first current source in series, and a second input-transistor connected to the second current source in series. Further, the folded cascode operational amplifier includes a tail current source connected to a connection point between the first input-transistor and the second input-transistor, a load current source, and a second voltage terminal connected to the tail current source and the load current source. The folded cascode operational amplifier also includes an output-transistor connected to the load current source, and an output-terminal arranged between the second current source and the second input-transistor and connected to the output-transistor.

Abstract: Disclosed herein is a gyrator circuit, including, a first transconductance amplifier, a capacitor, and a second transconductance amplifier, wherein the differential input terminals of the first transconductance amplifier and the differential output terminals of the second transconductance amplifier being separated from each other.

Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.