Including Differential Amplifier Patents (Class 330/252)
  • Patent number: 8320846
    Abstract: An amplifier includes a separating unit, a generator, first to fourth switching amplifiers, and an outputting unit. The separating unit separates a pulse signal into a first separated pulse signal and a second separated pulse signal. The generator generates first to fourth low speed pulse signals by using the first and the second separated pulse signal. The first switching amplifier amplifies the first low speed pulse signal. The second switching amplifier amplifies the second low speed pulse signal by using the output of the first switching amplifier as a power-supply. The third switching amplifier amplifies the third low speed pulse signal. The fourth switching amplifier amplifies the fourth low speed pulse signal by using the output of the third switching amplifier as a power-supply. The outputting unit combines and outputs the first and the second output pulse signal.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: November 27, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayuki Kato
  • Publication number: 20120293258
    Abstract: This application describes a system for minimizing the common mode voltage drift at the input of a fully differential amplifier. An impedance component is coupled to the inputs and outputs of the differential amplifier. The impedance component optimizes the common mode resistance or impedance to ground without significantly affecting the differential impedance, matches the input common mode voltage to the output common mode voltage and reduces the input common mode voltage drift in presence of leakage currents.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 22, 2012
    Applicant: Infineon Technologies AG
    Inventors: Andrea Fant, Luca Sant, Patrick Vernei Torta
  • Patent number: 8314658
    Abstract: A power amplifier comprises a plurality of primary inductors provided on a substrate in a circular geometry as a whole; a plurality of amplifier pairs; a secondary inductor; and a connection wiring. Each amplifier pair is coupled to two ends of a corresponding primary inductor, and amplifies and output to the corresponding primary inductor a pair of first and second signals given as differential input signals, respectively. The secondary inductor is provided adjacent to the primary inductors in a circular geometry, further combines and outputs signals made by combining first and second signals in each primary inductor. The connection wiring is provided inside the primary inductors on the substrate and electrically couples middle points of respective primary inductors with each other.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Satoshi Yamakawa
  • Publication number: 20120281991
    Abstract: A differential amplifier capable of canceling an input offset current and expanding a linearly operating range is disclosed. The differential amplifier, which is preferably applicable to an optical receiver to convert a photocurrent into a voltage signal, includes a trans-impedance amplifier and an offset canceller that detects output offset and extracts input current to cancel the output offset. Moreover, the extracted input current traces the average level of the input voltage to widen the linearly operating range of the trans-impedance amplifier.
    Type: Application
    Filed: May 2, 2012
    Publication date: November 8, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yoshiyuki SUGIMOTO
  • Publication number: 20120274401
    Abstract: An object is to suppress operation delay caused when a semiconductor device that amplifies and outputs an error between two potentials returns from a standby mode. Electrical connection between an output terminal of a transconductance amplifier and one electrode of a capacitor is controlled by a transistor whose channel is formed in an oxide semiconductor layer. Consequently, turning off the transistor allows the one electrode of the capacitor to hold charge for a long time even if the transconductance amplifier is in the standby mode. Moreover, when the transconductance amplifier returns from the standby mode, turning on the transistor makes it possible to settle charging and discharging of the capacitor in a short time. As a result, the operation of the semiconductor device can enter into a steady state in a short time.
    Type: Application
    Filed: April 23, 2012
    Publication date: November 1, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Kazunori WATANABE
  • Publication number: 20120268204
    Abstract: Apparatus and methods for equalization are provided. In one embodiment, an apparatus for equalizing an input voltage includes a first capacitor and a first resistor having a first end and a second end, the first end configured to receive the input voltage. The apparatus further includes a second resistor having a first end electrically connected to the second end of the first resistor at an output node. The apparatus further includes an inverting voltage buffer for substantially inverting the input voltage to generate an inverted input voltage. The apparatus further includes a transconductance buffer for receiving the inverted input voltage and for generating a current from a first end of the first capacitor to the output node having a magnitude equal to about the magnitude of the input voltage signal divided by the impedance of the first capacitor.
    Type: Application
    Filed: April 25, 2011
    Publication date: October 25, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventors: Michael St. Germain, Jennifer Lloyd, Kimo Tam
  • Publication number: 20120268207
    Abstract: An integrated circuit includes an input unit and a voltage level detecting unit. The input unit is configured to output differential amplification signals corresponding to differential input signals in response to a voltage level detection signal. The voltage level detecting unit is configured to detect a voltage level of the differential amplification signals and output the voltage level detection signal.
    Type: Application
    Filed: December 21, 2011
    Publication date: October 25, 2012
    Inventor: Kwan-Dong KIM
  • Patent number: 8295408
    Abstract: A differential amplifier stage under a band design whereby a data signal at a maximum transfer rate among received waveforms is subjected to attenuation upon passing through a transmission line is not amplified, and a signal at a transfer rate half the maximum transfer rate is amplified. If it is determined that a signal whose amplitude is larger in value than a high reference voltage, the signal is determined as a signal “1” while if smaller in value than a low reference voltage, the signal is determined as a signal “0”. If the first amplitude detector detects that the amplitude of the signal is smaller in value than the high reference voltage, and the second amplitude detector detects that the amplitude of the signal is larger in value than the low reference voltage, the present signal is determined as an inverting signal of an immediately preceding signal.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: October 23, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Ushio, Takashi Muto
  • Publication number: 20120262235
    Abstract: A differential output stage configured for receiving differential input signal comprising first and second signals, comprising a first output for providing a first output signal, and a second output providing a second output signal, the first and second output signals together forming a differential output signal, a first voltage buffer and first controlled current source each connected to the first output, the first voltage buffer being driven by a signal in-phase with the first input signal, the first controlled current source being driven by a signal in-phase with the second input signal, and a second voltage buffer and second controlled current source each connected to the second output, the second voltage buffer being driven by a signal in-phase with the second input signal, the second controlled current source being driven a signal in-phase with by the first input signal.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 18, 2012
    Applicant: NXP B.V.
    Inventor: Gian HOOGZAAD
  • Patent number: 8289083
    Abstract: A circuit topology in accordance with a system, method and device for an active power splitter with an input and at least two outputs which allows the use of negative feedback and thus improving stability and linearity without substantially increasing the noise figure of the system is provided.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: October 16, 2012
    Assignee: ViaSat, Inc.
    Inventors: Gaurav Menon, Nitin Jain, David W. Corman
  • Patent number: 8283980
    Abstract: An amplifier circuit includes an amplifier unit and a current control circuit as means for achieving the aforementioned object. The amplifier unit includes a gain compensation MOS transistor compensating for gain of an output characteristic and a linearity compensation MOS transistor compensating for linearity of an output characteristic. A source of the gain compensation MOS transistor is connected to a drain of the linearity compensation MOS transistor. An input signal is applied to a gate of the linearity compensation MOS transistor. A drain of the gain compensation MOS transistor is set as an output. The current control circuit performs control so as to pass predetermined current between the drain and the source of the gain compensation MOS transistor and pass predetermined current between the drain and the source of the linearity compensation MOS transistor.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: October 9, 2012
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Arai, Masahiro Kudo, Shinji Yamaura
  • Publication number: 20120249242
    Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, a method includes providing a first differential amplification block, providing a second differential amplification block, electrically connecting the first and second differential amplification blocks in a stack between a first voltage reference and a second voltage reference, amplifying a first signal using the first differential amplification block, and amplifying a second signal using the second differential amplification block. A voltage difference between the first and second voltage references defines a power supply voltage, and the first differential amplification block operates over a first range of the power supply voltage and the second differential amplification block operates over a second range of the power supply voltage.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 4, 2012
    Applicant: Analog Devices, Inc.
    Inventor: Marc Goldfarb
  • Publication number: 20120249241
    Abstract: A trans-impedance amplifier (TIA) for a light-receiving circuit is disclosed where the TIA reduces the power consumption as suppressing the degradation of the signal quality in high frequency regions. The TIA comprises a primary core, a dummy core, and a differential amplifier that receives each output of two cores in the differential mode. Two cores have an arrangement substantially same to each other except that the power consumption thereof is smaller in the dummy core. Because the output impedance of two cores becomes substantially equal, the scattering parameter of the common mode to the differential mode at the output of the primary core becomes small enough.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 4, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Akihiro MOTO, Keiji TANAKA
  • Patent number: 8279003
    Abstract: An RF amplifier including first and second branches coupled in parallel between first and second supply voltage terminals, and a differential pair including first and second transistors each having first and second main current terminals, the second main current terminal of the first transistor being coupled by a first capacitor to the first main current terminal of the second transistor, and the second main current terminal of the second transistor being coupled by a second capacitor to the first main current terminal of the first transistor, wherein the first branch includes a first resistor coupled between the first main current terminal of the first transistor and the second capacitor, and the second branch includes a second resistor; coupled between the first main current terminal of the second transistor and the first capacitor.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: October 2, 2012
    Assignee: STMicroelectronics (Grenoble) SAS
    Inventors: Olivier Touzard, Fabien Sordet
  • Patent number: 8274330
    Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: September 25, 2012
    Assignee: Black Sand Technologies, Inc.
    Inventors: Susanne A. Paul, Timothy J. Dupuis
  • Publication number: 20120235744
    Abstract: The disclosure relates to a driving method for obtaining a linear gain variation of a transconductance amplifier that includes a first differential transistor cell, with adjustment of a driving voltage value of a degenerative driving transistor of the transconductance amplifier The method includes generating an output current signal of a second differential cell corresponding to the first differential transistor cell of the transconductance amplifier, the output current signal having a linear relationship with a transconductance value of the second differential cell as the driving voltage varies; generating a reference current signal having a linear relationship with a differential input voltage; comparing the output current signal and the reference current signal for adjusting the driving voltage value; and modifying the transconductance value of the second differential cell up to a balance of the current signals.
    Type: Application
    Filed: May 29, 2012
    Publication date: September 20, 2012
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Matteo Albertini, Daniele Ronchi, Sandro Rossi, Giulio Ricotti
  • Patent number: 8270846
    Abstract: A plurality of inductors are connected in series between a load resistor and a first transistor, and a plurality of second transistors provided in parallel are connected to the plurality of inductors.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: September 18, 2012
    Assignee: Fujitsu Limited
    Inventor: Yukito Tsunoda
  • Patent number: 8269557
    Abstract: An electronic amplifier is characterized by a first stage (1) controlled by an input voltage UE, the operating voltage of said stage being on positive and/or negative potentials (V1+/V1A?), which are always constant with respect to the input voltage (UE), and further by a second impedance-converting stage (2), which is controlled by a voltage supplied by the first stage (1) and the operating voltage of which is on positive and/or negative potentials (V5+/V5A?), which are always constant with respect to the voltage supplied by the first stage (1).
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: September 18, 2012
    Inventor: Klaus Zametzky
  • Publication number: 20120229213
    Abstract: To provide an envelope tracking type amplifier that has high efficiency and small fluctuations, an output unit supplies an output signal that is adjusted corresponding to an input signal to a power supply terminal of the amplifier. The output unit includes an analog amplifying circuit that amplifies the input signal; a digital circuit that selectively outputs a first voltage or a second voltage that is lower than the first voltage; and first and second output circuits. The first output circuit includes a first integrating circuit that integrates an output signal of the digital circuit; and a combining section that combines an output signal of the first integrating circuit and an output signal of the analog amplifying circuit and outputs the combined signal to a power supply terminal of the amplifier.
    Type: Application
    Filed: October 28, 2010
    Publication date: September 13, 2012
    Inventor: Yuji Takahashi
  • Patent number: 8264253
    Abstract: Disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: September 11, 2012
    Assignee: Intel Corporation
    Inventors: Kathy Tian, Harry Muljono
  • Publication number: 20120224443
    Abstract: A sense amplifier includes a first transistor, a second transistor, an output circuit, and a shielding circuit. The first transistor has a gate bias established by a cell current, and the second transistor has a gate bias established by a reference current. The output circuit is coupled to the first and the second transistor. The shielding circuit is located between the second transistor and the output circuit.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 6, 2012
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • Patent number: 8258867
    Abstract: A front-end equalizer and amplifier circuit includes two pairs of fully differential pair transistors, wherein the tail currents of one pair of transistors are connected with ground and connected with each other through the capacitive component to realize the connection between the pair of transistors and the feedback capacitor, the tail currents of the other pair of transistors are connected with ground and connected with each other through the resistive component to realize the connection between the other pair of transistors and the feedback resistor, the output positive and negative ends of each pair of transistors are connected with each other through the inductive component, thus forming the load for connecting the voltage source. The circuit increases the high frequency gain. Its single-stage gain is equivalent to the multi-stage gain. Compared with the traditional multi-stage structure, the present invention decreases the power consumption and area, and improves the reliability.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: September 4, 2012
    Assignee: IPGoal Microelectronics (Sichuan) Co., Ltd.
    Inventor: Ziche Zhang
  • Patent number: 8248164
    Abstract: Apparatus and methods for an integrated circuit, single ended-to-differential amplifier are provided. In an example, the amplifier can include an amplifier circuit having a first input configured to receive a single-ended signal, a second input, and a differential output configured to provide an amplified representation of the single-ended signal. The amplifier can include a filter circuit configured to balance a common-mode voltage between the first and second inputs of the amplifier circuit. The filter circuit can include a common-mode input configured to receive the common-mode voltage, a first impedance network coupled between the common-mode input and the first input of the amplifier circuit, and a second impedance network coupled between the common-mode input and the second input of the amplifier circuit. The filter circuit can provide a low frequency pole below 1 hertz.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: August 21, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Andrew M. Jordan, Hrvoje Jasa
  • Publication number: 20120206200
    Abstract: A programmable current driver provides de-emphasis capability. A number of identical transmitter slices, consisting of a unit current source and a unit differential pair, are connected in parallel to the termination resistors. As the transmitter slices are identical, the current density through the differential pairs are identical, and the VDS voltages across them (as well as the VDS voltages across the unit current sources) are the same, ensuring that the current through each slice is identical (within the limits of device matching). Biasing circuitry ensures that each unit current source sinks a current having a fixed proportion to the total current.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 16, 2012
    Applicant: Cavium, Inc.
    Inventor: Mark Spaeth
  • Patent number: 8237693
    Abstract: The present invention enables rising and falling slew rates to be symmetrized and secures a drive current at the time of 2H inversion driving. An operational amplifier in accordance with one aspect of the present invention includes: a first output transistor and a second output transistor connected in series between a first power supply and a second power supply; an output terminal connected to a node between the first output transistor and the second output transistor; a phase-compensating element provided either between the gate of the first output transistor and the output terminal or between the gate of the second output transistor and the output terminal; and a floating current source connected between the gate of the first output transistor and the gate of the second output transistor.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: August 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kouichi Nishimura, Atsushi Shimatani
  • Patent number: 8232828
    Abstract: There is provided an analog circuit having improved response time. An analog circuit having improved response time may include: a low level limiter converting a signal having a lower level than a predetermined reference level into a signal having a predetermined non-low level higher than the predetermined reference level; and an analog circuit section amplifying the signal from the low level limiter into a signal having a predetermined level.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: July 31, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Shinichi Iizuka, Sang Hee Kim, Jun Kyung Na, Sang Hoon Ha
  • Patent number: 8228120
    Abstract: Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: July 24, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Peter J. Mole, Philip V. Golden
  • Publication number: 20120169421
    Abstract: An amplifying circuit includes a first circuit component configured to receive and amplify first and second input voltages to generate an output voltage. The first circuit component is formed by a first amplifier and a second amplifier. A second circuit component is configured to provide a first offset current that is associated with a first input current of the first amplifier. The first offset current compensates for variation in the first input current. A third circuit component is configured to provide a second offset current that is associated with a second input current of the second amplifier. The second offset current compensates for variation in the second input current.
    Type: Application
    Filed: December 7, 2011
    Publication date: July 5, 2012
    Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD.
    Inventors: GuoHua ZHONG, XiangSheng LI
  • Patent number: 8212614
    Abstract: A buffer stage includes a flipped voltage follower and an emitter follower. The flipped voltage follower is connected between a high voltage rail and a low voltage rail and includes an input and an output. The emitter follower is also connected between the high voltage rail and the low voltage rail and includes an input and an output. A resistor connects the output of the flipped voltage follower to the output of the emitter follower. The input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage. The output of the emitter follower provides an output of the buffer stage. A differential buffer stage can be implemented using a pair of such buffer stages. Such a differential buffer stage can provide the output stage for a fully differential operational amplifier.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: July 3, 2012
    Assignee: Intersil Americas Inc.
    Inventor: Gwilym Francis Luff
  • Publication number: 20120161868
    Abstract: A clock signal capable of changing the frequency in a wide range and with high resolution is generated. An operational amplifier AMP1 is subject to feedback control so that the voltage of a positive input part equals that of a negative input part. The voltage of a circuit node fbck equals a reference voltage VREFI. A decoder DEC decodes control signals CNT7 and CNT6 and turns on one of transistors T2 to T5. This configuration provides feedback control so that the voltage of the circuit node fbck equals the reference voltage VREFI. This significantly reduces the on-resistances of the transistors T2 to T5 and prevents the degradation of the frequency accuracy.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 28, 2012
    Inventors: Kosuke YAYAMA, Takashi Nakamura
  • Patent number: 8195109
    Abstract: A switched power amplifier contained in a circuit is implemented to receive a single-ended input signal and generate a single-ended output signal, the single-ended output signal being a power-amplified version of the single-ended input signal. The switched power amplifier provides high efficiency.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: June 5, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gireesh Rajendran, Apu Sivadas, Subhashish Mukherjee, Krishnaswamy Thiagarajan
  • Patent number: 8184083
    Abstract: Provided is an output buffer, which may be included in a source driver of a liquid crystal display (LCD) device. The output buffer may include a differential amplification unit and an output unit. The differential amplification unit may generate control currents by amplifying the difference between the voltages of an analog image signal and a signal output from the output buffer. The output unit outputs the amplified analog image signal in response to the control currents. The amount of bias current used to drive the differential amplification unit increases during a charge recycling period, and the amount of quiescent current flowing through the output unit decreases during the charge recycling period. The amount of the bias current used to drive the differential amplification unit decreases during a driving period, and the amount of the quiescent current flowing through the output unit increases during the driving period.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: May 22, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyu-young Chung
  • Publication number: 20120121273
    Abstract: An amplifier implementing with a common base circuit is disclosed. The amplifier includes the common base circuit, a current shunt, and a current supplement. The common base circuit receives an input current. The current shunt shunts the input current based on the average of the output of the pre-amplifier. The current supplement supplements a current shunted by the current shunt.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 17, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Makoto ITO, Taizo TATSUMI
  • Publication number: 20120119833
    Abstract: A buffer stage includes a flipped voltage follower and an emitter follower. The flipped voltage follower is connected between a high voltage rail and a low voltage rail and includes an input and an output. The emitter follower is also connected between the high voltage rail and the low voltage rail and includes an input and an output. A resistor connects the output of the flipped voltage follower to the output of the emitter follower. The input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage. The output of the emitter follower provides an output of the buffer stage. A differential buffer stage can be implemented using a pair of such buffer stages. Such a differential buffer stage can provide the output stage for a fully differential operational amplifier.
    Type: Application
    Filed: January 17, 2012
    Publication date: May 17, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventor: Gwilym Francis Luff
  • Patent number: 8179186
    Abstract: Techniques are disclosed for reducing off-state leakage current in a differential switching device. The techniques can be embodied, for example, in a method that includes receiving a differential input signal at a differential input of each of a primary switch and a dummy switch. In an enabled-state of the device, the method further includes passing the differential input signal to a differential output of the primary switch. In a disabled-state of the device, the method further includes canceling off-state leakage current at the differential output of the primary switch, by virtue of the dummy switch having its differential output reverse-coupled to the differential output of the primary switch. The method may further include preventing the dummy switch from passing signals other than off-state leakage signals. The techniques can be embodied, for instance, in a switching device.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: May 15, 2012
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Gregory M. Flewelling, Douglas S. Jansen
  • Publication number: 20120112835
    Abstract: An amplifier having an input transmission network with a plurality of input transformers having serially coupled primary windings. Each one of the input transformers has a secondary winding magnetically coupled to a corresponding one of the primary windings. The amplifier includes an output transmission network having a plurality of output transformers having serially coupled secondary windings. Each one of the output transformers has a secondary winding magnetically coupled to a corresponding one of the primary windings. The amplifier includes a plurality of amplifier sections, each one the sections having an input connected to a corresponding one of the secondary windings of the input transformers and an output connected to a corresponding one of the primary windings of the output transformers.
    Type: Application
    Filed: November 9, 2010
    Publication date: May 10, 2012
    Applicant: Raytheon Company
    Inventors: Jonathan P. Comeau, Matthew A. Morton, Edward W. Thoenes
  • Patent number: 8174318
    Abstract: Apparatus and methods are disclosed, such as those involving a transconductance amplifier. One such apparatus includes a transconductance amplifier comprising an input to receive an input voltage signal, and an output to provide an output current signal at least partly in response to the input voltage signal. The apparatus also includes a linearizer configured to remove non-linearity in the output current signal such that the output current signal is substantially linear when the input voltage signal is within a range; and a current booster configured to add a current to the output current signal such that the output current signal is substantially linear when the input voltage signal is outside the range. The current booster allows the amplifier to have a linear response to a larger voltage swing without adding noise.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: May 8, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Edmund Balboni
  • Publication number: 20120092069
    Abstract: A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch.
    Type: Application
    Filed: November 23, 2011
    Publication date: April 19, 2012
    Inventor: Scott C. McLeod
  • Publication number: 20120092068
    Abstract: A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining.
    Type: Application
    Filed: November 23, 2011
    Publication date: April 19, 2012
    Inventor: Scott C. McLeod
  • Patent number: 8154343
    Abstract: A low-power high dynamic range RF input stage (200) with a noiseless degeneration component, such as a capacitor (201), is provided. High dynamic range means a combination of low noise contribution by the stage (200) and a low level of intermodulation products occurring especially at high input levels. Low power means that the power consumption of a conventional input stage is about 5 times higher than the power consumption of the stage according to the invention, for the same noise, gain and distortion level. This new stage can be used in amplifiers, but also in the lower stage of double balanced mixers (300-400) commonly used in RF receivers, examples of which are applications, are provided.
    Type: Grant
    Filed: January 16, 2006
    Date of Patent: April 10, 2012
    Assignee: NXP B.V.
    Inventors: Oswald Josef Moonen, Marc Lambertus Vlemmings, Arnold Hendrik Neelen
  • Patent number: 8149955
    Abstract: A receiver arrangement includes a single ended multiband feedback amplifier, at least one single ended input, differential output mixer arrangement including a main mixer and a trim mixer, and a mixer feedback loop circuit configured to receive differential output signals generated by the mixer arrangement. The mixer feedback loop circuit generates a feedback signal based on the received differential output signals and provides the feedback signal to the mixer arrangement to minimize DC-offset and second order intermodulation products. The single ended multiband feedback amplifier may include an input stage and a programmable resonance tank circuit connected to the input stage for suppressing downconverted noise from harmonics of the LO-frequency, and a configurable feedback net that shapes the frequency response of a feedback loop including the feedback net based on a band operation of the single ended multiband feedback amplifier.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: April 3, 2012
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Tobias Tired
  • Patent number: 8143948
    Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: March 27, 2012
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Farhood Moraveji
  • Patent number: 8139792
    Abstract: An amplifier circuit (100) has an input stage (OP1) and an output stage (Q1, Q2) operating with different supply voltages and different quiescent voltages. The output stage has a feedback input connected to receive a feedback signal from the output of the output stage. A biasing circuit (602) applies a bias signal (Ioff) to said input stage at an operating level appropriate to establish a quiescent output voltage different from a ground reference level of the input stage.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: March 20, 2012
    Assignee: Wolfson Microelectronics plc
    Inventor: Anthony James Magrath
  • Patent number: 8134814
    Abstract: A semiconductor integrated circuit, includes an operational amplifier including a first input terminal, a second input terminal, and an output terminal, a first transistor which has a source-drain route connected between an external terminal and a first voltage, and a gate terminal connected to the output terminal of the operational amplifier; and a second transistor which has a source-drain route connected between the first input terminal of the operational amplifier and the first voltage, and a gate terminal connected to the output terminal of the operational amplifier.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: March 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Masakazu Ikegami
  • Publication number: 20120056671
    Abstract: Apparatus and methods for an integrated circuit, single ended-to-differential amplifier are provided. In an example, the amplifier can include an amplifier circuit having a first input configured to receive a single-ended signal, a second input, and a differential output configured to provide an amplified representation of the single-ended signal. The amplifier can include a filter circuit configured to balance a common-mode voltage between the first and second inputs of the amplifier circuit. The filter circuit can include a common-mode input configured to receive the common-mode voltage, a first impedance network coupled between the common-mode input and the first input of the amplifier circuit, and a second impedance network coupled between the common-mode input and the second input of the amplifier circuit. The filter circuit can provide a low frequency pole below 1 hertz.
    Type: Application
    Filed: September 2, 2010
    Publication date: March 8, 2012
    Inventors: Andrew M. Jordan, Hrvoje Jasa
  • Publication number: 20120049960
    Abstract: A pre-driver includes first to fourth transistors and first and second impedance elements. The first transistor, coupled between the first output terminal and a first node, has a gate coupled to the first differential input terminal. The second transistor, coupled between the second differential output terminal and the first node, has a gate coupled to the second differential input terminal. The third transistor, coupled between the first differential output terminal and a second node, has a gate coupled to the first differential input terminal. The fourth transistor, coupled between the second differential output terminal and the second node, has a gate coupled to the second differential input terminal. The first and second impedance elements are coupled between the first differential output terminal and a third node, and coupled between the second differential output terminal and the third node, respectively, wherein the third node is biased to a preset voltage.
    Type: Application
    Filed: August 30, 2011
    Publication date: March 1, 2012
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventor: Jer-Hao HSU
  • Patent number: 8125272
    Abstract: In one embodiment, an apparatus includes a first amplification block configured to receive a signal. A second amplification block is configured to output the signal where the outputted signal is amplified. The isolation circuit allows reuse of a current flowing through the second amplification block by coupling the current to pass through the first amplification block. Also, the isolation circuit provides isolation between the first amplification block and the second amplification block to restrict the signal from flowing through the isolation circuit.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: February 28, 2012
    Assignee: Marvell International Ltd.
    Inventor: Thart Fah Voo
  • Patent number: 8120425
    Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: February 21, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Ayman A. Fayed, Russell Byrd, Baher Haroun
  • Patent number: 8120424
    Abstract: A buffer stage includes a flipped voltage follower and an emitter follower. The flipped voltage follower is connected between a high voltage rail and a low voltage rail and include an input and an output. The emitter follower is also connected between the high voltage rail and the low voltage rail and includes an input and an output. A resistor connects the output of the flipped voltage follower to the output of the emitter follower. The input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage. The output of the emitter follower provides an output of the buffer stage. A differential buffer stage can be implemented using a pair of such buffer stages. Such a differential buffer stage can provide the output stage for a fully differential operational amplifier.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: February 21, 2012
    Assignee: Intersil Americas Inc.
    Inventor: Gwilym Francis Luff
  • Publication number: 20120039487
    Abstract: An external audio signal is input to an input terminal which is connected to the first terminal of a first resistor. The first terminal of a second resistor is connected to the second terminal of the first resistor. An operational amplifier is arranged such that its inverting input terminal is connected to the second terminal of the second resistor, and a reference voltage is applied to its non-inverting input terminal. A third resistor is arranged between the output terminal and the inverting input terminal of the operational amplifier. A first diode is arranged between the second terminal of the first resistor and a power supply terminal such that its cathode is on the power supply terminal side. Furthermore, a second diode is arranged between the second terminal of the first resistor and the ground such that its cathode is on the second terminal side of the first resistor.
    Type: Application
    Filed: October 25, 2010
    Publication date: February 16, 2012
    Applicant: ROHM CO., LTD.
    Inventor: Mitsuteru SAKAI