Abstract: A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Abstract: Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error correction unit is configured to execute error correction processing of correcting the error when the error occurs. The adjustment control unit is configured to start adjustment processing of adjusting a transmission characteristic of the interface when the error occurs.

Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus determines at least one time-frequency resource among resources of a cellular communication system to be used for device-to-device (D2D) communication, identifies a propagated start point of a first portion of the at least one time-frequency resource, and begins transmission of the D2D signal from a transmission start point. The transmission start point is based on the propagated start point and a cellular communication system downlink timing offset to the propagated start point. The apparatus also identifies a propagated end point of a last portion of the at least one time-frequency resource and ends transmission of the D2D signal at a transmission end point. The transmission end point is based on the propagated end point and a cellular communication system downlink timing advance to the propagated end point.

Abstract: In an audio processing apparatus configured to supply audio data to a processor configured to process audio data, a plurality of receivers, each configured to receive audio data and a work clock carried with the audio data and to supply the audio data to the processor; a plurality of PLL circuits corresponding to the plurality of receivers, each PLL circuit being configured to generate a clock signal based on a word clock received by the corresponding receiver; and a selector configured to select a clock signal from among a plurality of clock signals generated by the plurality of PLL circuits, and to supply the selected clock signal to the processor, the processor outputting the processed audio data at timing synchronized with the selected clock signal are provided.

Abstract: Technology is described for an asynchronous wrapper circuit for a clock gating cell (CGC). In one example, the asynchronous wrapper cell for CGC includes circuitry configured to (1) sample a data channel via sampling circuitry for a communication start signal to enable the CGC to start a gated clock for a data message on the data channel, and (2) reset an enable of the CGC to an idle mode via idle mode control circuitry after the data message has been clocked via the CGC through function cell circuitry. The idle mode control circuitry generates an output for the sampling circuitry from the function cell. Various other computing circuitries are also disclosed.

Abstract: A broadband digital transmitter is disclosed. The digital transmitter includes a vector decomposer circuit, a phase selector circuit, and a digital power amplifier (DPA). The vector decomposer circuit receives baseband in-phase (I) and quadrature (Q) signals and decomposes the baseband I and Q signals into an offset envelope signal and a non-offset envelope signal. The phase selector circuit receives a plurality of phase offset local oscillator (LO) signals and outputs, responsive to the baseband I and Q signals, offset LO signals and non-offset LO signals. The DPA processes the offset envelope signal, the non-offset envelope signal, the offset LO signals, and the non-offset LO signals to generate an output signal of the digital transmitter.

Abstract: An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circuit.

Abstract: Certain aspects of the present disclosure provide techniques for wireless communications, wherein first number of transit antennas is advertised, but a different number of transmit antennas are actually used for transmission.

Abstract: A data communication system includes a master and a slave. The master transmits a first subject signal including a first subject data to the slave via a transmission line. The slave extracts a clock signal from the first subject signal by performing a clock data recovery process and determines the first subject data based on the first subject signal. The slave transmits a second subject signal including a second subject data to the master during an existing period of the first subject signal without interfering an extracting of the clock signal and a determination of the first subject data. The master receives the second subject signal and cancels a waveform component of the first subject signal from a waveform of the second subject signal, and then determines the second subject data based on the second subject signal.

Abstract: Described are embodiments of methods, apparatuses, and systems for time synchronization of a multi-protocol I/O interconnect of computer apparatus. A method for synchronizing time across the multi-protocol I/O interconnect may include determining a first local time at a first port of a first switch of a switching fabric of a multi-protocol interconnect and a second local time at a second port of a second switch of the switching fabric, calculating an offset value based at least in part on a difference between the first local time and the second local time, and adjusting the second local time by the offset value. Other embodiments may be described and claimed.

Abstract: A signal comprising a first edge and a second edge is received. The first edge of the signal is synchronized with a first clock and the synchronized first edge of the signal is passed to an output. The synchronization results in a delay of the first edge of the signal. The second edge of the signal is passed to the output. The passed second edge of the signal has a delay that is less than the delay of the first edge of the signal by at least one clock cycle of the first clock.

Abstract: Embodiments are disclosed for a device for determining a presentation time for a generated packet. An example device includes a communication interface communicatively connectable to another device and configured to transmit data, a processor, and a storage device that stores instructions executable by the processor to receive a stream packet, extract a timestamp from the stream packet, and add one or more offsets to the extracted timestamp to determine a presentation time. The instructions are further executable to transmit a generated packet, the generated packet including an indication of the determined presentation time.

Abstract: A scheme is described that provides for a low latency, glitch free chip interface that does not require a clock. This invention handles input transitions that are skewed and also input transitions that are momentary. A change in an input state initiates a pulse that propagates through the system and samples the new input state after a delay. If there is a difference between the sampled input state and the present input state, then a new pulse is initiated in order to avoid any illegal transitions at the output.

Abstract: A synchronization module is associated with a network node of a communication network which includes at least one Synchronization Master entity. The synchronization module has knowledge of a plurality of Synchronization Master references. Endpoints of paths of the plurality of Synchronization Master references are obtained. Each of the paths extends between one Synchronization Master entity and the first or the second access network node. The paths are obtained from a synchronization report module based on the obtained endpoints. For each of the Synchronization Master references, a first path and a second path of the obtained paths are selected. A time synchronization inaccuracy value between the first and the second access network node is calculated based on the selected paths. A Synchronization Master reference is selected based on the calculated time synchronization inaccuracy values, and the first and the second access network nodes are notified which Synchronization Master reference was selected.

Abstract: Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (RF) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the RF circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The RF circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.

Abstract: Provided is a wireless signal receiver including: an analog-digital converter (ADC) converting an analog RF signal into a digital baseband signal; and a sub-sampling block dividing and processing the digital baseband signal into a first path signal and a second path signal, and extracting a complex baseband signal by using a relative sample delay difference between the first and second path signals, wherein the first path signal is a signal obtained by adjusting a sample delay and sampling rate of the digital baseband signal, and the second path signal is a signal obtained by filtering without adjusting the sampling rate of the digital baseband signal.

Abstract: A parallel interface is disclosed. The parallel interface of the present disclosure includes an input unit configured to input, in parallel, a plurality of predetermined data signals and a clock signal; an output unit configured to output, in parallel, the predetermined data signals in synchronization with the clock signal; and a plurality of transmission lines disposed between the input unit and the output unit and configured to transmit, in parallel, the predetermined data signals and the clock signal, wherein the transmission lines are configured with a wiring pattern in which the transmission lines have different electrical lengths and an equal electrical capacitance.

Abstract: In some embodiments, a system comprises a clock, a root node, a radio channel network, and first and second child nodes. The clock may be configured to generate a clock signal. The root node may be configured to generate a first frame including a first payload and a first overhead and generate a second frame including a second payload and a second overhead. The first and second overheads may comprise a synchronization value based on the clock signal. The radio channel network may be in communication with the root node for transmitting the first and second frames. Each first and second child nodes may be configured to perform clock recovery including frequency synchronization using the synchronization value and a respective phase-lock loop.

Abstract: A time control apparatus provided in a slave machine and synchronizing time information with time information of a master machine connected over a network includes: calculation units respectively calculating time difference candidates of the slave machine with respect to the master machine and network delays indicative of an average of times necessary for communication of first and second messages over the network based on transmission and reception times of the first messages which are transmitted from the master machine and received using the slave machine and transmission and reception times of the second messages which are transmitted from the slave machine and received using the master machine; a selection unit selecting one of the calculated time difference candidates as a time difference based on the calculated network delays; and an adjustment unit adjusting the time information of the slave machine based on the selected time difference.

Abstract: Aligning FIFO pointers includes resetting, by a write control block coupled to a write side of the FIFO, write pointers to an initial value. Then, iteratively, until one or more bits retrieved from the write side match one or more bits of an alignment bit pattern: providing, by the write side to the read side, the alignment bit pattern; retrieving, by the read side, one or more bits from the write side; providing, by the read side through a read control block, the retrieved one or more bits to the write control block; determining, by the write control block, whether the retrieved one or more bits match one or more bits of the alignment bit pattern; and, if the retrieved one or more bits do not match one or more bits of the alignment bit pattern, suppressing the read pointer from incrementing for a predetermined period of time.

Abstract: Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.

Abstract: An apparatus used to communicate with a plurality of audio/video (A/V) end nodes in an Audio Video Bridging (AVB) network. The apparatus may include a first A/V end node. The first A/V end node may be configured to transmit a clock reference stream including a plurality of timestamps to a plurality of A/V end nodes. The plurality of A/V end nodes may transmit a media stream including a plurality of video samples and a plurality of audio samples to one another. The media stream may be separate from the plurality of timestamps. The plurality of A/V end nodes may be arranged to syntonize or synchronize the plurality of video samples and the plurality of audio samples with one another for playback in response to the plurality of timestamps.

Abstract: Systems and methods of generating an RF stimulus signal with different power levels for IC testing. A DC modulating signal is used to power modulate a radio frequency (RF) carrier signal and thereby generate an RF stimulus signal at varying power levels. The DC modulating signal includes a sequence of DC waveforms at different voltage levels. A DC voltage transition in the modulating signal instantaneously triggers the transition of an output power in the RF stimulus signal. Reference waveforms that can cause a known response pattern in a DUT may be added at the beginning of the modulating signal for data calibration purposes.

Abstract: The present disclosure relates to a method for facilitating synchronization in a wireless communication system. A number sequence of length L is defined. The number sequence is mapped on a first set of discrete Fourier frequency coefficients. A second set of discrete Fourier frequency coefficients is generated by frequency shifting the first set of discrete Fourier frequency coefficients. The second set of discrete Fourier frequency coefficients is transformed into a time domain signal.

Abstract: A signal processing device that generates an output signal from image data by using a clock corresponding to the pixels of the image data, the signal processing device includes: a delayed signal group generating unit that generates a group of delayed signals with a delay element group formed with stages of delay elements; a clock adjusting unit that generates a modulation/synchronization clock from the group of delayed signals by referring to phase data matching the clock with a predetermined phase and frequency modulation coefficient data converting the clock to a predetermined frequency; and a PWM processing unit that generates a PWM signal from the group of delayed signals by referring to the phase data, the frequency modulation coefficient data, the modulation/synchronization clock, and the image data, the PWM signal having a pulse width corresponding to the value of the image data.

Abstract: An optical line terminal transmitter front-end, an optical network terminal receiver front-end and a bit-interleaved passive optical network (BIPON). In one embodiment, the transmitter front-end includes: (1) a bit interleaver configured to group and interleave a plurality of user bit-streams to yield a combined single bit-stream, (2) an encoder coupled to the bit interleaver and configured to encode multiple bits of the single bit-stream into a multi-level code corresponding to a 2m-level multi-level signal and (3) a multi-level modulator coupled to the encoder and configured to modulate the multi-level code into the 2m-level multi-level signal.

Abstract: Disclosed are a method and device for increasing the adaptability of light intensity, which relate to the field of photoelectric communications. The method comprises: providing several stages of load resistors in the device, the device collecting voltage values, calculating the average value of all the collected voltage values when a preset number of voltage values which meet the requirements are collected, setting a voltage according to the average value and judging whether the set voltage meets preset requirements; and if yes, collecting data according to the set voltage; otherwise switching a load resistor according to a preset rule, wherein the load voltage may affect the voltage collection. The present invention has the beneficial effects of: improving the adaptability of a screen to light intensity during optical signal collection, and at the same time being able to reduce the error rate.

Abstract: A data stream that contains periodic time reference values referenced to a first reference clock is received for transcoding. The received data stream is processed to form an output data stream that contains the periodic time reference values. At least one of the periodic time reference values is adjusted by adding a count value to the at least one periodic reference value to form an adjusted periodic time reference value. The output data stream is transmitted with the adjusted periodic time reference value.

Abstract: A system and method synchronizes multi-AWG system, where such systems are of a type having a master arbitrary waveform generator (AWG), one or more slave AWGs, and a sync hub having a sync controller and sync phase detector. The method operates by receiving at the sync hub a divided down clock (SystemRefClock) signal from a master arbitrary waveform generator (AWG). The method then derives a clock signal (SystemClock) from the SystemRefClock signal received from the master AWG and outputs the SystemClock signal to the master AWG and to the one or more slave AWGs Finally, the SystemClock signal is used to clock a synchronous trigger for the master AWG and one or more slave AWGs to play a waveform. In one aspect, the synchronous trigger includes AlignmentFiducial and Run signals to effect trigger and play commands.

Abstract: For a baseband digital front-end (BDFE) processor that communicates with one or more radio-frequency integrated circuit (RFIC) chips over two or more JESD-compliant links in a multi-antenna base station, the BDFE has JESD transmitters (TXs) and receivers (RXs) that transmit and receive data to and from the RFIC chips and a time-based generator (TBGEN) that generates sync and idle signals that ensure that the processing of the different JESD TXs and RXs are aligned in time for data associated with a single logical group of antennas. The TBGEN has hardware-based alignment circuitry that generates the sync and idle signals, thereby avoiding the latency and unpredictability inherent with software-based solutions.

Abstract: A clock and data recovery (CDR) circuit produces an in-phase clock, a quadrature clock offset by 90 degrees from the in-phase clock, and an auxiliary clock offset from the in-phase clock by a fraction of 90 degrees. A data sampler cyclically samples a data signal to form sets of samples according to the in-phase, quadrature, and auxiliary clocks, each set comprising an in-phase sample, a quadrature sample, and an auxiliary sample. A CDR logic circuit processes the samples to form a timing word for each set.

Abstract: In one embodiment, a processor includes at least one execution unit to execute instructions, and a logic to obtain a value of a virtual time counter based on a scale factor that corresponds to a ratio of a first frequency of a first platform to a second frequency of a second platform that includes the processor. The processor is to execute guest software that is migrated from the first platform to the second platform using the value of the virtual time counter obtained by the logic. Other embodiments are described and claimed.

Abstract: The implementation of serial transmission protocols typically involves the transmission of data in form of serial data streams over multiple serial communication links in parallel. Upon reception, the serial data streams are aggregated to implement a behavior equivalent to the transmission of the data over a single serial communication link. A high-speed serial communication receiver with a central alignment control circuit is provided that performs the identification of word boundaries within each serial data stream, the alignment of all the serial data streams, and the arrangement of the serial communication links in a given order. Using a single central alignment control circuit reduces the circuit area required for performing these operations, facilitates a reduced latency, and can easily control a simplified switching network.

Abstract: In the described embodiments, a processor core (e.g., a GPU core) receives a section of program code to be executed in a transaction from another entity in a computing device. The processor core sends the section of program code to one or more compute units in the processor core to be executed in a first transaction and concurrently executed in a second transaction, thereby creating a “redundant transaction pair.” When the first transaction and the second transaction are completed, the processor core compares a read-set of the first transaction to a read-set of the second transaction and compares a write-set of the first transaction to a write-set of the second transaction. When the read-sets and the write-sets match and no transactional error condition has occurred, the processor core allows results from the first transaction to be committed to an architectural state of the computing device.

Abstract: Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed.

Abstract: An apparatus and method for synchronizing a multimedia interface clock between a multimedia source device and a multimedia sink device connected over a wireless channel. The method comprises measuring a frequency of the source clock signal generated by the multimedia source device, wherein the measurement of the frequency is performed using a first reference clock signal; generating a frequency-stamp message including in part the measured frequency; encapsulating the frequency-stamp message in at least one packet; and transmitting the at least one packet to a wireless receiver connected to the multimedia sink device over the wireless channel.

Abstract: A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.

Abstract: The invention relates to direct digital receiver for an RF coil (11, 12, 13, 200), in particular of a magnetic resonance imaging system (1), for providing a digital sample output signal at a digital operating frequency in a time base of a system clock (222), the receiver comprising: —an analogue-to-digital converter (214) for converting an analogue signal received from the RF coil (11, 12, 13, 200) to a digital sample input signal, the analogue-to-digital converter (214) being driven by a local clock, a local clock oscillator (400) adapted for providing the local clock in a local clock time base to the analogue-to-digital converter (214), the local clock time base being independent of the system clock time base, a phase detector (402) adapted for determining a phase difference (512) between the system clock (222) and the local clock, a resampling unit (224) adapted for resampling the digital sample input signal to the digital sample output signal using said phase difference (512).

Abstract: The present subject matter includes a system for communications between a transmitter and a receiver. In various embodiments, the system uses a sleep interval to allow the receiver to go to sleep between wake up times to “sniff” for transmissions from the transmitter. The system adjusts the length of the preamble of the transmitted signal or a repetition of packets to allow the receiver to detect a transmitted signal based on drift in the clocks of the system. In various embodiments, a receive channel is changed if a signal is not received at a prior channel selection. In various embodiments, the transmission is determined by detection of an event. In various embodiments, the event is an ear-to-ear event. In various embodiments, the receiver and transmitter are in opposite hearing aids adapted to be worn by one wearer.

Abstract: Embodiments of the invention relate to a multi-scale spatio-temporal neural network system. One embodiment comprises a neural network including multiple heterogeneous neuron populations that operate at different time scales. Each neuron population comprises at least one digital neuron. Each neuron population further comprises a time scale generation circuit that controls timing for operation of said neuron population, wherein each neuron of said neuron population integrates neuronal firing events at a time scale corresponding to said neuron population. The neural network further comprises a plurality of synapses interconnecting the neurons, wherein each synapse interconnects a neuron with another neuron. At least one neuron receives neuronal firing events from an interconnected neuron that operates at a different time scale.

Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.

Abstract: A method and an apparatus are provided in an OFDM receiver for detecting and compensating for long echo. The method comprises a first pilot tone interpolation mechanism and a first window placement to filter a received OFDM symbol, a long echo channel detection coupled with a second pilot tone interpolation mechanism, a pre-echo and post-echo detection wherein the pre-echo condition is associated with a second new window placement, and both pre-echo and post-echo conditions place two time windows around a first peak channel response and a second peak channel response for channel estimation. The long echo is estimated by obtaining power spectra of a subset of subcarriers in one OFDM symbol, performing an inverse Fourier transform on the power spectra and determining the long echo by measuring the time between two peaks in the power profile.

Abstract: An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.

Abstract: There is provided a communication apparatus communicating with a master apparatus generating events at a constant time interval via a network, including: a clocking unit clocking a time; an event generator generating an event based on the clocking unit in accordance with event interval information specifying a time interval for event generation; a storage storing a first timestamp representing a time when the event is generated in the event generator; a receiver receiving, from the master apparatus, a frame containing a second timestamp representing a time of the event generated in the master apparatus; and an event interval corrector correcting the event interval information so as to make a timing of event generation in the event generator closer to a timing of event generation in the master apparatus based on the first timestamp, the second timestamp, and a pre-acquired time difference between the clocking unit and the master apparatus.

Abstract: A Synchronous Ethernet (SyncE) network device includes a pair of phase-locked loops including a first phase-locked loop responsive to a SyncE input clock and a second phase-locked loop coupled to the first phase-locked loop. The second phase-locked loop is configured to be simultaneously lockable to both the SyncE input clock via the first phase-locked loop and an IEEE 1588 packet stream, during a locked mode of operation, and also lockable to the SyncE input clock during a holdover mode of operation which is triggered in response to a failure of the IEEE 1588 packet stream.

Abstract: An apparatus for synchronizing two clock signals is disclosed. The apparatus may include a selection unit and circuitry. The selection unit may be configured to select a first or second clock signal as an output clock signal. A frequency of the first clock signal may be less than a frequency of the second clock signal. The circuitry may be configured to send a first signal to the selection unit, causing the selection unit to select the first clock signal. The circuitry may also be configured to send a second signal to the selection unit, causing the selection unit to select a subset of clock pulses of the second clock signal as the output clock signal. The subset of clock pulses of the second clock signal may include a clock pulse of the second clock signal corresponding to a transition of the first clock signal.

Abstract: Aspects of a method and system for efficient full resolution correlation may include correlating a first signal with a second signal at a rate corresponding to a first discrete signal, wherein each sample of the first signal may be generated by summing a plurality of consecutive samples from the first discrete signal, and the second signal may be generated by summing the plurality of consecutive samples from a second discrete signal. The correlating may be performed by a matched filter and/or a correlator. The first signal comprising N samples may be generated by summing L consecutive samples for each of the N samples from the first discrete signal comprising N*L samples. The second signal comprising N samples may be generated by summing L consecutive samples for each of the N samples from the second discrete signal comprising N*L samples.

Abstract: A computing system includes: a communication unit configured to: identify a first synchronization symbol and a second synchronization symbol corresponding to a synchronization signal, generate the synchronization signal including the first synchronization symbol and the second synchronization symbol using a synchronization generator mechanism and a prefix generator mechanism; and an inter-device interface coupled to the communication unit, configured to communicate the synchronization signal for synchronizing a first device and a second device for communicating a serving content.

Abstract: A circuit test system including a circuit test apparatus and a circuit to be tested is provided. The circuit test apparatus provides a first clock signal. The circuit to be tested includes a plurality of input/output pads and at least one clock pad. At least two input/output pads of the input/output pads are connected to each other to form a test loop during a test mode. The clock pad receives the first clock signal. The circuit to be tested multiplies a frequency of the first clock signal to generate a second clock signal, and the test loop of the circuit to be tested is tested based on the second clock signal during the test mode. The frequency of the second clock signal is higher than that of the first clock signal. Furthermore, a circuit test method of the foregoing circuit test system is also provided.

Abstract: The present disclosure relates to a method for facilitating synchronization in a wireless communication system. A number sequence of length L is defined. The number sequence is mapped on a first set of discrete Fourier frequency coefficients. A second set of discrete Fourier frequency coefficients is generated by frequency shifting the first set of discrete Fourier frequency coefficients. The second set of discrete Fourier frequency coefficients is transformed into a time domain signal.