Abstract: A system (1) for transferring a data signal (sig_fast) from a first clock domain (4) to a second clock domain (8). The first clock domain (4) has a first clock (ck_fast) with a frequency greater than the frequency of a second clock (ck_slow) in the second clock domain (8). The system (1) also has a signal input (10) for receiving an input signal (sig_fast) from the first clock domain (4), means (16, 18) for checking whether the second clock (ck_slow) is in a part of its cycle away from a forthcoming transition, and means (22) for transferring the input signal (sig_fast) to the second clock domain (8) if the checking means (16, 18) determines that the second clock (ck_slow) is in part of its cycle away from a forthcoming transition. The checking means (16, 18) are clocked by the first clock (ck_fast).

Abstract: A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.

Abstract: A method and system to enable interoperability between Internet enabled devices and online applications without traditionally agreeable on device standard formats between the manufacturer and applications ahead time. The application is able to connect, control, and actuate newly added devices at runtime.

Abstract: A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.

Abstract: Provided is a high-speed serial data receiving apparatus including: a clock converter configured to convert a serial clock into a parallel clock; a data converter configured to convert a serial data packet into N parallel data packets and outputting the N parallel data packets; a synchronization signal detector configured to receive the N parallel data packets and the parallel clock, and detecting a data start synchronization of the N parallel data packets output from the data converter by comparing the parallel data packets with a synchronization code of N bits set in advance; and an error compensation unit configured to detect and compensate for a skew between parallel clock and data.

Abstract: A method and device for sending a synchronization signal and a method and device for synchronization between base stations, include: determining, by a synchronization source base station according to a synchronization level of the synchronization source base station, a resource for sending an NLRS for clock synchronization between base stations, and according to the determined resource. In this way, one NLRS for clock synchronization between base stations is configured on each synchronization source base station, and the NLRS is sent on a resource determined according to a synchronization level, so that a synchronization base station that acquires the NLRS can determine the synchronization level of the synchronization source base station according to a resource for sending the NLRS.

Abstract: Disclosed is a transmitting apparatus that includes an uplink transmitting unit that generates at least two carrier transmission signals carrier and generates transmission control data corresponding to the carrier transmission signals, a Radio Frequency Front End (RFFE) that transmits the at least two carrier transmission signals, and a transmission controller including a storage unit and decoders. The transmission controller activates a decoder corresponding to transmission control data output from the uplink transmitting unit, and the activated decoder accesses information of the storage unit to control wireless transmission of the RFFE.

Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.

Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.

Abstract: The systems and methods for a twisted pair transceiver with correlation detection includes a transceiver system operating on a cable. The transceiver system includes a receiver to obtain one or more data samples related to one or more encoded data symbols. The transceiver system further includes a first correlation filter to generate a first correlation output based on the one or more data samples, and a second correlation filter to generate a second correlation output based on the one or more data samples. The transceiver system further includes a detector. The detector compares the first correlation output with the second correlation output, generates an output data bit based on a comparison result, and sends the output data bit for data decoding.

Abstract: An optical transmitter transmits an orthogonal frequency division multiplexing symbol in which only one-half of available subcarriers are modulated with data and the remaining subcarriers are suppressed by not modulating with data. The transmission is of duration equal to half the symbol period of the OFDM symbol, resulting in a half-cycle transmission. An optical receiver receives the half-cycle transmission OFDM symbol, regenerates the full time domain representation and recovers data modulated on the one-half of available subcarriers. The modulated subcarriers and the suppressed subcarriers alternate in the frequency domain.

Abstract: A master-slave flip-flop includes a master latch, a slave latch, a first logic gate and a signal transition detector. The first logic gate is receiving a reference clock and a first control clock, and outputting a first trigger signal to control one of the master latch and the slave latch, which are connected with a logic circuit, to switch to an opaque state or a transparent state, wherein the other one of the master latch and the slave latch is switched to an opaque state or a transparent state according to the reference clock. The above-mentioned master-slave flip-flop can correct sampling when a timing error occurs.

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

Abstract: A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

Abstract: The present disclosure discloses a proximity detection method and apparatus for a near field communication, which belongs to the field of communications technologies. The method includes: sending, by a first electronic device, a signal of a detection frame; determining whether a second electronic device capable of performing the near field communication exists according to a received response frame, wherein the detection frame includes at least two symbols modulated with different frequencies. In embodiments of the present disclosure, a signal of a detection frame which includes multiple symbols modulated with different frequencies is sent, so that a peer-to-peer electronic device existing within a communicatable range can be detected for communication in a case of that these modulation frequencies suffer an interference.

Abstract: Asynchronous bridge circuitry provides data communication between source circuitry 4 in a source clock domain and destination circuitry 12 in a destinations clock domain. The asynchronous bridge circuitry includes first-in-first-out buffer 20, transmission path circuitry 14, which has an input end coupled to the source circuitry and an output end coupled to the first-in-first-out buffer. The transmission path circuitry has a transmission delay corresponding to a plurality of source clock cycles. Write pointer circuitry 22 located within the source clock domain at the output end 18 of the transmission path circuitry so as to generate a write pointer for the first-in-first-out buffer. Transmission control circuitry 26 located within the source clock domain at the input end 16 of the transmission path circuitry is configured to generate a transmission control signal which controls whether or not the source circuitry is permitted to send data.

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.

Abstract: In an example implementation, an alignment detection circuit includes a buffer, a candidate selection circuit, and a correlator circuit. The buffer is configured to receive a data stream from a data lane, the data stream including alignment markers delineating data frames, each of the alignment markers having a predefined bit pattern. The candidate selection circuit is configured to identify candidate data blocks in successive data blocks of the data stream provided by the buffer, each of the candidate blocks having a measure of symmetry satisfying a threshold metric indicative of the predefined bit pattern. The correlator circuit is configured to search for at least one of the alignment markers in each of the candidate blocks and adjust alignment of the data stream in the buffer in response to locating the at least one alignment marker.

Abstract: Embodiments of the disclosure relate to systems and methods for determining asymmetric downlink and uplink propagation delays in a wireless distribution system (WDS) for more accurately determining propagation delay. In this regard, a WDS is configured to determine both the separate downlink and uplink propagation delays between a central unit and a plurality of remote units. It is not presumed that the downlink propagation delay and the uplink propagation delay in the WDS are symmetric to provide a more accurate determination of propagation delay. Therefore, it is possible to determine the downlink and uplink propagation delays with improved accuracy, thus enabling more precise location identification in the WDS.

Abstract: This application teaches a method for indicating voxel quality comprising graphically and/or mathematically. Such a method may include measuring a distance from the three-dimensional scanning device to an area of a subject corresponding to an image voxel. It may also include measuring an angle between a line of sight from the three-dimensional imaging device and an orthogonal ray of the same area of the subject corresponding to the same voxel. The process may further include comparing the measured distance and angle to known acceptable operating ranges of the scanner, and plotting a quality point corresponding to the foregoing metrics on a set of axes.

Abstract: A method of compensating for a round-trip transmission delay in an audio system comprising: a portable communications device; an audio accessory; and a cable, suitable for connecting the portable communications device and the audio accessory, having at least one wire and being detachable from at least one of the portable communications device and the audio accessory. At first times, a first synchronization data pattern is transmitted on the at least one wire from said device to said accessory, wherein said first synchronization data pattern comprises first signal level transitions on the at least one wire, synchronized to a master transmission clock. At second times, a second synchronization data pattern is transmitted on the at least one wire from said accessory to said device, wherein said second synchronization data pattern comprises second signal level transitions at timings that are set based on a delay value stored in said accessory.

Abstract: Methods and systems for obtaining improved joint channel estimates for a multi-user, frequency-multiplexed data transmission such as SC-FDMA or OFDM begins by estimating separate contributions of users (and/or other signal sources) to the received signal based on joint frequency domain channel estimates. A reduced data set is obtained by subtracting contributions of one or more users from the received data, leaving only the estimated contributions of the remaining users, with noise and residual estimation error signal. Time domain joint channel estimation is then performed on the reduced data set, which is feasible because the number of users has been reduced. In exemplary embodiments, the reduced data set includes only one estimated user contribution. This process is repeated to obtain time domain estimates for all of the users. The method can be repeated by using the TD channel estimates to re-estimate the user contributions and calculate revised TD channel estimates.

Abstract: A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Abstract: Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error correction unit is configured to execute error correction processing of correcting the error when the error occurs. The adjustment control unit is configured to start adjustment processing of adjusting a transmission characteristic of the interface when the error occurs.

Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus determines at least one time-frequency resource among resources of a cellular communication system to be used for device-to-device (D2D) communication, identifies a propagated start point of a first portion of the at least one time-frequency resource, and begins transmission of the D2D signal from a transmission start point. The transmission start point is based on the propagated start point and a cellular communication system downlink timing offset to the propagated start point. The apparatus also identifies a propagated end point of a last portion of the at least one time-frequency resource and ends transmission of the D2D signal at a transmission end point. The transmission end point is based on the propagated end point and a cellular communication system downlink timing advance to the propagated end point.

Abstract: Technology is described for an asynchronous wrapper circuit for a clock gating cell (CGC). In one example, the asynchronous wrapper cell for CGC includes circuitry configured to (1) sample a data channel via sampling circuitry for a communication start signal to enable the CGC to start a gated clock for a data message on the data channel, and (2) reset an enable of the CGC to an idle mode via idle mode control circuitry after the data message has been clocked via the CGC through function cell circuitry. The idle mode control circuitry generates an output for the sampling circuitry from the function cell. Various other computing circuitries are also disclosed.

Abstract: In an audio processing apparatus configured to supply audio data to a processor configured to process audio data, a plurality of receivers, each configured to receive audio data and a work clock carried with the audio data and to supply the audio data to the processor; a plurality of PLL circuits corresponding to the plurality of receivers, each PLL circuit being configured to generate a clock signal based on a word clock received by the corresponding receiver; and a selector configured to select a clock signal from among a plurality of clock signals generated by the plurality of PLL circuits, and to supply the selected clock signal to the processor, the processor outputting the processed audio data at timing synchronized with the selected clock signal are provided.

Abstract: An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circuit.

Abstract: A broadband digital transmitter is disclosed. The digital transmitter includes a vector decomposer circuit, a phase selector circuit, and a digital power amplifier (DPA). The vector decomposer circuit receives baseband in-phase (I) and quadrature (Q) signals and decomposes the baseband I and Q signals into an offset envelope signal and a non-offset envelope signal. The phase selector circuit receives a plurality of phase offset local oscillator (LO) signals and outputs, responsive to the baseband I and Q signals, offset LO signals and non-offset LO signals. The DPA processes the offset envelope signal, the non-offset envelope signal, the offset LO signals, and the non-offset LO signals to generate an output signal of the digital transmitter.

Abstract: Certain aspects of the present disclosure provide techniques for wireless communications, wherein first number of transit antennas is advertised, but a different number of transmit antennas are actually used for transmission.

Abstract: A data communication system includes a master and a slave. The master transmits a first subject signal including a first subject data to the slave via a transmission line. The slave extracts a clock signal from the first subject signal by performing a clock data recovery process and determines the first subject data based on the first subject signal. The slave transmits a second subject signal including a second subject data to the master during an existing period of the first subject signal without interfering an extracting of the clock signal and a determination of the first subject data. The master receives the second subject signal and cancels a waveform component of the first subject signal from a waveform of the second subject signal, and then determines the second subject data based on the second subject signal.

Abstract: Described are embodiments of methods, apparatuses, and systems for time synchronization of a multi-protocol I/O interconnect of computer apparatus. A method for synchronizing time across the multi-protocol I/O interconnect may include determining a first local time at a first port of a first switch of a switching fabric of a multi-protocol interconnect and a second local time at a second port of a second switch of the switching fabric, calculating an offset value based at least in part on a difference between the first local time and the second local time, and adjusting the second local time by the offset value. Other embodiments may be described and claimed.

Abstract: A signal comprising a first edge and a second edge is received. The first edge of the signal is synchronized with a first clock and the synchronized first edge of the signal is passed to an output. The synchronization results in a delay of the first edge of the signal. The second edge of the signal is passed to the output. The passed second edge of the signal has a delay that is less than the delay of the first edge of the signal by at least one clock cycle of the first clock.

Abstract: A scheme is described that provides for a low latency, glitch free chip interface that does not require a clock. This invention handles input transitions that are skewed and also input transitions that are momentary. A change in an input state initiates a pulse that propagates through the system and samples the new input state after a delay. If there is a difference between the sampled input state and the present input state, then a new pulse is initiated in order to avoid any illegal transitions at the output.

Abstract: Embodiments are disclosed for a device for determining a presentation time for a generated packet. An example device includes a communication interface communicatively connectable to another device and configured to transmit data, a processor, and a storage device that stores instructions executable by the processor to receive a stream packet, extract a timestamp from the stream packet, and add one or more offsets to the extracted timestamp to determine a presentation time. The instructions are further executable to transmit a generated packet, the generated packet including an indication of the determined presentation time.

Abstract: A synchronization module is associated with a network node of a communication network which includes at least one Synchronization Master entity. The synchronization module has knowledge of a plurality of Synchronization Master references. Endpoints of paths of the plurality of Synchronization Master references are obtained. Each of the paths extends between one Synchronization Master entity and the first or the second access network node. The paths are obtained from a synchronization report module based on the obtained endpoints. For each of the Synchronization Master references, a first path and a second path of the obtained paths are selected. A time synchronization inaccuracy value between the first and the second access network node is calculated based on the selected paths. A Synchronization Master reference is selected based on the calculated time synchronization inaccuracy values, and the first and the second access network nodes are notified which Synchronization Master reference was selected.

Abstract: Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (RF) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the RF circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The RF circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.

Abstract: Provided is a wireless signal receiver including: an analog-digital converter (ADC) converting an analog RF signal into a digital baseband signal; and a sub-sampling block dividing and processing the digital baseband signal into a first path signal and a second path signal, and extracting a complex baseband signal by using a relative sample delay difference between the first and second path signals, wherein the first path signal is a signal obtained by adjusting a sample delay and sampling rate of the digital baseband signal, and the second path signal is a signal obtained by filtering without adjusting the sampling rate of the digital baseband signal.

Abstract: A parallel interface is disclosed. The parallel interface of the present disclosure includes an input unit configured to input, in parallel, a plurality of predetermined data signals and a clock signal; an output unit configured to output, in parallel, the predetermined data signals in synchronization with the clock signal; and a plurality of transmission lines disposed between the input unit and the output unit and configured to transmit, in parallel, the predetermined data signals and the clock signal, wherein the transmission lines are configured with a wiring pattern in which the transmission lines have different electrical lengths and an equal electrical capacitance.

Abstract: In some embodiments, a system comprises a clock, a root node, a radio channel network, and first and second child nodes. The clock may be configured to generate a clock signal. The root node may be configured to generate a first frame including a first payload and a first overhead and generate a second frame including a second payload and a second overhead. The first and second overheads may comprise a synchronization value based on the clock signal. The radio channel network may be in communication with the root node for transmitting the first and second frames. Each first and second child nodes may be configured to perform clock recovery including frequency synchronization using the synchronization value and a respective phase-lock loop.

Abstract: A time control apparatus provided in a slave machine and synchronizing time information with time information of a master machine connected over a network includes: calculation units respectively calculating time difference candidates of the slave machine with respect to the master machine and network delays indicative of an average of times necessary for communication of first and second messages over the network based on transmission and reception times of the first messages which are transmitted from the master machine and received using the slave machine and transmission and reception times of the second messages which are transmitted from the slave machine and received using the master machine; a selection unit selecting one of the calculated time difference candidates as a time difference based on the calculated network delays; and an adjustment unit adjusting the time information of the slave machine based on the selected time difference.

Abstract: Aligning FIFO pointers includes resetting, by a write control block coupled to a write side of the FIFO, write pointers to an initial value. Then, iteratively, until one or more bits retrieved from the write side match one or more bits of an alignment bit pattern: providing, by the write side to the read side, the alignment bit pattern; retrieving, by the read side, one or more bits from the write side; providing, by the read side through a read control block, the retrieved one or more bits to the write control block; determining, by the write control block, whether the retrieved one or more bits match one or more bits of the alignment bit pattern; and, if the retrieved one or more bits do not match one or more bits of the alignment bit pattern, suppressing the read pointer from incrementing for a predetermined period of time.

Abstract: Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.

Abstract: An apparatus used to communicate with a plurality of audio/video (A/V) end nodes in an Audio Video Bridging (AVB) network. The apparatus may include a first A/V end node. The first A/V end node may be configured to transmit a clock reference stream including a plurality of timestamps to a plurality of A/V end nodes. The plurality of A/V end nodes may transmit a media stream including a plurality of video samples and a plurality of audio samples to one another. The media stream may be separate from the plurality of timestamps. The plurality of A/V end nodes may be arranged to syntonize or synchronize the plurality of video samples and the plurality of audio samples with one another for playback in response to the plurality of timestamps.

Abstract: Systems and methods of generating an RF stimulus signal with different power levels for IC testing. A DC modulating signal is used to power modulate a radio frequency (RF) carrier signal and thereby generate an RF stimulus signal at varying power levels. The DC modulating signal includes a sequence of DC waveforms at different voltage levels. A DC voltage transition in the modulating signal instantaneously triggers the transition of an output power in the RF stimulus signal. Reference waveforms that can cause a known response pattern in a DUT may be added at the beginning of the modulating signal for data calibration purposes.

Abstract: The present disclosure relates to a method for facilitating synchronization in a wireless communication system. A number sequence of length L is defined. The number sequence is mapped on a first set of discrete Fourier frequency coefficients. A second set of discrete Fourier frequency coefficients is generated by frequency shifting the first set of discrete Fourier frequency coefficients. The second set of discrete Fourier frequency coefficients is transformed into a time domain signal.

Abstract: A signal processing device that generates an output signal from image data by using a clock corresponding to the pixels of the image data, the signal processing device includes: a delayed signal group generating unit that generates a group of delayed signals with a delay element group formed with stages of delay elements; a clock adjusting unit that generates a modulation/synchronization clock from the group of delayed signals by referring to phase data matching the clock with a predetermined phase and frequency modulation coefficient data converting the clock to a predetermined frequency; and a PWM processing unit that generates a PWM signal from the group of delayed signals by referring to the phase data, the frequency modulation coefficient data, the modulation/synchronization clock, and the image data, the PWM signal having a pulse width corresponding to the value of the image data.

Abstract: An optical line terminal transmitter front-end, an optical network terminal receiver front-end and a bit-interleaved passive optical network (BIPON). In one embodiment, the transmitter front-end includes: (1) a bit interleaver configured to group and interleave a plurality of user bit-streams to yield a combined single bit-stream, (2) an encoder coupled to the bit interleaver and configured to encode multiple bits of the single bit-stream into a multi-level code corresponding to a 2m-level multi-level signal and (3) a multi-level modulator coupled to the encoder and configured to modulate the multi-level code into the 2m-level multi-level signal.

Abstract: Disclosed are a method and device for increasing the adaptability of light intensity, which relate to the field of photoelectric communications. The method comprises: providing several stages of load resistors in the device, the device collecting voltage values, calculating the average value of all the collected voltage values when a preset number of voltage values which meet the requirements are collected, setting a voltage according to the average value and judging whether the set voltage meets preset requirements; and if yes, collecting data according to the set voltage; otherwise switching a load resistor according to a preset rule, wherein the load voltage may affect the voltage collection. The present invention has the beneficial effects of: improving the adaptability of a screen to light intensity during optical signal collection, and at the same time being able to reduce the error rate.