Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

Abstract: A data transmission system in a communication network comprising a data modulator comprises: a first part at the level of the collection point part comprising: an NCR module taking account of an external absolute time reference to reconstitute a network clock, a transmitter module receiving the value of a time reference to be inserted into the data packet to be transmitted and transmitting to the NCR module an information item on an instant of synchronization for the receiver, a second part at the level of the radiofrequency part of a gateway comprising; a receiver module, a module for reconstructing a clock locally, a module for inserting a time reference into a data packet received by the receiver before transmission of the data via the satellite, the first part and the second part exchange encapsulated data.

Abstract: Systems and methods for power conservation in a SOUNDWIRE audio bus provide a pulse density modulated (PDM) audio stream at an audio source to an encoder. The encoder has a plurality of encoding states corresponding to bit patterns. The encoder compares bits of the audio stream to available bit patterns and selects an encoding state. The audio source sends the encoding state to an audio sink and then sends data to the audio sink based on encoding using the selected encoding state. The data is sent over a non-return to zero inverted (NRZI) audio bus. As the audio stream changes bit patterns, the encoder may select different more efficient encoding states and provide updates to the audio sink of changes in the encoding state.

Abstract: Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.

Abstract: The systems and methods for a twisted pair transceiver with correlation detection includes a transceiver system operating on a cable. The transceiver system includes a receiver to obtain one or more data samples related to one or more encoded data symbols. The transceiver system further includes a first correlation filter to generate a first correlation output based on the one or more data samples, and a second correlation filter to generate a second correlation output based on the one or more data samples. The transceiver system further includes a detector. The detector compares the first correlation output with the second correlation output, generates an output data bit based on a comparison result, and sends the output data bit for data decoding.

Abstract: Digital pre-distortion may be provided. First, a characterization for input matching circuitry may be determined. Next, a characterization for non-linearity of an amplifier connected to the input matching circuitry may be determined. Then, a distortion correcting signal may be generated from an input signal based on the determined characterization for the input matching circuitry and the determined characterization for the non-linearity of the amplifier. The generated distortion correcting signal may then be provided to the input matching circuitry.

Abstract: A system controller, preferably implemented as a cloud service, enables the synchronization of display devices located at geographically remote locations relative to one another. A display and control devices are provided at each of a plurality of sites, with one or both of the devices being capable displaying the transmitted show. The control device enables the system controller to determine local relative delays in the show and to control the temporal reproduction of said transmitted show by said display device so as to achieve a substantially synchronized reproduction of the show at each of the sites.

Abstract: A content delivery apparatus includes an external input portion, a content reception portion and a delivery portion. To the external input portion, first content having at least a fundamental component is inputted. The content reception portion receives second content having a fundamental component and an extended component. When delivering the first content, the delivery portion delivers the fundamental component of the first content to a client apparatus more than once.

Abstract: A preamble detector for a Bluetooth Long Range includes a receiver for forming baseband samples from Bluetooth packets and a preamble detect controller for enabling and disabling power to the receiver. Where the preamble duration is Tcyc, the preamble detector turns on for a preamble detect time T1 and turns off for a duration T2, where T2=Tcyc?2*T1. A series of hierarchical decisions is made on sequentially increasing intervals of time based on an accumulated correlation result of correlating the baseband samples against a SYNC sequence to power the receiver back down before the end of the T1 period when the accumulated correlation result is below a threshold and continues to a subsequent correlation interval when the accumulated correlation result is above a threshold, where the threshold is established to have at least a 20% false alarm rate for preamble detection.

Abstract: This disclosure relates to techniques for synchronization signals. The synchronization signal comprise a primary synchronization signal (PSS) generated based on a PSS sequence and a secondary synchronization signal (SSS) generated based on an SSS sequence. The SSS sequence may be generated based on a first sequence corresponding to a first cyclic shift and a second sequence corresponding to a second cyclic shift. The first cyclic shift and the second cyclic shift are associated with Cell ID. The Cell ID can be determined from the first cyclic shift and the second cyclic shift.

Abstract: Low power consumption networking method for 802.15.4e wireless device “WD” taking 4-20 mA loop power, including: a “WD” taking loop power; constructing a WD oriented to ultra-low power consumption; the WD implementing unidirectional time synchronization based on preceding wireless network; on basis of preceding time synchronization, completing neighbor discovery; the WD interacting with the wireless network; and pausing a preceding procedure according to a power monitoring result of an energy storage monitoring module.

Abstract: A rate determination apparatus 1 includes a reception unit 2 configured to receive a transmission frame modulated by an FSK modulation scheme, a symbol rate detection unit 3 configured to detect a symbol rate based on a period of a preamble portion in the received transmission frame, a multilevel symbol detection unit 4 configured to detect a multilevel-modulated multilevel symbol based on a frequency deviation in the received transmission frame, and a bit rate determination unit 5 configured to determine a bit rate based on the detected symbol rate and the detected multilevel symbol. Then, the bit rate can be determined during communication.

Abstract: A scan output flip-flop is provided. The scan output flip-flop outputs a scan-out signal at a first output terminal and includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal of the selection circuit to serve as an input signal. The control circuit is coupled to the output terminal of the selection circuit and controlled by a first clock signal to generate a first control signal and a second control signal according to the input signal. The second control signal is the inverse of the first control signal. The scan-out stage circuit is controlled by the first control signal and the second control signal to generate the scan-out signal.

Abstract: Embodiments disclosed herein provide systems and methods for acoustically transferring information between systems. In a particular embodiment, a method provides identifying information for acoustic transfer and determining an amount of time corresponding to the information. The method further provides acoustically transmitting a signal at a first time and, upon the amount of time elapsing since the first time, acoustically transmitting the signal at a second time.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal.

Abstract: An apparatus and method may detect and reduce noise on data busses by adjusting the phase of the input/output (I/O) signals in a controlled, predictable manner. The control may allow a maximum data rate to be achieved. In one embodiment, an algorithm used to determine phase change data may be handled by a feedback loop and may be dynamically adjusted. The system may detect noise on rails and critical signals for logging in call home data. The system may maintain a database of settings as a function of a workload. The system may be used in the field as the workload changes to determine that a signal has reached a first threshold. In response to determining that the signal has reached the first threshold, an alert is initiated. A system may determine that the signal has reached a second threshold. In response to determining that the signal has reached the second threshold, the signal may be coupled to logic circuitry.

Abstract: A receiver for data communication may include: an input buffer suitable for generating plural comparison signals by differentially comparing plural input signals; a de-serializer suitable for generating plural groups of de-serialized signals by de-serializing the plural comparison signals at a preset de-serialization ratio; a D flip-flop suitable for generating plural delayed signals by delaying last de-serialized signals of the respective plural groups of de-serialized signals by a preset time; a symbol decoder suitable for comparing current and previous states of the plural comparison signals and for generating plural symbol signals based on a preset state diagram defining a correspondence relationship between the plural symbol signals and changes between current and previous states of the plural comparison signals.

Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx 164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI Interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.

Abstract: A phase-locked loop according to the present disclosure includes a reference-phase generation circuit that sequentially generates a reference phase value, and an oscillating circuit that generates a first clock on a basis of a difference between the reference phase value and a feedback phase value. The phase-locked loop further includes a signal generation circuit that generates, on a basis of the first clock, a plurality of second clocks varying in phase, and generates a third clock by switching the plurality of second clocks a plurality of times in each of cycle periods each corresponding to one cycle of the reference clock. The phase-locked loop further includes a phase detection circuit that determines a phase value of the third clock and outputs the determined phase value as the feedback phase value.

Abstract: Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed.

Abstract: A beamforming device is provided. The beamforming device comprises: a beam deriving unit for deriving, among multiple reception beams, a first reception beam receiving, from a terminal, the first largest reception signal and a second reception beam receiving, from the terminal, the second largest reception signal; and a control unit for estimating the direction of the terminal on the basis of a ratio value between the size of the reception signal received through the first reception beam and the size of the reception signal received through the second reception beam.

Abstract: Embodiments of the disclosure disclose a synchronization method and apparatus on the basis of a field broadband bus architecture of an industrial Internet, where the bus architecture includes a bus controller, at least one bus terminal, and a two-wire bus, and the bus controller and the bus terminal are connected over the two-wire bus to constitute a bus system, the bus system communicating using OFDM technology; and in the method, all the bus terminals refer to the bus controller, and when receiving a signal, and transmitting a signal, they adjust a clock for a received signal, and a signal to be transmitted, adaptively according to the downlink pilot signal so as to synchronize their clocks and symbols with the bus controller, and adjust a transmission time for the signal to be transmitted so that all the devices in the bus system are synchronized.

Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

Abstract: The present invention relates to a method of transmitting and a method of receiving signals, and corresponding apparatus. One aspect of the present invention relates to a method of obtaining a field for indicating a time de-interleaving depth from a layer 1 (L1) header of preamble symbols.

Abstract: Disclosed is a technology for detecting an erroneous operation of a task scheduler of a battery management system. An apparatus for detecting an erroneous operation according to an exemplary embodiment includes: a first scheduler module configured to control a first task to be executed for every first period; a second scheduler module configured to control a second task to be executed for every second period; a task counting unit configured to increase the first counting value for the first scheduler module in accordance with the first period whenever the first task is executed, and increase the second counting value for the second scheduler module in accordance with the second period whenever the second task is executed; and an erroneous operation detecting unit configured to detect erroneous operations of the first scheduler module and the second scheduler module based on the first counting value and the second counting value.

Abstract: A system (1) for transferring a data signal (sig_fast) from a first clock domain (4) to a second clock domain (8). The first clock domain (4) has a first clock (ck_fast) with a frequency greater than the frequency of a second clock (ck_slow) in the second clock domain (8). The system (1) also has a signal input (10) for receiving an input signal (sig_fast) from the first clock domain (4), means (16, 18) for checking whether the second clock (ck_slow) is in a part of its cycle away from a forthcoming transition, and means (22) for transferring the input signal (sig_fast) to the second clock domain (8) if the checking means (16, 18) determines that the second clock (ck_slow) is in part of its cycle away from a forthcoming transition. The checking means (16, 18) are clocked by the first clock (ck_fast).

Abstract: A circuit arrangement for clock and data recovery comprises a control unit, a phase-locked loop circuit and a sampling unit. The control unit is configured to derive a first reference signal and a second reference signal from an input signal. Furthermore, the control unit is configured to derive a common reference signal from one of the first reference signal and the second reference signal, selected depending on a mode of operation of the circuit arrangement. The phase-locked loop circuit is configured to generate an oscillator signal based on the common reference signal. The sampling unit is configured to extract a recovered data signal from the input signal.

Abstract: Uplink carrier selection is performed for reduced bandwidth machine type communication devices by reserving a portion of a wideband carrier for machine type communication traffic to provide a plurality of narrowband uplink carriers in the wideband carrier, and by selecting a narrowband uplink carrier of the plurality of narrowband uplink carriers for use by a machine type communication device.

Abstract: A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.

Abstract: A method and system to enable interoperability between Internet enabled devices and online applications without traditionally agreeable on device standard formats between the manufacturer and applications ahead time. The application is able to connect, control, and actuate newly added devices at runtime.

Abstract: A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.

Abstract: Provided is a high-speed serial data receiving apparatus including: a clock converter configured to convert a serial clock into a parallel clock; a data converter configured to convert a serial data packet into N parallel data packets and outputting the N parallel data packets; a synchronization signal detector configured to receive the N parallel data packets and the parallel clock, and detecting a data start synchronization of the N parallel data packets output from the data converter by comparing the parallel data packets with a synchronization code of N bits set in advance; and an error compensation unit configured to detect and compensate for a skew between parallel clock and data.

Abstract: A method and device for sending a synchronization signal and a method and device for synchronization between base stations, include: determining, by a synchronization source base station according to a synchronization level of the synchronization source base station, a resource for sending an NLRS for clock synchronization between base stations, and according to the determined resource. In this way, one NLRS for clock synchronization between base stations is configured on each synchronization source base station, and the NLRS is sent on a resource determined according to a synchronization level, so that a synchronization base station that acquires the NLRS can determine the synchronization level of the synchronization source base station according to a resource for sending the NLRS.

Abstract: Disclosed is a transmitting apparatus that includes an uplink transmitting unit that generates at least two carrier transmission signals carrier and generates transmission control data corresponding to the carrier transmission signals, a Radio Frequency Front End (RFFE) that transmits the at least two carrier transmission signals, and a transmission controller including a storage unit and decoders. The transmission controller activates a decoder corresponding to transmission control data output from the uplink transmitting unit, and the activated decoder accesses information of the storage unit to control wireless transmission of the RFFE.

Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.

Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.

Abstract: The systems and methods for a twisted pair transceiver with correlation detection includes a transceiver system operating on a cable. The transceiver system includes a receiver to obtain one or more data samples related to one or more encoded data symbols. The transceiver system further includes a first correlation filter to generate a first correlation output based on the one or more data samples, and a second correlation filter to generate a second correlation output based on the one or more data samples. The transceiver system further includes a detector. The detector compares the first correlation output with the second correlation output, generates an output data bit based on a comparison result, and sends the output data bit for data decoding.

Abstract: An optical transmitter transmits an orthogonal frequency division multiplexing symbol in which only one-half of available subcarriers are modulated with data and the remaining subcarriers are suppressed by not modulating with data. The transmission is of duration equal to half the symbol period of the OFDM symbol, resulting in a half-cycle transmission. An optical receiver receives the half-cycle transmission OFDM symbol, regenerates the full time domain representation and recovers data modulated on the one-half of available subcarriers. The modulated subcarriers and the suppressed subcarriers alternate in the frequency domain.

Abstract: A master-slave flip-flop includes a master latch, a slave latch, a first logic gate and a signal transition detector. The first logic gate is receiving a reference clock and a first control clock, and outputting a first trigger signal to control one of the master latch and the slave latch, which are connected with a logic circuit, to switch to an opaque state or a transparent state, wherein the other one of the master latch and the slave latch is switched to an opaque state or a transparent state according to the reference clock. The above-mentioned master-slave flip-flop can correct sampling when a timing error occurs.

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

Abstract: A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

Abstract: The present disclosure discloses a proximity detection method and apparatus for a near field communication, which belongs to the field of communications technologies. The method includes: sending, by a first electronic device, a signal of a detection frame; determining whether a second electronic device capable of performing the near field communication exists according to a received response frame, wherein the detection frame includes at least two symbols modulated with different frequencies. In embodiments of the present disclosure, a signal of a detection frame which includes multiple symbols modulated with different frequencies is sent, so that a peer-to-peer electronic device existing within a communicatable range can be detected for communication in a case of that these modulation frequencies suffer an interference.

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.

Abstract: Asynchronous bridge circuitry provides data communication between source circuitry 4 in a source clock domain and destination circuitry 12 in a destinations clock domain. The asynchronous bridge circuitry includes first-in-first-out buffer 20, transmission path circuitry 14, which has an input end coupled to the source circuitry and an output end coupled to the first-in-first-out buffer. The transmission path circuitry has a transmission delay corresponding to a plurality of source clock cycles. Write pointer circuitry 22 located within the source clock domain at the output end 18 of the transmission path circuitry so as to generate a write pointer for the first-in-first-out buffer. Transmission control circuitry 26 located within the source clock domain at the input end 16 of the transmission path circuitry is configured to generate a transmission control signal which controls whether or not the source circuitry is permitted to send data.

Abstract: In an example implementation, an alignment detection circuit includes a buffer, a candidate selection circuit, and a correlator circuit. The buffer is configured to receive a data stream from a data lane, the data stream including alignment markers delineating data frames, each of the alignment markers having a predefined bit pattern. The candidate selection circuit is configured to identify candidate data blocks in successive data blocks of the data stream provided by the buffer, each of the candidate blocks having a measure of symmetry satisfying a threshold metric indicative of the predefined bit pattern. The correlator circuit is configured to search for at least one of the alignment markers in each of the candidate blocks and adjust alignment of the data stream in the buffer in response to locating the at least one alignment marker.

Abstract: Embodiments of the disclosure relate to systems and methods for determining asymmetric downlink and uplink propagation delays in a wireless distribution system (WDS) for more accurately determining propagation delay. In this regard, a WDS is configured to determine both the separate downlink and uplink propagation delays between a central unit and a plurality of remote units. It is not presumed that the downlink propagation delay and the uplink propagation delay in the WDS are symmetric to provide a more accurate determination of propagation delay. Therefore, it is possible to determine the downlink and uplink propagation delays with improved accuracy, thus enabling more precise location identification in the WDS.

Abstract: This application teaches a method for indicating voxel quality comprising graphically and/or mathematically. Such a method may include measuring a distance from the three-dimensional scanning device to an area of a subject corresponding to an image voxel. It may also include measuring an angle between a line of sight from the three-dimensional imaging device and an orthogonal ray of the same area of the subject corresponding to the same voxel. The process may further include comparing the measured distance and angle to known acceptable operating ranges of the scanner, and plotting a quality point corresponding to the foregoing metrics on a set of axes.

Abstract: A method of compensating for a round-trip transmission delay in an audio system comprising: a portable communications device; an audio accessory; and a cable, suitable for connecting the portable communications device and the audio accessory, having at least one wire and being detachable from at least one of the portable communications device and the audio accessory. At first times, a first synchronization data pattern is transmitted on the at least one wire from said device to said accessory, wherein said first synchronization data pattern comprises first signal level transitions on the at least one wire, synchronized to a master transmission clock. At second times, a second synchronization data pattern is transmitted on the at least one wire from said accessory to said device, wherein said second synchronization data pattern comprises second signal level transitions at timings that are set based on a delay value stored in said accessory.

Abstract: Methods and systems for obtaining improved joint channel estimates for a multi-user, frequency-multiplexed data transmission such as SC-FDMA or OFDM begins by estimating separate contributions of users (and/or other signal sources) to the received signal based on joint frequency domain channel estimates. A reduced data set is obtained by subtracting contributions of one or more users from the received data, leaving only the estimated contributions of the remaining users, with noise and residual estimation error signal. Time domain joint channel estimation is then performed on the reduced data set, which is feasible because the number of users has been reduced. In exemplary embodiments, the reduced data set includes only one estimated user contribution. This process is repeated to obtain time domain estimates for all of the users. The method can be repeated by using the TD channel estimates to re-estimate the user contributions and calculate revised TD channel estimates.