Abstract: A thin film transistor display panel includes a gate electrode on a substrate; a gate insulating layer on the substrate and the gate electrode; a planarization layer on the gate insulating layer and at opposing sides of the gate electrode, where the planarization layer exposes the gate insulating layer; a semiconductor layer on the gate insulating layer; and a source electrode and a drain electrode on the semiconductor layer and spaced apart from each other.

Abstract: A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: Apparatus for atomic layer deposition on a surface of a sheeted substrate, comprising: an injector head comprising a deposition space provided with a precursor supply and a precursor drain; said supply and drain arranged for providing a precursor gas flow from the precursor supply via the deposition space to the precursor drain; the deposition space in use being bounded by the injector head and the substrate surface; a gas bearing comprising a bearing gas injector, arranged for injecting a bearing gas between the injector head and the substrate surface, the bearing gas thus forming a gas-bearing; a conveying system providing relative movement of the substrate and the injector head along a plane of the substrate to form a conveying plane along which the substrate is conveyed.

Abstract: An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.

Abstract: Source wires having a semiconductor film thereunder are formed wide within a range that does not overlap pixel electrodes formed later. Thereafter, a resist pattern for use in patterning the pixel electrodes is formed so as to overlap edge portions of the source wires, and etching using the resist pattern as a mask is performed, whereby the pixel electrodes are formed, and in addition, the edge portions of the source wires are removed, whereby a structure in which the semiconductor film has a portion projecting beyond the source wires on both sides is formed.

Abstract: A display device is disclosed. In one aspect, the display device includes a first substrate including a display area and a non-display area surrounding the display area and a display unit formed over the first substrate in the display area and configured to display an image. The display device also includes a plurality of first reinforcing members formed over the first substrate in the non-display area, wherein the first reinforcing members are spaced apart from each other. The display device further includes a second substrate formed over the first substrate with the display unit interposed therebetween, and a sealant formed in the non-display area and substantially sealing the first and second substrates, wherein the sealant is interposed between the display area and the plurality of first reinforcing members.

Abstract: The present invention provides a thin wiring pattern such as wiring formed by discharging a droplet. In the present invention, a porous (including microporous) substance is formed as a base film in forming pattern by using a droplet discharge method (also referred to as an ink-jetting method). One feature of a wiring substrate according to the present invention provides a porous film and a conductive layer thereon. One feature of a semiconductor device of the present invention provides a thin film transistor in which a gate electrode is formed by the conductive layer having the above-described structure.

Abstract: A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

Abstract: According to one embodiment, a display device includes a semiconductor including a first channel region, a second channel region, a source region, a drain region, a first region located between the source region and the first channel region, a second region formed between the first channel region and the second channel region, and a third region located between the drain region and the second channel region, wherein the second region has a length of 5 ?m or more, which is greater than a length of each of the first region and the third region.

Abstract: A method for forming the crystalline thin film according to an implementation of the present invention includes: preparing a substrate; forming a non-crystalline thin film above the substrate; and crystallizing at least a predetermined region in the non-crystalline thin film, by irradiating the non-crystalline thin film with a laser beam having a predetermined wavelength and scanned relative to the substrate. In the preparing, a direction of a largest residual stress on the substrate is identified. In the crystallizing, the laser beam is scanned in the identified direction of the largest residual stress.

Abstract: A bitcell may include an insulating region, a first doping proximate to the insulating region, and a second doping surrounding the first doping. The second doping can be characterized by a higher gate voltage breakdown than the first doping. Also, the bitcell may include a gate terminal, and the bitcell may be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating region between the gate terminal and the first doping.

Abstract: A method for forming a U-shaped semiconductor device includes forming trenches in a crystalline layer and epitaxially growing a U-shaped semiconductor material along sidewalls and bottoms of the trenches. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. The U-shaped semiconductor material is supported by backfilling underneath the U-shaped semiconductor material with a dielectric material. A semiconductor device is formed with the U-shaped semiconductor material.

Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.

Abstract: A thin-film transistor (TFT) array substrate comprises: a substrate; an active layer and a capacitor first electrode formed on the substrate; a gate insulating film formed on the substrate, the active layer and the capacitor first electrode; a gate electrode formed on the gate insulating film corresponding to the active layer and a capacitor second electrode formed on the gate insulating film corresponding to the capacitor first electrode; an interlayer insulating film formed on the gate insulating film, the gate electrode, and the capacitor second electrode; and a pixel electrode, a source electrode, and a drain electrode formed on the interlayer insulating film; wherein at least one of the source electrode and the drain electrode is formed on the pixel electrode. A method of fabricating the TFT array substrate is also disclosed.

Abstract: Methods of making a photovoltaic device with an organic liquid precursor having electron donor, electron acceptor, and liquid carrier are provided. The liquid precursor is applied to an electrode. A gas permeable layer/stamp contacts and applies pressure to the organic liquid precursor removing liquid carrier to form a solid active material with uniform interpenetrating network domains of electron donor/acceptor materials. A two-step process is also contemplated. A liquid precursor with either electron donor or acceptor is applied to an electrode, contacted under pressure with a first stamp having a nanoscale pattern, thus forming a solid with a patterned surface. Then, a second liquid precursor with the other of the electron donor or acceptor is applied to the patterned surface, contacted with a second stamp under pressure to form the active material. A transparent conducting electrode with material nanograting can be formed. The methods also include continuous processing, like roll-to-roll manufacturing.

Abstract: An embodiment of the present invention provides a fabricating method of a thin film transistor, a fabricating method of an array substrate, and a display device. The fabricating method of a thin film transistor comprises: forming a gate electrode on a substrate; and forming a gate insulating layer, a semiconductor layer, source and drain electrodes and a channel region on the substrate, wherein, the semiconductor layer is formed of a metal oxide, and two etching steps are used to form the channel region, and in a first etching step, a part of a source-drain metal layer above the semiconductor layer corresponding to the channel region is removed by using a dry etching, and in a second etching step, a remaining part of the source-drain metal layer above the semiconductor layer corresponding to the channel region is removed by using a wet etching, thereby forming the channel region.

Abstract: To provide a highly reliable semiconductor device by giving stable electrical characteristics to a transistor including an oxide semiconductor film. A gate electrode layer is formed over a substrate, a gate insulating film is formed over the gate electrode layer, an oxide semiconductor film is formed over the gate insulating film, a conductive film is formed over the oxide semiconductor film, so that a region in vicinity of an interface with the oxide semiconductor film in contact with the conductive film is made amorphous, heat treatment is performed, the conductive film is then processed to form a source electrode layer and a drain electrode layer, and a part of the amorphous region in the oxide semiconductor film which is exposed by formation of the source electrode layer and the drain electrode layer is removed.

Abstract: A organic light emitting display device includes a thin film transistor (TFT) having a gate electrode, a source electrode and a drain electrode which are insulated from the gate electrode, and a semiconductor layer which is insulated from the gate electrode and which contacts each of the source electrode and the drain electrode; and a pixel electrode electrically connected to one of the source electrode and the drain electrode. The gate electrode is made up of a first conductive layer and a second conductive layer on the first conductive layer, and the pixel electrode is formed of the same material as the first conductive layer of the gate electrode on a same layer as the first conductive layer of the gate electrode.

Abstract: Provide are an electrode sensor and a method of fabricating the same. the method may include providing a substrate with a first electrode, forming a resist layer on the substrate to cover the first electrode, patterning the resist layer to expose a portion of the first electrode, forming an insulating layer on the substrate, removing the insulating layer on the resist layer and the resist layer to form a well in the insulating layer, and forming a second electrode in the well to be electrically connected to the first electrode. According to the method, it is possible to prevent the first electrode from being damaged. In addition, the second electrode may be configured have an increased surface area, and thus, the electrode can have low impedance.

Abstract: A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.

Abstract: A thin film transistor is provided. The thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, a transition layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The transition layer is sandwiched between the insulating layer and the semiconductor layer. The transition layer is a silicon-oxide cross-linked polymer layer including a plurality of Si atoms. The plurality of Si atoms is bonded with atoms of the insulating layer and atoms of the semiconductor layer.

Abstract: A thin film transistor includes a post on a substrate. The post has a height dimension extending away from the substrate to a top portion of the post which extends a distance beyond a bottom portion of the post in a direction parallel to the substrate to define a reentrant profile. A conformal conductive gate layer is located on an edge of the post in the reentrant profile and not over the top portion of the post, and includes a portion that extends along the substrate. A conformal insulating layer is on the gate layer in the reentrant profile. A conformal semiconductor layer is on the insulating layer in the reentrant profile. First and second electrodes are located in contact with first and second portions of the semiconductor layer over the top portion of the post and not over the top portion of the post, respectively.

Abstract: The present invention provides an array substrate comprising: a substrate, having a thin film transistor (TFT) formed thereupon, the TFT having a gate electrode, a source electrode and a drain electrode; a first metal layer, formed on the substrate, and comprising a gate line and the gate electrode of the TFT; a first insulating layer, covering the first metal layer and the substrate; a semiconductor layer, an ohmic contact layer, and a second metal layer, which are sequentially formed on the first insulating layer; a second insulating layer, covering the semiconductor layer, the ohmic contact layer, and the second metal layer; a pixel electrode, provided on the second insulating layer and is connected to the drain electrode. The second metal layer further comprises an etch-blocking pattern in the peripheral area of the pixel electrode within the overlapping region between the pixel electrode and the first metal layer.

Abstract: A method of forming a gate layer of a thin film transistor includes providing a substrate including a gate structure having a reentrant profile. A conformal conductive inorganic thin film is deposited over the gate structure and in the reentrant profile. A photoresist is deposited on the conformal conductive inorganic thin film over the gate structure and filling the reentrant profile. The photoresist is exposed from a side of the photoresist opposite the substrate allowing the photoresist in the reentrant profile to remain unexposed. The conformal conductive inorganic thin film is etched in areas not protected by the photoresist to form a patterned conductive gate layer located in the reentrant profile of the gate structure.

Abstract: A semiconductor device including a first connecting member including a first electrode; a second connecting member including a second electrode; and an anisotropic conductive film between the first connecting member and the second connecting member, the anisotropic conductive film bonding the first electrode to the second electrode, wherein the anisotropic conductive film exhibits linear indentations in an inter-terminal space of the second connecting member after pre-compression and primary compression of the anisotropic conductive film onto the first and second connecting members.

Abstract: Methods for fabrication of fin devices for an integrated circuit are provided. Fin structures are formed in a semiconductor material, where the fin structures include sidewalls and tops. Dopant implantation is performed at a tilt angle to form a doped region along the sidewalls and the tops of the fin structures, where the semiconductor material is maintained at an elevated temperature during the dopant implantation. The elevated temperature prevents amorphization of the fin structures during the dopant implantation. A field effect transistor is formed from the fin structures. The field effect transistor has a threshold voltage that is based on the dopant implantation.

Abstract: A method of processing quantum dots is disclosed. The method comprises applying energy to excite the quantum dots to emit light and placing the quantum dots under vacuum after excitation of the quantum dots. Also disclosed is a method of processing a component including quantum dots comprising applying energy to the component including quantum dots to excite the quantum dots to emit light; and placing the component including quantum dots under vacuum after excitation. A method for processing a device is further disclosed, the method comprising applying energy to the device to excite the quantum dots to emit light; and placing the device under vacuum after excitation of the quantum dots. A method for preparing a device is also disclosed. Quantum dots, component, and devices of the methods are also disclosed.

Abstract: A microelectromechanical systems (MEMS) device (58) includes a structural layer (78) having a top surface (86). The top surface (86) includes surface regions (92, 94) that are generally parallel to one another but are offset relative to one another such that a stress concentration location (90) is formed between them. Laterally propagating shallow surface cracks (44) have a tendency to form in the structural layer (78), especially near the joints (102) between the surface regions (92, 94). A method (50) entails fabricating (52) the MEMS device (58) and forming (54) trenches (56) in the top surface (86) of the structural layer (78) of the MEMS device (58). The trenches (56) act as a crack inhibition feature to largely prevent the formation of deep cracks in structural layer (78) which might otherwise result in MEMS device failure.

Abstract: This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and configured to receive first, second, and third control signals, respectively. Dielectric layers insulate the gates from the semiconducting layer and from one another. In a first mode, the first, second, and third gates are configured such that charge is stored in a potential well in a region of the semiconducting layer adjacent the second gate. In a second mode, the first, second and third gate electrodes are configured such that the stored charge is transferred through the region of the semiconducting layer adjacent the third gate electrode and through the source to a load.

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract: A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

Abstract: Oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film are reduced and electric characteristics of a transistor including the oxide semiconductor film are improved. Further, a highly reliable semiconductor device including the transistor including the oxide semiconductor film is provided. In the transistor including the oxide semiconductor film, at least one insulating film in contact with the oxide semiconductor film contains excess oxygen. By the excess oxygen included in the insulating film in contact with the oxide semiconductor film, oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced. Note that the insulating film including the excess oxygen has a profile of the excess oxygen concentration having two or more local maximum values in the depth direction.

Abstract: Embodiments of the invention provide a semiconductor structure including a finFET having an epitaxial semiconductor region in direct physical contact with a plurality of fins, wherein the epitaxial semiconductor region traverses an insulator layer and is in direct physical contact with the semiconductor substrate. The gate of the finFET is disposed over an insulator layer, such as a buried oxide layer. Methods of forming the semiconductor structure are also included.

Abstract: A method of forming a thin film transistor array panel includes: forming a first insulating layer on a substrate; forming an amorphous carbon layer on the first insulating layer; forming a second insulating layer on the amorphous carbon layer; forming an opening in the amorphous carbon layer by patterning the second insulating layer and the amorphous carbon layer; and forming a trench in the first insulating layer by etching the first insulating layer, the etching the first insulating layer using the amorphous carbon layer including the opening as a mask.

Abstract: A thin film transistor display panel includes a gate electrode on a substrate; a gate insulating layer on the substrate and the gate electrode; a planarization layer on the gate insulating layer and at opposing sides of the gate electrode, where the planarization layer exposes the gate insulating layer; a semiconductor layer on the gate insulating layer; and a source electrode and a drain electrode on the semiconductor layer and spaced apart from each other.

Abstract: A thin film transistor array panel includes: an substrate; a gate line and a gate pad portion disposed on the substrate; a gate insulating layer disposed on the gate line and the gate pad portion; a data line and a data pad portion disposed on the gate insulating layer; a gate assistance pad portion disposed at a position corresponding to the gate pad portion; a first insulating layer disposed on the data line and removed at the gate pad portion and the data pad portion; a first field generating electrode disposed on the first insulating layer; a second insulating layer disposed on the first field generating electrode and removed at the gate pad portion and the data pad portion; and a second field generating electrode disposed on the second insulating layer. The assistance gate pad portion and the gate insulating layer include a contact hole exposing the gate pad portion.

Abstract: A semiconductor device includes first memory strings coupled between a first common source line formed on a substrate and bit lines formed over the first common source line, and second memory strings coupled between the bit lines and a second common source line formed over the bit lines, wherein each of the bit lines includes a stacked structure of a conductive layer and a silicon layer formed on the conductive layer.

Abstract: An organic light-emitting display apparatus and a fabrication method thereof are disclosed. The organic light-emitting display apparatus may include, for example, a flexible substrate, a plurality of barrier layers formed on the flexible substrate, a thin film transistor (TFT) formed on the barrier layers, the TFT including a semiconductor active layer, and at least one thermal emission layer formed between the barrier layers, an organic light-emitting device (OLED) electrically connected to the TFT, formed on the barrier layers, and an encapsulation portion encapsulating the OLED.

Abstract: When forming spacer structures enclosing a gate electrode structure of a transistor, a common problem is given by the thickness variation of the spacer structure obtained as a result of a first deposition process performed in a first chamber and a second, subsequent process performed in a second chamber. The present disclosure provides a method for forming spacers of a well-defined thickness. The method relies on a single deposition step performed by means of an atomic layer deposition. The deposition is performed in two stages performed at different temperatures.

Abstract: A Group III-nitride-based enhancement mode transistor includes a heterojunction fin structure. Side faces and a top face of the heterojunction fin structure are covered by a p-type Group III-nitride layer.

Abstract: A thin film transistor (TFT) that includes a control electrode, a semiconductor pattern, a first input electrode, a second input electrode, and an output electrode is disclosed. in one aspect, the semiconductor pattern includes a first input area, a second input area, a channel area, and an output area. The channel area is formed between the first input area and the output area and overlapped with the control electrode to be insulated from the control electrode. The second input area is formed between the first input area and the channel area and doped with a doping concentration different from a doping concentration of the first input areas. The second input electrode makes contact with the second input area and receives a control voltage to control a threshold voltage.

Abstract: The present invention has an object to perform a peeling treatment in a short time. Peeling is performed while a peeling layer is exposed to an atmosphere of an etching gas. Alternatively, peeling is performed while an etching gas for a peeling layer is blown to the peeling layer in an atmosphere of an etching gas. Specifically, an etching gas is blown to a part to be peeled while a layer to be peeled is torn off from a substrate. Alternatively, peeling is performed in an etchant for a peeling layer while supplying an etchant to the peeling layer.

Abstract: An organic light-emitting display apparatus and a method of manufacturing the same. The organic light-emitting display apparatus includes an organic light-emitting device in which a pixel electrode, an intermediate layer that includes an emissive layer, and a cathode electrode are sequentially stacked. The cathode contact unit includes a cathode bus line that is formed on the same layer as the pixel electrode and contacts the cathode electrode, a first auxiliary electrode that is formed on the cathode bus line along an edge area of the cathode bus line, and a second auxiliary electrode that contacts the first auxiliary electrode.

Abstract: A method of creating a semiconductor device is disclosed. An end of a carbon nanotube is unzipped to provide a substantially flat surface. A contact of the semiconductor device is formed. The substantially flat surface of the carbon nanotube is coupled to the contact to create the semiconductor device. An energy gap in the unzipped end of the carbon nanotube may be less than an energy gap in a region of the carbon nanotube outside of the unzipped end region.

Abstract: A thin-film semiconductor device having two thin-film transistors, wherein each of the two thin-film transistors includes: a gate electrode; a gate insulating film; a semiconductor layer; a channel protection layer; an intrinsic semiconductor layer; a contact layer in contact with a portion of sides of the channel region; a source electrode on the contact layer; and a drain electrode opposite to the source electrode on the contact layer, wherein the contact layer of one of the two thin-film transistors has a conductivity type different from a conductivity type of the contact layer of the other of the two thin-film transistors.

Abstract: A thin film transistor includes a semiconductor layer disposed on a base substrate and including an oxide semiconductor material, a source electrode and a drain electrode, which respectively extend from opposing ends of the semiconductor layer, a plurality of low carrier concentration areas respectively disposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer, a gate insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating layer.

Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.

Abstract: Thin film transistors having a high current drive capability and a suitable threshold voltage are provided. The thin film transistor includes a gate electrode, an insulating layer formed on the gate electrode, a semiconductor layer formed on the insulating layer, and source/drain electrodes formed on the semiconductor layer. The semiconductor layer includes a plurality of regions separated from each other in a longitudinal direction of the source/drain electrodes.

Abstract: An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.