Abstract: A method of etching capable of rapidly and flatly performing wet etching on a Si substrate using fluonitric acid represented by HF(a)HNO3(b)H2O(c) (where the unit of a, b and c is wt % and a+b+c=100). The etching rate of an SiO2 layer with the highly concentrated fluonitric acid is significantly lowered by the appropriate selection of its composition as compared with the etching rate of the Si substrate, and etch the Si substrate until the SiO2 layer is exposed. In this way, it is possible to rapidly etch the Si substrate and significantly enhance the flatness of the etched surface.

Abstract: A semiconductor light emitting element in which changes in light distribution characteristics due to inclination angle of side surfaces are suppressed. The semiconductor light emitting element includes a semiconductor structure having a light extracting surface as its upper surface; a reflecting layer disposed on side surfaces of the semiconductor structure; and a positive electrode and a negative electrode disposed on a lower surface of the semiconductor structure. Side surfaces of the semiconductor structure are inclined, expanding upward from the lower surface to the upper surface. At least a portion of each side surface includes a plurality of protrusions, a plurality of recesses, or a combination thereof.

Abstract: Disclosed are an etchant which is used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel, and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant to be used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode, including hydrogen peroxide, an organic acid, and an organic phosphonic acid, wherein the organic acid is at least one member selected from citric acid and malic acid; a content of hydrogen peroxide is from 0.75 to 12% by mass; a content of the organic acid is from 0.75 to 25% by mass; and a content of the organic phosphonic acid is from 0.0005 to 1% by mass, and a method for manufacturing a semiconductor device using the etchant.

Abstract: Approaches for providing a single spacer, double hardmask dual-epi FinFET are disclosed. Specifically, at least one approach for providing the FinFET includes: forming a set of spacers along each sidewall of a plurality of fins of the FinFET device; forming a first ultra-thin hardmask over the plurality of fins; implanting the first ultra-thin hardmask over a first set of fins from the plurality of fins; removing the first ultra-thin hardmask over a second set of fins from the plurality of fins untreated by the implant; forming an epitaxial (epi) layer over the second set of fins; forming a second ultra-thin hardmask over the FinFET device; implanting the second ultra-thin hardmask; removing the second ultra-thin hardmask over the first set of fins; and growing an epi layer over the first set of fins.

Abstract: Compositions useful for the selective removal of silicon nitride materials relative to poly-silicon, silicon oxide materials and/or silicide materials from a microelectronic device having same thereon. The removal compositions include fluorosilicic acid, silicic acid, and at least one organic solvent. Typical process temperatures are less than about 100° C. and typical selectivity for nitride versus oxide etch is about 200:1 to about 2000:1. Under typical process conditions, nickel-based silicides as well as titanium and tantalum nitrides are largely unaffected, and polysilicon etch rates are less than about 1 ? min?1.

Abstract: A double patterning method of forming a plurality of hole patterns having a small pitch using etch selectivities includes forming a patterning mask pattern defining a preliminary hole exposing an upper surface of a buffer mask layer, an inner spacer exposing the upper surface of the buffer mask layer on an inner wall of the preliminary hole, a buffer mask pattern having a first hole, and a core insulating pattern filling the preliminary hole and the first hole, an outer spacer to expose a first portion of the patterning mask pattern on the exposed portion of the outer side of the inner spacer, and an empty space exposing a first portion of the buffer mask pattern. A second portion of the patterning mask pattern and a second portion of the buffer mask pattern are exposed. A second hole is formed by removing the second portion of the buffer mask pattern.

Abstract: In order to provide a copper oxide etchant and an etching method using the same capable of selectively etching exposure/non-exposure portions when laser light exposure is performed by using copper oxide as a thermal-reactive resist material, the copper oxide etchant for selectively etching copper oxides having different oxidation numbers in a copper oxide-containing layer containing the copper oxide as a main component contains at least a chelating agent or salts thereof.

Abstract: Disclosed is a liquid processing method capable of rapidly penetrating a liquid chemical into a concave portion formed on the surface of a substrate with the chemical liquid. The liquid processing method includes wetting the inside of the concave portion by supplying an organic solvent having surface tension smaller than the chemical liquid to the substrate, and cleaning the inside of the concave portion with the chemical liquid by supplying a cleaning liquid including the chemical liquid to the substrate and substituting the liquid inside the concave portion with the chemical liquid.

Abstract: The invention provides a process for removing a film from a substrate, said process comprising applying a composition to the film, and wherein the composition comprises at least the following: a) water; and b) at least one compound selected from the following compounds (i-v): i) NR4HF2 (Formula 1), wherein R?H, alkyl, substituted alkyl, ii) NR4F (Formula 2), wherein R?H, alkyl, substituted alkyl, iii) HF (hydrofluoric acid), iv) H2SiF6 (hexafluorosilicic acid), or v) combinations thereof. The invention also provides a composition comprising at least the following: a) water; and b) at least one compound selected from the following compounds (i-v): i) NR4HF2 (Formula 1), wherein R?H, alkyl, substituted alkyl, ii) NR4F (Formula 2), wherein R?H, alkyl, substituted alkyl, iii) HF (hydrofluoric acid), iv) H2SiF6 (hexafluorosilicic acid), or v) combinations thereof.

Abstract: An aqueous alkaline etching and cleaning composition for treating the surface of silicon substrates, the said composition comprising: (A) a quaternary ammonium hydroxide; and (B) a component selected from the group consisting of water-soluble acids and their water-soluble salts of the general formulas (I) to (V): (R1—S03-)nXn+ (I), R—P032?(Xn+)3-n (II); (RO—S03-)nXn+ (III), RO—P032?(Xn+)3-n, (IV), and [(RO)2P02?]nXn+ (V); wherein the n=1 or 2; X is hydrogen or alkaline or alkaline-earth metal; the variable R1 is an olefinically unsaturated aliphatic or cycloaliphatic moiety and R is R1 or an alkylaryl moiety; the use of the composition for treating silicon substrates, a method for treating the surface of silicon substrates, and methods for manufacturing devices generating electricity upon the exposure to electromagnetic radiation.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Abstract: Processes are described to etch metals. In an embodiment, a process may include contacting a substrate with a stripping solution to remove photoresist from the substrate to produce a stripped substrate. The stripped substrate may include a plurality of solder pillars and a plurality of metal-containing field regions disposed around the plurality of solder pillars. In an illustrative embodiment, the plurality field regions may include copper. Additionally, the process may include rinsing the stripped substrate to produce a rinsed substrate. The rinsed substrate may be substantially free of a Sn layer or a Sn oxide layer. Further, the process may include contacting the rinsed substrate with an etch solution that is capable of removing an amount of one or more metals from the plurality of field regions.

Abstract: A pickling solution for the surface pre-treatment of plastic surfaces in preparation for metallization, the solution comprising a source of Mn(VII) ions; and an inorganic acid; wherein the pickling solution is substantially free of chromium (VI) ions, alkali ions, and alkaline-earth ions.

Abstract: An etchant composition includes ammonium persulfate (((NH4)2)S2O8), an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a phosphate-containing compound, a chloride-containing compound, and residual water.

Abstract: Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby.

Abstract: Disclosed are a test piece and the manufacturing method thereof The test piece includes an insulating substrate and a circuit pattern structure formed on the insulating substrate, wherein circuit pattern structure includes a first metal pattern layer, a second metal pattern layer, a third metal pattern layer, a fourth metal pattern layer, and a fifth metal pattern layer. The first metal pattern layer, the second metal pattern layer, the third metal pattern layer, the fourth metal pattern layer, and the fifth metal pattern layer have same pattern shapes and positions thereof are overlapping in a plane. The first metal pattern layer and the second metal pattern layer are nano-metal films formed by vacuum coating, therefore, the test piece has excellent uniformity of film and low resistance to provide a stable test current to prevent the judging mistakes and to improve the test efficiency.

Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.

Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.

Abstract: Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very little effect on nearby oxides (e.g., silicon dioxide hard mask materials), and etching refractory metals (e.g. tantalum) at an intermediate rate. The solutions are aqueous base solutions (e.g., ammonia-peroxide mixture or TMAH-peroxide mixture) with just enough hydrofluoric acid (HF) added to make the solution's pH about 8-10. Applications include metallization of sub-micron logic structures.

Abstract: An aqueous removal composition having a pH in the range of from 2 to 14 and method for selectively removing an etching mask consisting essentially of TiN, TaN, TiNxOy, TiW, W, or alloy of Ti or W relative to low-k materials from a semiconductor substrate comprising said low-k materials having a TiN, TaN, TiNxOy, TiW, W, or alloy of Ti or W etching mask thereon wherein the removal composition comprises at least one oxidizing agent and a carboxylate compound.

Abstract: A tool and method is provided for mixing multiple components and feeding a single blend of the multiple components into the tool. The method includes adjusting a concentration of etchant solution. The method includes determining an etch target for each batch of wafers of a plurality of batches of wafers entering an etch chamber of a wafer processing tool. The method further includes adjusting a concentration of 40% NH4F to 49% HF for the each batch of wafers of the plurality of batches of wafers entering the wafer processing tool during a single run.

Abstract: Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl3, antimony alkylamines, and antimony alkoxides, such as Sb(OEt)3. The oxygen source may be, for example, ozone. In some embodiments the antimony oxide thin films are deposited in a batch reactor. The antimony oxide thin films may serve, for example, as etch stop layers or sacrificial layers.

Abstract: Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross section is provided below an element of the photonic device and the element may be formed from a ledge of the supporting substrate which is over the cavity.

Abstract: The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.

Abstract: A substrate processing apparatus includes: a substrate holder to hold a substrate in a horizontal posture while rotating the substrate about a vertical rotary axis passing through the center of a plane of the substrate; a guard member having a shape extending along at least part of a surface peripheral area of the substrate, the guard member being placed in a position close to the surface peripheral area of the substrate held by the substrate holder in a noncontact manner; a cup being a tubular member with an open top end, the cup being provided so as to surround the substrate held by the substrate holder and the guard member together; and a nozzle from which a processing liquid is discharged to the surface peripheral area of the substrate held by the substrate holder. The nozzle is placed on a side opposite the cup with respect to at least part of the guard member.

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

Abstract: A method for making a solar cell is disclosed. In accordance with the method of the present invention a composite wafer is formed. The composite layer includes a single crystal silicon wafer, a silicon-based device layer and sacrificial porous silicon sandwiched therebetween. The composite wafer is treated to an aqueous etchant maintained below ambient temperatures to selectively etch the sacrificial porous silicon and release or undercut the silicon-based layer from the single crystal silicon wafer. The released silicon device layer is attached to a substrate to make a solar cell and the released single crystal silicon wafer is reused to make additional silicon device layer.

Abstract: An improved structure of heterojunction field effect transistor (HFET) and a fabrication method thereof are disclosed. The improved HFET structure comprises sequentially a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a Schottky capping layer formed by a higher energy gap material, a tunneling layer formed by a lower energy gap material, a first etching stop layer, and a first n type doped layer.

Abstract: Disclosed is an adjustable semiconductor processing apparatus and a control method thereof. The apparatus comprises a micro chamber with an upper chamber portion defining an upper working surface and a lower chamber portion defining a lower working surface that are relatively moveable towards each other between an open position and a closed position. When the chamber is in the closed position, a cavity formed by the upper working surface and the lower working surface defines a gap between the upper working surface, the lower working surface and a semiconductor wafer received in the cavity for flow of a processing fluid. A drive device enables the upper working surface of the upper chamber portion or/and the lower working surface of the lower chamber portion to tilt or deform to control flow of chemical agents within the micro chamber.

Abstract: The present invention provides an etching liquid for a multilayer thin film containing a copper layer and a titanium layer, and a method of using it for etching a multilayer thin film containing a copper layer and a titanium layer, that is, an etching liquid for a multilayer thin film containing a copper layer and a titanium layer, which comprises (A) hydrogen peroxide, (B) nitric acid, (C) a fluoride ion source, (D) an azole, (E) a quaternary ammonium hydroxide and (F) a hydrogen peroxide stabilizer and has a pH of from 1.5 to 2.5, and a etching method of using it.

Abstract: A polishing composition for a silicon wafer and a rinsing composition for a silicon wafer according to the present invention contain a nonionic surfactant of a polyoxyethylene adduct. The HLB value of the polyoxyethylene adduct is 8 to 15. The weight-average molecular weight of the polyoxyethylene adduct is 1400 or less. The average number of moles of oxyethylene added in the polyoxyethylene adduct is 13 or less. The content of the polyoxyethylene adduct in each of the polishing composition and the rinsing composition is 0.00001 to 0.1% by mass.

Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.

Abstract: A method for single side texturing of a crystalline semiconductor substrate (10) comprises: providing a substrate (10), for example a semiconductor substrate, comprising a first surface (12) and a second surface (14) opposite to one another with respect to the substrate (10); providing a masking layer (21) with a random pattern on the first surface (12) of the substrate (10); and etching the substrate (10) in a polishing solution, thereby texturing the first surface (12) of the substrate (10) and polishing the second surface (14) in a single wet etching step.

Abstract: Disclosed is a technique for attaining high etching selectivity of a silicon nitride film to a silicon oxide film. The etching method includes a step of supplying a silylating agent to a substrate having a silicon nitride film and a silicon oxide film exposed on the surface thereof to thereby form a silylated film as a protective film over the surface of the silicon oxide film. After this step, an etching solution is supplied to the substrate. It is thus possible to selectively etch only the silicon nitride film.

Abstract: Methods and formulations for the selective etching of etch stop layers deposited above metal-based semiconductor layers used in the manufacture of TFT-based display devices are presented. The formulations are based on an alkaline solution. Methods and formulations for the selective etching of molybdenum-based and/or copper-based source/drain electrode layers deposited above metal-based semiconductor layers used in the manufacture of TFT-based display devices are presented. The formulations are based on an alkaline solution.

Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.

Abstract: A method to thin an initial silicon-on-insulator substrate that has a layer of silicon oxide buried between a silicon carrier substrate and a silicon surface layer.

Abstract: The present invention provides a semiconductor device production method and a rinse used in the production method. The method includes: a sealing composition application process in which a semiconductor sealing layer is formed by applying, to at least a portion of a surface of a semiconductor substrate, a semiconductor sealing composition that includes a resin having a cationic functional group and a weight average molecular weight of from 2,000 to 600,000, wherein a content of sodium and a content of potassium are 10 mass ppb or less on an elemental basis, respectively; and, subsequently, a rinsing process in which the surface of the semiconductor substrate on which the semiconductor sealing layer has been formed is rinsed with a rinse having a pH at 25° C. of 6 or lower.

Abstract: The present invention relates to a method for acidic surface etching of a silicon wafer, such as those used for solar cells, comprising contacting at least one surface of a silicon wafer as cut with an acidic etching agent, provided that the wafer is, prior to the acidic etching, not subjected to an alkaline etching step or process. Further, the present invention is directed to Si wafer, photovoltaic cells, PERC photovoltaic cells and solar modules produced according to the method of the present invention.

Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.

Abstract: Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.

Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.

Abstract: A semiconductor process includes the following steps. Firstly, a conductive substrate is provided. Then, at least one insulating pattern is formed on the conductive substrate. Thereafter at least one metal pattern is formed on the insulating pattern. After that, a passivation layer is formed on the conductive substrate to cover the metal pattern by an electroplating process.

Abstract: A method of texturizing a silicon substrate comprising a) contacting the substrate with an etching solution comprising glycolic acid, b) etching a surface of the substrate thereby forming disruptions in said surface of the substrate, and c) removing the etching solution to yield a texturized substrate, said texturized substrate having a plurality of disruptions in at least one surface with a surface density of disruptions of a minimum of 60 disruptions in a 400 micron square area.

Abstract: Embodiments of a method for thinning a wafer are provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. Embodiments of system for forming the thinned wafer are also provided.

Abstract: A liquid treatment apparatus of continuously performing a plating process on multiple substrates includes a temperature controlling container for accommodating a plating liquid; a temperature controller for controlling a temperature of the plating liquid in the temperature controlling container; a holding unit for holding the substrates one by one at a preset position; a nozzle having a supply hole through which the temperature-controlled plating liquid in the temperature controlling container is discharged to a processing surface of the substrate; a pushing unit for pushing the temperature-controlled plating liquid in the temperature controlling container toward the supply hole of the nozzle; and a supply control unit for controlling a timing when the plating liquid is pushed by the pushing unit. The temperature controller controls the temperature of the plating liquid in the temperature controlling container based on the timing when the plating liquid is pushed by the pushing unit.

Abstract: Apparatuses and methods are provided where porous metal is deposited on a substrate, a mask is provided on the porous metal and then an etching is performed.

Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

Abstract: A method and apparatus for dispensing a liquid etchant onto a wafer dispenses the liquid etchant onto a wafer using a scanning dispensing nozzle while controlling the dispensing temperature of the etchant in real time as a function of the radial position of the dispensing nozzle over the wafer. The dispensing temperature of the etchant is controlled to enhance the effectiveness of the etchant and thus compensate for the lower etching rate zones in the wafer.

Abstract: In one exemplary embodiment of the invention, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to a surface of the first layer; after applying the filling material, heating the structure to enable the filling material to at least partially fill the plurality of pores, where heating the structure results in residual filling material being left on the surface of the first layer; and after heating the structure, removing the residual filling material by applying a solvent wash.