Liquid Phase Etching Patents (Class 438/745)
  • Patent number: 8921234
    Abstract: Methods of etching exposed titanium nitride with respect to other materials on patterned heterogeneous structures are described, and may include a remote plasma etch formed from a fluorine-containing precursor. Precursor combinations including plasma effluents from the remote plasma are flowed into a substrate processing region to etch the patterned structures with high titanium nitride selectivity under a variety of operating conditions. The methods may be used to remove titanium nitride at faster rates than a variety of metal, nitride, and oxide compounds.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jie Liu, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Seung Park, Zhijun Chen, Ching-Mei Hsu
  • Patent number: 8921177
    Abstract: A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hsi Yeh, Hsien-Hsin Lin, Ying-Hsueh Chang Chien, Yi-Fang Pai, Chi-Ming Yang, Chin-Hsiang Lin
  • Patent number: 8920567
    Abstract: A post metal chemical-mechanical planarization (CMP) cleaning process for advanced interconnect technology is provided. The process, which follows CMP, combines an acidic clean and a basic clean in sequence. The process can achieve a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. The process also eliminates the circular ring defects that occur intermittently during roller brush cleans within a roller brush clean module.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Vamsi Devarapalli, Colin J. Goyette, Michael R. Kennett, Mahmoud Khojasteh, Qinghuang Lin, James J. Steffes, Adam D. Ticknor, Wei-tsu Tseng
  • Patent number: 8916429
    Abstract: Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Li Chou, Shao-Yen Ku, Pei-Hung Chen, Jui-Ping Chuang
  • Patent number: 8912098
    Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
  • Publication number: 20140357089
    Abstract: The embodiments disclosed herein pertain to novel methods and apparatus for removing material from a substrate. In certain embodiments, the method and apparatus are used to remove negative photoresist, though the disclosed techniques may be implemented to remove a variety of materials. In practicing the disclosed embodiments, a stripping solution may be introduced from an inlet to an internal manifold, sometimes referred to as a cross flow manifold. The solution flows laterally through a relatively narrow cavity between the substrate and the base plate. Fluid exits the narrow cavity at an outlet, which is positioned on the other side of the substrate, opposite the inlet and internal manifold. The substrate spins while in contact with the stripping solution to achieve a more uniform flow over the face of the substrate. In some embodiments, the base plate includes protuberances which operate to increase the flow rate (and thereby increase the local Re) near the face of the substrate.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Applicant: Novellus Systems, Inc.
    Inventors: Bryan L. BUCKALEW, Steven T. MAYER, David PORTER, Thomas A. PONNUSWAMY
  • Patent number: 8900478
    Abstract: Disclosed are an etchant which is used for redistribution of a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel; and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and citric acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of citric acid of from 1 to 20% by mass, with a molar ratio of hydrogen peroxide and citric acid being in the range of from 0.3 to 5; an etchant for selective etching of copper which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and malic acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of malic acid of from 1.5 to 25% by mass, with a molar ratio of hydrogen peroxide and malic acid being in the range of from 0.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 2, 2014
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Akira Hosomi, Kensuke Ohmae
  • Patent number: 8894867
    Abstract: Disclosed is a method for producing ZnO contact layers for solar cells. The layers are etched using hydrofluoric acid so as to generate a texture.
    Type: Grant
    Filed: August 7, 2010
    Date of Patent: November 25, 2014
    Assignee: Forschungszentrum Juelich GmbH
    Inventors: Eerke Bunte, Jorj Owen, Juergen Huepkes
  • Patent number: 8895390
    Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Dipankar Pramanik
  • Patent number: 8895446
    Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Hao-Ming Lien
  • Publication number: 20140342572
    Abstract: An apparatus and a method for selectively etching an encapsulant forming a package of resinous material around an electronic device includes an electronic device package mountable on the etch head; a conductive electrode in electrical contact with package leads of the electronic device package to apply a first voltage to the package leads of the electronic device; a first pump configured to pump a first quantity of the etchant solution from the source into the etch head where the etchant solution is electrically biased to a second voltage different from the first voltage and is cooled to a temperature below the ambient temperature. An etch cavity is formed on an exterior surface of the electronic device package. When the etchant solution has etched through an exterior surface of the electronic device package, the conductive bond wires of the electronic device is prevented from being etched by the applied first voltage.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 20, 2014
    Inventor: Alan M. Wagner
  • Patent number: 8883030
    Abstract: A substrate processing apparatus comprising a substrate holding rotating mechanism, a process liquid supply mechanism having a nozzle for dispensing a process liquid toward a principal face of the substrate, a processing liquid reservoir for holding sufficient process liquid to form a liquid film covering the whole principal face of the substrate, a liquid film forming unit for forming the liquid film by supplying the process liquid onto the principal face of the substrate in a single burst, and a control unit for controlling the liquid film forming unit and the process liquid supply mechanism such that the process liquid is dispensed from the process liquid nozzle toward the principal face of the substrate after formation of the liquid film covering the whole area of the principal face of the substrate by the liquid film forming unit.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: November 11, 2014
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Masahiro Miyagi, Koji Hashimoto, Toru Endo
  • Patent number: 8883571
    Abstract: A method of manufacturing a transistor includes: forming an oxide semiconductor film and a gate electrode on a substrate, the oxide semiconductor film having a channel region, and the gate electrode facing the channel region; and forming an insulating film covering the gate electrode and the oxide semiconductor film. Infiltration of moisture from the insulating film into the oxide semiconductor film is suppressed by the substrate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventors: Narihiro Morosawa, Motohiro Toyota
  • Patent number: 8883653
    Abstract: An inventive substrate treatment method includes a silylation step of supplying a silylation agent to a substrate, and an etching step of supplying an etching agent to the substrate after the silylation step. The method may further include a repeating step of repeating a sequence cycle including the silylation step and the etching step a plurality of times. The cycle may further include a rinsing step of supplying a rinse liquid to the substrate after the etching step. The cycle may further include a UV irradiation step of irradiating the substrate with ultraviolet radiation after the etching step. The method may further include a pre-silylation or post-silylation UV irradiation step of irradiating the substrate with the ultraviolet radiation before or after the silylation step.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: November 11, 2014
    Assignee: SCREEN Holdings Co., Ltd.
    Inventor: Akio Hashizume
  • Patent number: 8883033
    Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Sheng Chen, Shin-Chi Chen, Chih-Yueh Li, Ted Ming-Lang Guo, Bo-Syuan Lee, Tsung-Hsun Tsai, Yu-Chin Cheng
  • Patent number: 8883652
    Abstract: A silicon etching liquid characterized by anisotropically dissolving monocrystalline silicon therein by using an aqueous solution containing a quaternary ammonium hydroxide and an aminoguanidine salt and an etching method of silicon using the instant etching liquid are an etching liquid and an etching method enabling one to perform processing at a high etching rate in etching processing of silicon, particularly in etching processing of silicon in a manufacturing process of MEMS parts or semiconductor devices.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: November 11, 2014
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kazuyoshi Yaguchi, Ryuji Sotoaka
  • Patent number: 8877640
    Abstract: A cleaning solution is provided. The cleaning solution includes an aliphatic polycarboxylic acid, a chain sulfonic acid substantially less than 4 wt % and an amine containing buffer agent.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: November 4, 2014
    Assignee: United Microelectronics Corporation
    Inventors: An-Chi Liu, Tien-Cheng Lan, Kuei-Hsuan Yu
  • Patent number: 8877653
    Abstract: A solvent vapor containing a solvent material capable of dissolving hydrogen fluoride is supplied to a surface of a substrate, thereby covering the surface of the substrate with a liquid film containing solvent material. Thereafter an etching vapor containing a hydrogen fluoride is supplied to the surface of the substrate covered by the liquid film containing the solvent material, thereby etching the surface of the substrate.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 4, 2014
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Takahiro Yamaguchi, Akio Hashizume, Yuya Akanishi, Takashi Ota
  • Patent number: 8877077
    Abstract: A method of printing comprises the steps of: providing a solid state material having an exposed surface; applying an auxiliary layer to the exposed surface to form a composite structure, the auxiliary layer having a stress pattern; subjecting the composite structure to conditions facilitating fracture of the solid state material along a plane at a depth therein; and removing the auxiliary layer and, therewith, a layer of the solid state material terminating at the fracture depth, wherein an exposed surface of the removed layer of solid state material has a surface topology corresponding to the stress pattern.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: November 4, 2014
    Assignee: Siltectra GmbH
    Inventor: Lukas Lichtensteiger
  • Patent number: 8871108
    Abstract: A method of removing carbon materials, preferably amorphous carbon, from a substrate includes dispensing a liquid sulfuric acid composition including sulfuric acid and/or its desiccating species and precursors and having a water/sulfuric acid molar ratio of no greater than 5:1 onto an material coated substrate in an amount effective to substantially uniformly coat the carbon material coated substrate. The liquid sulfuric acid composition is exposed to water vapor in an amount effective to increase the temperature of the liquid sulfuric acid composition above the temperature of the liquid sulfuric acid composition prior to exposure to the water vapor. In preferred embodiments, amorphous carbon is selectively removed as compared to a silicon oxide (e.g., silicon dioxide) and/or silicon nitride.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignee: TEL FSI, Inc.
    Inventor: Jeffrey M. Lauerhaas
  • Patent number: 8871653
    Abstract: An etching agent for a semiconductor substrate, which is capable of etching a titanium (Ti)-based metal film on a semiconductor substrate and an etching method using the etching agent, and relates to a liquid for preparing the etching agent for a semiconductor substrate composed of a solution comprising (A) hydrogen peroxide, (B) a phosphonic acid chelating agent having a hydroxyl group, (C) a basic compound, and (D-1) a copper anticorrosive. An etching method for etching a titanium (Ti)-based metal film on a semiconductor substrate using the etching agent. A solution comprising (B) a phosphonic acid chelating agent having a hydroxyl group, (C) a basic compound, and (D-1) a copper anticorrosive.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 28, 2014
    Assignee: Wako Pure Chemical Industries, Ltd.
    Inventors: Osamu Matsuda, Nobuyuki Kikuchi, Ichiro Hayashida, Satoshi Shirahata
  • Publication number: 20140315331
    Abstract: Candidate wet processes for native oxide removal from, and passivation of, germanium surfaces can be screened by high-productivity combinatorial variation of different process parameters on different site-isolated regions of a single substrate. Variable process parameters include the choice of hydrohalic acid used to remove the native oxide, the concentration of the acid in the solution, the exposure time, and the use of an optional sulfur passivation step. Measurements to compare the results of the process variations include attenuated total reflectance Fourier transform infrared spectroscopy (ATR-FTIR), contact angle, atomic force microscopy (AFM), scanning electron microscopy (SEM), and X-ray fluorescence (XRF). A sample screening experiment indicated somewhat less native oxide regrowth using HCl or HBr without sulfur passivation, compared to using HF with sulfur passivation.
    Type: Application
    Filed: March 11, 2014
    Publication date: October 23, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Sandip Niyogi, Shuogang Huang, Chi-I Lang
  • Patent number: 8865493
    Abstract: A method of forming a light conversion element includes providing a semiconductor construction having a first photoluminescent element epitaxially grown together with a second photoluminescent element. A first region is etched in the first photoluminescent element from a first side of the semiconductor construction and a second region is etched in the second photoluminescent element from a second side of the semiconductor construction. In some embodiments the wavelength converter is attached to an electroluminescent element, such as a light emitting diode (LED).
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: October 21, 2014
    Assignee: 3M Innovative Properties Company
    Inventors: Tommie W. Kelley, Andrew J. Ouderkirk, Catherine A. Leatherdale
  • Patent number: 8859396
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, John M. Parsey, Jr.
  • Patent number: 8859435
    Abstract: A method of removing materials, and preferably photoresist, from a substrate comprises dispensing a liquid sulfuric acid composition comprising sulfuric acid and/or its desiccating species and precursors and having a water/sulfuric acid molar ratio of no greater than 5:1 onto an material coated substrate in an amount effective to substantially uniformly coat the material coated substrate. The substrate is preferably heated to a temperature of at least about 90° C., either before, during or after dispensing of the liquid sulfuric acid composition. After the substrate is at a temperature of at least about 90° C., the liquid sulfuric acid composition is exposed to water vapor in an amount effective to increase the temperature of the liquid sulfuric acid composition above the temperature of the liquid sulfuric acid composition prior to exposure to the water vapor. The substrate is then preferably rinsed to remove the material.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: October 14, 2014
    Assignee: TEL FSI, Inc.
    Inventors: Kurt Karl Christenson, Ronald J. Hanestad, Patricia Ann Ruether, Thomas J. Wagener
  • Patent number: 8852447
    Abstract: A method for simultaneously detecting and separating a target analyte such as a protein or other macromolecule that includes providing a porous silicon matrix on the silicon substrate, exposing the porous silicon matrix to an environment suspect of containing the target analyte, observing optical reflectivity of the porous silicon matrix; and correlating the changes in the silicon substrate to the target analyte.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 7, 2014
    Assignee: The Regents of the University of California
    Inventors: Michael J. Sailor, Gaurav Abbi, Boyce E. Collins, Keiki-Pua S. Dancil
  • Publication number: 20140273499
    Abstract: A method and a system that include providing a localized dispensing apparatus. A substrate having a material disposed on its top surface is oriented above the localized dispensing apparatus. A chemical is then dispensed from the localized dispensing apparatus onto the top surface of the oriented substrate. The chemical removes the material. The path for the material removal may be determined and the localized dispensing apparatus programmed to provide chemical according to the path.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Min Huang, Chih-Wei Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20140273498
    Abstract: In a substrate processing apparatus, provided are an upper nozzle for supplying a chemical liquid having a temperature higher than that of a substrate onto an upper surface of the substrate and a heating liquid supply nozzle for supplying a heating liquid having a temperature higher than that of the substrate onto a lower surface of the substrate. It is thereby possible to suppress or prevent a decrease in the temperature of the chemical liquid supplied on the upper surface of the substrate from a center portion of the substrate toward an outer peripheral portion thereof. In a supply nozzle, the heating liquid supply nozzle is positioned on the inner side of a heating gas supply nozzle for ejecting heating gas in drying the substrate. It is thereby possible to simplify and downsize a structure used for heating the lower surface of the substrate.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Applicant: DAINIPPON SCREEN MFG. CO., LTD.
    Inventors: Kenji KOBAYASHI, Takemitsu MIURA
  • Publication number: 20140273497
    Abstract: Embodiments provided herein describe systems and methods for processing substrates. A substrate having a plurality of site-isolated regions defined thereon is provided. A plurality of wet processes is simultaneously performed. Each of the plurality of wet processes is performed on one of the plurality of site-isolated regions defined on the substrate. The simultaneously performing includes exposing each of the plurality of site-isolated regions to one of a plurality of wet processing formulations. Each of the plurality of wet processing formulations includes a component. The respective component is added to at least some of the plurality of wet processing formulations during the exposing. A processing condition is varied between at least two of the plurality of wet processes in a combinatorial manner.
    Type: Application
    Filed: December 17, 2013
    Publication date: September 18, 2014
    Applicant: Intermolecular Inc.
    Inventors: Makonnen Payne, Kim Van Berkel
  • Patent number: 8834729
    Abstract: A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes the steps of a) providing a blank printed wiring member comprising a copper foil laminated to a dielectric substrate; b) masking the blank printed wiring member to protect regions of the copper foil; c) removing copper in unprotected regions of the blank printed wiring member to form a patterned printed wiring member including contact pads and connector pads; d) depositing a nickel coating on the patterned printed wiring member using an electroless nickel deposition process; e) depositing a gold layer on the nickel coating using an electroless gold deposition process; and f) depositing palladium on the gold layer using an electroless palladium deposition process to improve wear resistance of the connector pads while preserving bondability of the contact pads.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: September 16, 2014
    Assignee: Eastman Kodak Company
    Inventors: Samuel Chen, Charles I. Levey
  • Patent number: 8835329
    Abstract: Methods for combinatorially processing semiconductor substrates are provided. The methods may involve receiving a substrate into a combinatorial processing chamber and sealing a plurality of flow cells against a surface of the substrate. The plurality of flow cells is enclosed within the combinatorial processing chamber to define an enclosed external environment for the plurality of flow cells. A pressure differential is created between a reaction area of the plurality of flow cells of the combinatorial processing chamber and the external environment, wherein each flow cells of the plurality of flow cells defines a site isolating region of the substrate. The regions the substrate are then combinatorially processed.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: September 16, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Sandeep Mariserla, Aaron T. Francis, Jeffrey Chih-Hou Lowe, Robert Anthony Sculac
  • Publication number: 20140256124
    Abstract: A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Jung Hsu, Gin-Chen Huang, Yi-An Lin, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 8828877
    Abstract: The present invention provides an etching solution less affected by trench structures and also provides an isolation structure-formation process employing the solution. The etching solution contains hydrofluoric acid and an organic solvent. The organic solvent has a ?H value defined by Hansen solubility parameters in the range of 4 to 12 inclusive and the saturation solubility thereof in water is 5 wt % or more at 20° C. This solution can be adopted instead of known etching solutions used in conventional production processes of semiconductor elements.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: September 9, 2014
    Assignee: AZ Electronic Materials USA Corp.
    Inventor: Issei Sakurai
  • Publication number: 20140248780
    Abstract: Methods of etching a patterned substrate may include flowing an oxygen-containing precursor into a first remote plasma region fluidly coupled with a substrate processing region. The oxygen-containing precursor may be flowed into the region while forming a plasma in the first remote plasma region to produce oxygen-containing plasma effluents. The methods may also include flowing a fluorine-containing precursor into a second remote plasma region fluidly coupled with the substrate processing region while forming a plasma in the second remote plasma region to produce fluorine-containing plasma effluents. The methods may include flowing the oxygen-containing plasma effluents and fluorine-containing plasma effluents into the processing region, and using the effluents to etch a patterned substrate housed in the substrate processing region.
    Type: Application
    Filed: February 21, 2014
    Publication date: September 4, 2014
    Applicant: Applied Materials, Inc.
    Inventors: Nitin K. Ingle, Dmitry Lubomirsky, Xinglong Chen, Shankar Venkataraman
  • Patent number: 8822325
    Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: September 2, 2014
    Inventors: Ching-Yu Ni, Chia-Ming Cheng, Nan-Chun Lin
  • Patent number: 8822347
    Abstract: A system to form a wet soluble lithography layer on a semiconductor substrate includes providing the substrate, depositing a first layer comprising a first material on the substrate, and depositing a second layer comprising a second material on the substrate. In an embodiment, the first material comprises a different composition than the second material and one of the first layer and the second layer includes silicon.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Wang, Ching-Yu Chang
  • Patent number: 8822346
    Abstract: A reaction block having a plurality of reaction chambers defined therein is provided. A bottom surface of each of the reaction chambers is configured to provide a seal for a corresponding reaction region on the substrate and around a periphery of the substrate. The reaction block includes a plurality of inlet channels and provides a gap between a top surface of the substrate and a bottom surface of the reaction block. The gap accepts a fluid from the inlet channels, wherein the reaction block includes a plurality of vacuum channels having access to the bottom surface of the reaction block to remove the fluid from the gap. A method of selectively etching a substrate for combinatorial processing is also provided.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: September 2, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Kurt Weiner
  • Patent number: 8821751
    Abstract: A CMP composition and associated method are provided that afford good corrosion protection and low defectivity levels both during and subsequent to CMP processing. This composition and method are useful in CMP (chemical mechanical planarization) processing in semiconductor manufacture involving removal of metal(s) and/or barrier layer material(s) and especially for CMP processing in low technology node applications.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: September 2, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Xiaobo Shi, Ronald Martin Pearlstein
  • Publication number: 20140242804
    Abstract: The present disclosure relates to a method and apparatus for performing a dry plasma procedure, while mitigating internal contamination of a semiconductor substrate. In some embodiments, the apparatus includes a semiconductor processing tool having a dry process stage with one or more dry process elements that perform a dry plasma procedure on a semiconductor substrate received from an input port. A wafer transport system transports the semiconductor substrates from the dry process stage to a wet cleaning stage located downstream of the dry process stage. The wet cleaning stage has one or more wet cleaning elements that perform a wet cleaning procedure to remove contaminants from a surface of the semiconductor substrates before the semiconductor substrate is provided to an output port. The wet cleaning procedure prior removes internal contaminants of the dry process procedure from the semiconductor substrate and thereby improves wafer manufacturing quality.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Shao-Yen Ku, Tsai-Pao Su, Wen-Chang Tsai, Chia-Wen Li, Yu-Yen Hsu
  • Patent number: 8815108
    Abstract: A method of depositing a non-continuous coating of a first material on a substrate, comprising: a) the formation of a mask on this substrate, by forming at least two mask layers, and etching of at least one cavity in these layers, this cavity having an outline such that a coating, deposited on the substrate, through the cavities of the mask, has at least one discontinuity over said outline of the cavity; b) the deposition of the first material on the substrate, through the cavities of the mask, the coating thus deposited having at least one discontinuity over the outline of said cavity; and c) the mask is removed.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: August 26, 2014
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bruno Remiat, Laurent Vandroux, Florent Souche
  • Patent number: 8815633
    Abstract: A method of fabricating a 3-dimensional structure on a copper-indium-gallium-diselenide material comprises steps: preparing a CIGS (Copper Indium Gallium Diselenide) substrate, and defining two types of regions complementary to each other on the CIGS substrate; providing a mold absorbing an etching solution that can etch the CIGS substrate instead of the mold; aligning the mold to the two types of regions, and allowing the etching solution to flow out from the mold and contact with the two types of regions to etch the two types of regions for generating a level drop between the two types of regions and forming a 3-dimensional (3D) structure on the CIGS substrate. As a result, the present invention can fabricate a large-area 3D structure on a CIGS substrate rapidly without using expensive equipments or complicated processes.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: August 26, 2014
    Assignee: National Tsing Hua University
    Inventors: Yu-Lun Chueh, Hsiang-Ying Cheng, Yi-Chung Wang, Yu-Ting Yen
  • Patent number: 8809184
    Abstract: One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 19, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Jin Cho, Jongwook Kye, Harry J. Levinson
  • Patent number: 8808555
    Abstract: Provided is a method of manufacturing a substrate for a liquid discharge head including a first face, energy generating elements which generate the energy to be used to discharge a liquid to a second face opposite to the first face, and liquid supply ports for supplying the liquid to the energy generating elements. The method includes preparing a silicon substrate having, at the first face, an etching mask layer having an opening corresponding to a portion where the liquid supply ports are to be formed, and having first recesses provided within the opening, and second recesses provided in the region of the second face where the liquid supply ports are to be formed, the first recesses and the second recesses being separated from each other by a portion of the substrate; and etching the silicon substrate by crystal anisotropic etching from the opening of the first face to form the liquid supply ports.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: August 19, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keiji Watanabe, Shuji Koyama, Hiroyuki Abo, Keiji Matsumoto
  • Publication number: 20140227883
    Abstract: In a substrate processing apparatus, an outer edge portion of a substrate in a horizontal state is supported from below by an annular substrate supporting part, and a lower surface facing part having a facing surface facing a lower surface of the substrate is provided inside the substrate supporting part. A gas ejection nozzle for ejecting heated gas toward the lower surface is provided in the lower surface facing part, and the substrate is heated by the heated gas when an upper surface of the rotating substrate is processed with a processing liquid ejected from an upper nozzle. Further, a lower nozzle is provided in the lower surface facing part, to thereby perform a processing on the lower surface with a processing liquid. Since the gas ejection nozzle protrudes from the facing surface, a flow of the processing liquid into the gas ejection nozzle can be suppressed during the processing.
    Type: Application
    Filed: February 12, 2014
    Publication date: August 14, 2014
    Applicant: DAINIPPON SCREEN MFG. CO., LTD.
    Inventors: Kenji IZUMOTO, Takemitsu MIURA, Kenji KOBAYASHI, Kazuhide SAITO, Akihisa IWASAKI
  • Patent number: 8796157
    Abstract: Method of selectively etching a first material on a substrate with a high selectivity towards a second material by flowing a liquid etchant across a substrate surface at a flow sufficiently fast to generate a minimum mean velocity parallel to the substrate's surface, wherein the first material is selected from a group including materials with semiconducting properties based on at least two different chemical elements.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: August 5, 2014
    Assignee: Lam Research AG
    Inventor: Gerald Wagner
  • Patent number: 8791029
    Abstract: A stamp having a nanoscale structure and a manufacturing method thereof are disclosed. The stamp includes a substrate, a buffer layer, and a nanoscale stamp layer. The method comprises forming a buffer layer on the substrate, and forming a stamp layer having a nanoscale structure on the buffer layer.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: July 29, 2014
    Assignee: Epistar Corporation
    Inventors: Chiu-Lin Yao, Ta-Cheng Hsu, Min-Hsun Hsieh
  • Patent number: 8790531
    Abstract: A high purity, non-toxic, environmentally friendly method for anisotropically etching single crystal silicon and etching polysilicon, suitable for microelectronics, optoelectronics and microelectromechanical (MEMS) device fabrication, using high purity aqueous ammonium hydroxide (NH4OH) solution generated at the point of use, is presented. The apparatus of the present invention supports generation of high purity aqueous NH4OH solution from ammonia NH3 gas dissolved into distilled/deionized water and maintained in equilibrium with an overpressure of NH3, within a hermetically enclosed chamber at the optimal temperature between 70-90° C., preventing evaporation of NH3 gas from aqueous NH4OH solution for achieving a high anisotropic etching rate. Other liquid anisotropic etching methods for silicon may use tetramethylammonium hydroxide (TMAH).
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: July 29, 2014
    Inventor: Alvin Gabriel Stern
  • Patent number: 8790470
    Abstract: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-san Lee, Chang-Ki Hong, Kun-Tack Lee, Woo-Gwan Shim, Jeong-Nam Han, Jung-Min Oh, Kwon-Taek Lim, Ha-Soo Hwang, Haldorai Yuvaraj, Jae-Mok Jung
  • Patent number: 8791028
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes a step of forming a dummy-fin semiconductor on a semiconductor substrate; a step of forming an insulating layer, into which a lower part of the dummy-fin semiconductor is buried, on the semiconductor substrate; a step of forming a fin semiconductor, which is bonded to a side face at an upper part of the dummy-fin semiconductor, on the insulating layer; and a step of removing the dummy-fin semiconductor on the insulating layer with the fin semiconductor being left on the insulating layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kimitoshi Okano
  • Publication number: 20140206200
    Abstract: A method for performing an oxide removal process is described. The method includes providing a substrate having an oxide layer, and preparing a patterned mask layer on the oxide layer, wherein the patterned mask layer has a pattern exposing at least a portion of the oxide layer. An HF treatment of the substrate is performed to transfer the pattern at least partially through the oxide layer, wherein the HF treatment exposes a silicon surface. Following the performing of the HF treatment, a surface property of the silicon surface is modified, wherein the modifying includes administering at least one oxidizing agent to contact the silicon surface to cause chemical oxidation of the silicon surface. And, following the modifying of the surface property, at least a portion of the patterned mask layer or a residual portion of the patterned mask layer is removed.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 24, 2014
    Applicant: TEL FSI, Inc.
    Inventor: Steven L. Nelson