Insulative Material Deposited Upon Semiconductive Substrate Patents (Class 438/778)
  • Publication number: 20140038424
    Abstract: A polyimide film is effectively formed on a complicated surface. The polyimide film is formed by reacting, on the surface, diamine monomer and tetracarboxylic acid dianhydride monomer both of which are dissolved within carbon dioxide in a supercritical states, together with a polyamic acid resulting from a reaction between the diamine monomer and the tetracarboxylic acid dianhydride reached to the surface.
    Type: Application
    Filed: March 1, 2013
    Publication date: February 6, 2014
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Mitsuhiro HORIKAWA, Hiroyuki ODE, Masashi HARUKI, Shigeki TAKISHIMA, Shinichi KIHARA
  • Patent number: 8643151
    Abstract: An embodiment of the disclosure provides a semiconductor device. The semiconductor device includes a plurality of metallization layers comprising a topmost metallization layer. The topmost metallization layer has two metal features having a thickness T1 and being separated by a gap. A composite passivation layer comprises a HDP CVD oxide layer under a nitride layer. The composite passivation layer is disposed over the metal features and partially fills the gap. The composite passivation layer has a thickness T2 about 20% to 50% of the thickness T1.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: February 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Hao Liu, Chyi-Tsong Ni, Hsiao-Yin Lin, Chung-Min Lin
  • Patent number: 8642446
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: February 4, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Xia Feng, Kang Chen, Jianmin Fang
  • Patent number: 8642487
    Abstract: A film deposition method including: a step of carrying a substrate into a vacuum chamber, and placing the substrate on a turntable; a step of rotating the turntable; and an adsorption-formation-irradiation step of supplying a first reaction gas to the substrate from a first reaction gas supply part to adsorb the first reaction gas on the substrate; supplying a second reaction gas from a second reaction gas supply part so that the first reaction gas adsorbed on the substrate reacts with the second reaction gas so as to form a reaction product on the substrate; and supplying a hydrogen containing gas to a plasma generation part that is separated from the first reaction gas supply part and the second reaction gas supply part in a circumferential direction of the turntable so as to generate plasma above the turntable and to irradiate the plasma to the reaction product.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: February 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Shigehiro Ushikubo, Tatsuya Tamura, Shigenori Ozaki, Takeshi Kumagai, Hiroyuki Kikuchi
  • Publication number: 20140027887
    Abstract: A semiconductor device includes a semiconductor substrate and at least one integrated circuit formed on a frontside of the semiconductor substrate. A shielding layer is formed on a backside of the semiconductor substrate. The shielding layer includes one or more elements having a high thermal neutron absorption cross section.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Inventor: Stephen J. Wong
  • Patent number: 8637400
    Abstract: A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Charles W. Koburger, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8637412
    Abstract: A first PECVD process incorporating a silicon oxide precursor alone and then with an organo-silicon precursor with increasing flow while the flow of the silicon oxide precursor is reduced to zero provides a graded carbon adhesion layer whereby the content of C increases with layer thickness and a second PECVD process incorporating an organo-silicon precursor including an organic porogen provides a multiphase ultra-low k dielectric. The multiphase ultra-low k PECVD process uses high frequency radio frequency power just above plasma initiation in a PECVD chamber. An energy post treatment is also provided. A porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa is formed.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Thomas Jasper Haigh, Jr., Kelly Malone, Son Van Nguyen, Vishnubhai Vitthalbhai Patel, Hosadurga Shobha
  • Publication number: 20140024180
    Abstract: Embodiments of the invention provide methods of an interface adhesion improvement methods used on a transparent substrate for OLED or thin film transistor applications. In one embodiment, a method of forming a buffer layer on a surface of a substrate includes providing a substrate having an planarization material disposed thereon in a processing chamber, supplying a buffer layer gas mixture including a silicon containing gas into the processing chamber, controlling a substrate temperature less than about 100 degrees Celsius, forming a buffer layer on the planarization material, supplying an encapsulating barrier layer deposition gas mixture including a silicon containing gas and a nitrogen containing gas into the processing chamber, and forming an encapsulating barrier layer on the buffer layer.
    Type: Application
    Filed: July 20, 2013
    Publication date: January 23, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Young Jin CHOI, Jrjyan Jerry CHEN, Beom Soo PARK, Soo Young CHOI
  • Publication number: 20140021589
    Abstract: A semiconductor of which a substance such as a semiconductor photocatalyst is uniformly coated on the surface thereof with a graphitic carbon film and a method of fabricating the same are disclosed. According to the inventive method, a graphitic carbon film having a thickness of 1 nm or less is uniformly formed on the surface of the semiconductor by performing hydrothermal synthesis and pyrolysis on glucose, so as to keep the original structure crystallinity of the semiconductor photocatalyst to be a support of the carbon film.
    Type: Application
    Filed: December 7, 2012
    Publication date: January 23, 2014
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Jeung-Ku KANG, Dong-Ki LEE, Kyu-Sung HAN, Weon-Ho SHIN, Jung-Woo LEE, Jung-Hoon CHOI, Kyung-Min CHOI, Yeob LEE
  • Patent number: 8633050
    Abstract: A method of manufacturing a solar cell having an effective minority charge carrier lifetime (?eff) of at least 500 ?s, said method comprising: providing a semiconductor wafer; and passivating a surface of said wafer by ALD-depositing a metal oxide layer on said surface by sequentially and alternatingly: (iii) exposing said surface to a first precursor, resulting in a coverage of the surface with the first precursor, and (iv) exposing said surface to a second precursor, resulting in a coverage of the surface with the second precursor, wherein at least one of steps (i) and (ii) is stopped before the coverage of the surface reaches a saturation level.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: January 21, 2014
    Assignee: ASM International N.V.
    Inventor: Dieter Pierreux
  • Patent number: 8633114
    Abstract: Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: January 21, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya E. Sato, Maitreyee Mahajani
  • Patent number: 8633119
    Abstract: Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: January 21, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya E. Sato, Maitreyee Mahajani
  • Publication number: 20140015124
    Abstract: Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polymide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.
    Type: Application
    Filed: July 16, 2012
    Publication date: January 16, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Owen R. Fay, Luke G. England, Christopher J. Gambee
  • Publication number: 20140017904
    Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 16, 2014
    Inventors: Vishal GAURI, Raashina HUMAYUN, Chi-I LANG, Judy H. HUANG, Michael BARNES, Sunil SHANKER
  • Patent number: 8629067
    Abstract: Methods of forming dielectric layers are described. The method may include the steps of mixing a silicon-containing precursor with a radical-nitrogen precursor, and depositing a dielectric layer on a substrate. The radical-nitrogen precursor is formed in a remote plasma by flowing hydrogen (H2) and nitrogen (N2) into the plasma in order to allow adjustment of the nitrogen/hydrogen ratio. The dielectric layer is initially a silicon-and-nitrogen-containing layer which may be converted to a silicon-and-oxygen-containing layer by curing and/or annealing the film in an oxygen-containing environment.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: January 14, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Xiaolin Chen, Matthew L. Miller, Nitin K. Ingle, Shankar Venkataraman
  • Publication number: 20140011356
    Abstract: A chuck, a system including a chuck and a method for making a semiconductor device are disclosed. In one embodiment the chuck includes a first conductive region configured to be capacitively coupled to a first RF power generator, a second conductive region configured to be capacitively coupled to a second RF power generator and an insulation region that electrically insulates the first conductive region from the second conductive region.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 9, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Manfred Engelhardt
  • Patent number: 8623741
    Abstract: In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one process on the structure; and after performing the at least one process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Geraud Jean-Michel Dubois, Teddie P. Magbitang, Willi Volksen, Theo J. Frot
  • Patent number: 8618003
    Abstract: Electronic devices can be prepared by forming a patterned thin film on a suitable receiver substrate. A cyanoacrylate polymer is used as a deposition inhibitor material and applied first as a deposition inhibitor material. The deposition inhibitor material can be patterned to provide selected areas on the receiver substrate where the deposition inhibitor is absent. An inorganic thin film is then deposited on the receiver substrate using a chemical vapor deposition technique only in those areas where the deposition inhibitor material is absent. The cyanoacrylate polymer deposition inhibitor material can be applied by thermal transfer from a donor element to a receiver substrate before a patterned thin film is formed.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: December 31, 2013
    Assignee: Eastman Kodak Company
    Inventors: Mitchell S. Burberry, David H. Levy
  • Publication number: 20130344704
    Abstract: Embodiments of the invention provide methods for curing an ultra low-k dielectric film within a UV processing chamber. In one embodiment, the method includes depositing an ultra low-k dielectric layer on a substrate in a deposition chamber, and subjecting the deposited ultra low-k dielectric layer to a UV curing processes in a UV processing chamber. The method includes stabilizing the UV processing chamber by flowing an oxygen gas and a purge gas into the UV processing chamber at a flow ratio of about 1:50000 to about 1:100. While flowing the oxygen-doped purge gas, the substrate is exposed to UV radiation to cure the deposited ultra low-k dielectric layer. The inventive oxygen-doped purge curing process provides an alternate pathway to build silicon-oxygen network of the ultra low-k dielectric material, thereby accelerating cross-linking efficiency without significantly affecting the film properties of the deposited ultra low-k dielectric material.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 26, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Mahendra CHHABRA, Scott A. HENDRICKSON, Sanjeev BALUJA, Tsutomu KIYOHARA, Juan Carlos ROCHA-ALVAREZ, Alexandros T. DEMOS
  • Publication number: 20130341769
    Abstract: The present invention relates to aluminium oxide-based passivation layers which simultaneously act as diffusion barrier for underlying wafer layers against aluminium and other metals. Furthermore, a process and suitable compositions for the production of these layers are described.
    Type: Application
    Filed: February 9, 2012
    Publication date: December 26, 2013
    Applicant: MERCK PATENT GMBH
    Inventors: Ingo Koehler, Oliver Doll, Werner Stockum, Sebastian Barth
  • Publication number: 20130337657
    Abstract: A method and apparatus are provided for plasma-based processing of a substrate based on a plasma source having at least two adjacent electrodes positioned with the long dimensions parallel to define a first gap minimum between the two electrodes of from 5 millimeters to 40 millimeters. A second gap minimum is defined between the two electrodes and the substrate. AC power is provided to the two electrodes through separate electrical circuits from a common supply with the phase difference therebetween. A first gas and a second are injected into the plasma-containing volume between the two electrodes are different positions relative to the substrate. A lower electrode with a lower electrode width that is less than the combined width of the two electrodes is powered from a separately controllable ac power supply at an ac frequency different from that supplied to the two electrodes.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 19, 2013
    Inventors: Stephen E. Savas, Carl Galewski, Hood Chatham, Sai Mantripragada, Allan Wiesnoski, Sooyun Joh
  • Publication number: 20130334454
    Abstract: The present invention relates to the use of printable inks for the formation of Al2O3 coatings or mixed Al2O3 hybrid layers, and to a corresponding process for the formation thereof.
    Type: Application
    Filed: February 9, 2012
    Publication date: December 19, 2013
    Applicant: MERCK PATENT GMBH
    Inventors: Ingo Koehler, Oliver Doll, Werner Stockum, Sebastian Barth
  • Patent number: 8610182
    Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: December 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
  • Patent number: 8609551
    Abstract: To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the substrate is accommodated; changing the specific element-containing layer into a nitride layer, by activating and supplying gas containing nitrogen into the processing container; and changing the nitride layer into an oxide layer or an oxynitride layer, by activating and supplying gas containing oxygen into the processing container; with this cycle set as one cycle and performed for at least one or more times.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: December 17, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Yoshiro Hirose
  • Patent number: 8609552
    Abstract: Embodiments of the invention describe methods for forming fluorocarbon (CF) films for semiconductor devices. According to one embodiment, the method includes providing a substrate, depositing a CF film on the substrate, generating, in the absence of a plasma, a treatment gas containing a gaseous specie having a molecular dipole, and treating the CF film with the treatment gas containing the gaseous specie having the molecular dipole to reduce the number of dangling bonds in the CF film. According to some embodiments, the method further includes depositing a second CF film on the treated CF film. According to some embodiments, the CF films may be deposited using a microwave plasma source containing a radial line slot antenna (RLSA).
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: December 17, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Yoshiyuki Kikuchi
  • Publication number: 20130330933
    Abstract: A method of forming a dielectric film having Si—C bonds and/or Si—N bonds on a semiconductor substrate by cyclic deposition, includes: (i) conducting one or more cycles of cyclic deposition in a reaction space wherein a semiconductor substrate is placed, using a Si-containing precursor and a reactant gas; and (ii) before or after step (i), applying a pulse of RF power to the reaction space while supplying a rare gas and a treatment gas without supplying a Si-containing precursor, whereby a dielectric film having Si—C bonds and/or Si—N bonds is formed on the semiconductor substrate.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Applicant: ASM IP HOLDING B.V.
    Inventors: Atsuki Fukazawa, Takahiro Oka
  • Publication number: 20130330934
    Abstract: A method of forming a thin film poly silicon layer includes following steps. Firstly, a substrate is provided. The substrate has a first surface. A heating treatment is then performed. A thin film poly silicon layer is then directly formed on the first surface of the substrate by a silicon thin film deposition process.
    Type: Application
    Filed: June 6, 2013
    Publication date: December 12, 2013
    Inventors: Hieng-Hsiung Huang, Wen-Chun Wang, Heng-Yi Chang, Chin-Chang Liu
  • Publication number: 20130323935
    Abstract: A method of forming a thin film on a surface of target objects in a vacuum-evacuable processing chamber by using a source gas and a reaction gas includes: forming a mixed gas by mixing the source gas and an inert gas in a gas reservoir tank, and supplying the mixed gas and the reaction gas into the processing chamber.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 5, 2013
    Inventors: Keisuke SUZUKI, Kentaro KADONAGA, Volker HEMEL, Bernhard ZOBEL
  • Publication number: 20130323923
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Fabian Koehler, Sergej Mutas, Dina Triyoso, Itasham Hussain
  • Publication number: 20130323921
    Abstract: In one embodiment, a trench shield electrode layer is separated from a trench gate electrode by an inter-electrode dielectric layer. A conformal deposited dielectric layer is formed as part of a gate dielectric structure and further isolates the trench shield electrode from the trench gate electrode. The conformal deposited dielectric layer is formed using an improved high temperature oxide (HTO) low pressure chemical vapor deposition (LPCVD) process.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Inventors: Peter A. Burke, Eric J. Ameele
  • Patent number: 8598049
    Abstract: A deposition method capable of forming an oxide film with a predetermined film thickness ratio using a deposition gas with which a small film thickness ratio is obtained and a deposition gas with which a large film thickness ratio is obtained. When forming an oxide film having a larger film thickness on the surface of a substrate than on the bottom surface of the hole so that the film thickness ratio of the oxide film formed on the surface of the substrate to the oxide film formed on the bottom surface of the hole becomes a predetermined ratio, plasma is generated from a gas mixture including tetraethoxysilane and oxygen to form an oxide film and then plasma is generated from a gas mixture including silane and nitrous oxide.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: December 3, 2013
    Assignee: SecureView LLC
    Inventors: Masayasu Hatashita, Akimitsu Oishi, Shoichi Murakami
  • Patent number: 8598048
    Abstract: An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: December 3, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth Robert Rhyner, Peter R. Harper
  • Publication number: 20130313711
    Abstract: In a semiconductor device where a metal circuit layer is disposed over a main planar surface of an insulating substrate, a semiconductor chip is connected by way of a solder over the metal circuit layer, and a metal wiring is connected over the metal circuit layer, in which a solder flow prevention area comprising a linear oxide material is formed between the semiconductor chip and the ultrasonic metal bonding region over the metal circuit layer.
    Type: Application
    Filed: May 15, 2013
    Publication date: November 28, 2013
    Applicant: Hitachi, Ltd.
    Inventors: Yukihiro KUMAGAI, Michiaki HIYOSHI
  • Patent number: 8592327
    Abstract: A method for protecting an exposed low-k surface is described. The method includes receiving a substrate having a mask layer and a low-k layer formed thereon, wherein a pattern formed in the mask layer using a lithographic process has been transferred to the low-k layer using an etching process to form a structural feature therein. Additionally, the method includes forming a SiOCl-containing layer on exposed surfaces of the mask layer and the low-k layer, and anisotropically removing the SiOCl-containing layer from a top surface of the mask layer and a bottom surface of the structural feature in the low-k layer, while retaining a remaining portion of the SiOCl-containing layer on sidewall surfaces of the structural feature. The method further includes performing an ashing process to remove the mask layer, and thereafter, selectively removing the remaining portion of the SiOCl-containing layer from the sidewall surfaces of the structural feature.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: November 26, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Kaushik Arun Kumar
  • Patent number: 8592261
    Abstract: A semiconductor device may be designed in the following manner. A stacked layer of a silicon oxide film and an organic film is provided over a substrate, deuterated water is contained in the organic film, and then a conductive film is formed in contact with the organic film. Next, an inert conductive material that does not easily generate a deuterium ion or a deuterium molecule is selected by measuring the amount of deuterium that exists in the silicon oxide film.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kaoru Hatano, Satoshi Seo
  • Patent number: 8592326
    Abstract: In a method for fabricating an inter dielectric layer in semiconductor device, a primary liner HDP oxide layer is formed by supplying a high density plasma (HDP) deposition source to a bit line stack formed on a semiconductor substrate. A high density plasma (HDP) deposition source is supplied to the bit line stack to form a primary liner HDP oxide layer. The primary liner HDP oxide layer is etched to a predetermined depth to form a secondary liner HDP oxide layer. An interlayer dielectric layer is formed to fill the areas defined by the bit line stack where the secondary liner HDP oxide layer is located.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: November 26, 2013
    Assignee: SK hynix Inc.
    Inventor: Byung Soo Eun
  • Patent number: 8586487
    Abstract: Methods and apparatus for forming conformal silicon nitride films at low temperatures on a substrate are provided. The methods of forming a silicon nitride layer include performing a deposition cycle including flowing a processing gas mixture into a processing chamber having a substrate therein, wherein the processing gas mixture comprises precursor gas molecules having labile silicon to nitrogen, silicon to carbon, or nitrogen to carbon bonds, activating the precursor gas at a temperature between about 20° C. to about 480° C. by preferentially breaking labile bonds to provide one or more reaction sites along a precursor gas molecule, forming a precursor material layer on the substrate, wherein the activated precursor gas molecules bond with a surface on the substrate at the one or more reaction sites, and performing a plasma treatment process on the precursor material layer to form a conformal silicon nitride layer.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 19, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Victor Nguyen, Mihaela Balseanu, Li-Qun Xia, Derek R. Witty
  • Publication number: 20130302997
    Abstract: Processes for preparation of an epitaxial graphene surface to make it suitable for deposition of high-? oxide-based dielectric compounds such as Al2O3, HfO2, TaO5, or TiO2 are provided. A first process combines ex situ wet chemistry conditioning of an epitaxially grown graphene sample with an in situ pulsing sequence in the ALD reactor. A second process combines ex situ dry chemistry conditioning of the epitaxially grown graphene sample with the in situ pulsing sequence.
    Type: Application
    Filed: July 1, 2013
    Publication date: November 14, 2013
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Nelson Garces, Virginia D. Wheeler, David Kurt Gaskill, Charles R. Eddy, JR., Glenn G. Jernigan
  • Publication number: 20130299912
    Abstract: A semiconductor device having high-k gate insulation films and a method of fabricating the semiconductor device are provided. The semiconductor device includes a first gate insulation film on a substrate and the first gate insulation film includes a material selected from the group consisting of HfO2, ZrO2, Ta2O5, TiO2, SrTiO3 and (Ba,Sr)TiO3, and lanthanum (La). Additionally, the semiconductor device includes a first barrier film on the first gate insulation film, a first gate electrode on the first barrier film, and n-type source/drain regions in the substrate at both sides of the first gate electrode.
    Type: Application
    Filed: March 15, 2013
    Publication date: November 14, 2013
    Inventors: Ju-Youn Kim, Young-Hun Kim
  • Patent number: 8580697
    Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: November 12, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
  • Patent number: 8580699
    Abstract: Catalyzed atomic layer deposition from a reduced number of precursors is described. A deposition precursor contains silicon, oxygen and a catalytic ligand. A hydroxyl-terminated substrate is exposed to the deposition precursor to form a silicon bridge bond between two surface-bound oxygens. The surface-bound oxygens were part of two surface-bound hydroxyl groups and the adsorption of the deposition precursor liberates the hydrogens. The silicon atom is also chemically-bound to one or two additional oxygen atoms which were already chemically-bound to the silicon within a same deposition precursor molecule. At least one of the additional oxygen atoms is further chemically-bound to the catalytic ligand either directly or by way of a hydrocarbon chain. Further exposure of the substrate to moisture (H2O) results in displacement of the additional oxygen which are replaced by hydroxyl groups from the moisture. The surface is again hydroxyl-terminated and the process may be repeated.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: November 12, 2013
    Assignee: Applied Materials, Inc.
    Inventor: Abhijit Basu Mallick
  • Publication number: 20130295776
    Abstract: Methods for recovery of precursor vapor from a gas and precursor vapor mixture used in a deposition process. The gas and precursor vapor mixture is passed through a multitude of heat transfer surfaces in a heat conducting housing causing the precursor vapor to condense. The precursor vapor in liquid form is then collected after condensation.
    Type: Application
    Filed: May 2, 2013
    Publication date: November 7, 2013
    Applicant: MSP Corporation
    Inventors: Benjamin Y.H. Liu, Thuc M. Dinh, Yamin Ma
  • Patent number: 8575037
    Abstract: Embodiments show a method for fabricating a cavity structure, a semiconductor structure, a cavity structure for a semiconductor device and a semiconductor microphone fabricated by the same. In some embodiments the method for fabricating a cavity structure comprises providing a first layer, depositing a carbon layer on the first layer, covering at least partially the carbon layer with a second layer to define the cavity structure, removing by means of dry etching the carbon layer between the first and second layer so that the cavity structure is formed.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: November 5, 2013
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Friza, Thomas Grille, Klaus Muemmler, Guenter Zieger, Carsten Ahrens
  • Publication number: 20130288482
    Abstract: In a method of forming a pattern, a photoresist pattern is formed on a substrate including an etching target layer. A surface treatment is performed on the photoresist pattern to form a guide pattern having a higher heat-resistance than the photoresist pattern. A material layer including a block copolymer including at least two polymer blocks is coated on a portion of the substrate exposed by the guide pattern. A micro-phase separation is performed on the material layer to form a minute pattern layer including different polymer blocks arranged alternately. At least one polymer block is removed from the minute pattern layer to form a minute pattern mask. The etching target layer is etched by using the minute pattern mask to form a pattern. Minute patterns may be formed utilizing a less complex process that those employed during conventional processes of forming a minute pattern.
    Type: Application
    Filed: September 28, 2012
    Publication date: October 31, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Woo Nam, Kyoung-Seon Kim, Eun-Sung Kim, Chul-Ho Shin, Shi-Yong Yi
  • Publication number: 20130288485
    Abstract: A method of forming a dielectric layer is described. The method first deposits an initially-flowable layer on a substrate. The initially-flowable layer is then densified by exposing the substrate to a high-density plasma (HDP). Essentially no additional material is deposited on the initially-flowable layer, in embodiments, but the impact of the accelerated ionic species serves to condense the layer and increase the etch tolerance of the processed layer.
    Type: Application
    Filed: March 11, 2013
    Publication date: October 31, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Jingmei Liang, Sukwon Hong, Jun Tae Choi
  • Patent number: 8569162
    Abstract: A conductive bump structure is formed on a substrate having a plurality of bonding pads and a first insulating layer thereon. The first insulating layer has a plurality of openings formed therein for exposing the bonding pads and a conductive post is formed on the bonding pads exposed through the openings. Therein, a gap is formed between the conductive post and the wall of the opening such that no contact occurs between the conductive post and the first insulating layer, thereby preventing delamination of the conductive bump structure caused by stresses concentrating on an interface of different materials as in the prior art.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: October 29, 2013
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Feng-Lung Chien, Yi-Hung Lin, Yi-Hsin Chen
  • Patent number: 8569183
    Abstract: Semiconductor devices and methods for making such devices are described. The semiconductor devices contain dielectric layers that have been deposited and/or flowed by the application of microwave energy (“MW dielectric layers”). The dielectric layers can be made by providing a substrate in a reaction chamber, flowing a precursor gas mixture (containing atoms that react to form a dielectric material) in the reaction chamber, and then subjecting the gas mixture to microwave energy at a frequency and power density sufficient to cause the atoms of the precursor gas mixture to react and deposit to form a dielectric layer on the substrate. As well, the devices can be made by applying microwave energy to an already-deposited dielectric film at a frequency and power density sufficient to cause the atoms of the deposited dielectric material to flow.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: October 29, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Robert J. Purtell
  • Publication number: 20130280919
    Abstract: An oxide film is formed, having a specific film thickness on a substrate by alternately repeating: forming a specific element-containing layer on the substrate by supplying a source gas containing a specific element, to the substrate housed in a processing chamber and heated to a first temperature; and changing the specific element-containing layer formed on the substrate, to an oxide layer by supplying a reactive species containing oxygen to the substrate heated to the first temperature in the processing chamber under a pressure of less than atmospheric pressure, the reactive species being generated by causing a reaction between an oxygen-containing gas and a hydrogen-containing gas in a pre-reaction chamber under a pressure of less than atmospheric pressure and heated to a second temperature higher than the first temperature.
    Type: Application
    Filed: November 8, 2011
    Publication date: October 24, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kazuhiro Yuasa, Ryuji Yamamoto
  • Publication number: 20130280913
    Abstract: There is provided a composition for forming a resist underlayer film having heat resistance for use in a lithography process in semiconductor device production. A composition for forming a resist underlayer film, comprising a polymer that contains a unit structure of formula (1) and a unit structure of formula (2) in a proportion of 3 to 97:97 to 3 in molar ratio: A method for producing a semiconductor device, including the steps of: forming an underlayer film using the composition for forming a resist underlayer film on a semiconductor substrate; forming a hard mask on the underlayer film; further forming a resist film on the hard mask; forming a patterned resist film and developing; etching the hard mask according to the patterned resist film; etching the underlayer film according to the patterned hard mask; and processing the semiconductor substrate according to the patterned underlayer film.
    Type: Application
    Filed: December 5, 2011
    Publication date: October 24, 2013
    Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Tetsuya Shinjo, Hiroaki Okuyama, Keisuke Hashimoto, Yasunobu Someya, Ryo Karasawa, Masakazu Kato
  • Patent number: 8563443
    Abstract: A method of forming a dielectric film having at least Si—N, Si—C, or Si—B bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: supplying a precursor in a pulse to adsorb the precursor on a surface of a substrate; supplying a reactant gas in a pulse over the surface without overlapping the supply of the precursor; reacting the precursor and the reactant gas on the surface; and repeating the above steps to form a dielectric film having at least Si—N, Si—C, or Si—B bonds on the substrate. The precursor has at least one Si—C or Si—N bond, at least one hydrocarbon, and at least two halogens attached to silicon in its molecule.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: October 22, 2013
    Assignee: ASM Japan K.K.
    Inventor: Atsuki Fukazawa