Abstract: A system including first and second filters and an adaptation engine. The first filter includes first taps that receive first coefficients and filters a digital signal to generate a first filtered signal. One of the first coefficients is constrained, such that the one of the first coefficients are not updated and phase and gain errors are introduced. The second filter includes second taps that receive second coefficients and filters the first filtered signal to generate a second filtered signal. The second coefficients include first and second coefficients. The adaptation engine, based on the one of the first coefficients, updates: the first coefficient to set a phase of the second filter; and the second coefficient to set a gain of the second filter. The phase of the second filter corresponds to a change in the phase error. The gain of the second filter corresponds to a change in the gain error.
Abstract: A vehicle audio system includes: a tune knob configured to select a frequency of a desired radio broadcast; a microcomputer configured to detect a broadcast frequency input through the tune knob and to determine an optimal sampling frequency of a full digital amplifier based on the detected broadcast frequency; a tuner configured to receive only a broadcast signal corresponding to the frequency selected through the tune knob; and the full digital amplifier configured to generate a digital signal by sampling the broadcast signal received by the tuner at the optimal sampling frequency determined by the microcomputer and to amplify and output the generated digital signal.
Abstract: Systems and methods are provided for an adjustable filter engine. In particular, an electronic system is provided that can include a focus module, memory, and control circuitry. In some embodiments, the focus module can include an adjustable filter engine and a motor. By using the adjustable filter engine to generate a filter with a large number of filter coefficients, the control circuitry can accommodate a variety of system characteristics. For example, by generating a set of cumulative coefficients and re-arranging the order of the cumulative coefficients, the control circuitry can reduce the bit-width requirements of the adjustable filter engine hardware. For instance, the control circuitry can reduce the number of multipliers required to perform a convolution between an updated filter and one or more input signals. In some embodiments, the updated filter can be generated to reduce oscillations of the motor movement due to a new position request.
Abstract: A reconfigurable filter bank system that has an asymmetrical tree structure with multiple stages to generate multiband outputs. Each stage may include cascaded low-pass filters (LPFs), cascaded high-pass filters (HPFs) and/or all-pass filter(s) (APF(s)) having identical phase responses. As the cascaded LPFs, cascaded HPFs and APF(s) have identical phase responses, each frequency band of the multiband output may have an identical phase shift such that the frequency bands are in-phase and can be added together. The multiband outputs of the reconfigurable filter bank may have near-perfect reconstruction (e.g., small number of cross-band ripples) and therefore only minor distortion. In addition, the number of frequency bands and corresponding non-uniform bandwidths (e.g., frequency ranges) may be user-adjustable and/or reconfigurable during device operation. Further, the reconfigurable filter bank may have reduced computational complexity and/or latency.
Type:
Grant
Filed:
March 28, 2016
Date of Patent:
March 28, 2017
Assignee:
AMAZON TECHNOLOGIES, INC.
Inventors:
Jun Yang, Colin Randall McEnroe, Jian Guo
Abstract: Methods and apparatuses are provided for graphically displaying the noise level on each WLAN channel, along with the arrangement of other (neighboring) wireless host devices on each channel with their respective signal strengths as a distance indicator. As a result, collected information may be gathered and displayed intuitively to allow a user to quickly assess the environment and manually configure the wireless host device. In addition, methods and apparatuses are provided for suggesting to a user or automatically selecting a wireless host device configuration based on the noise level on each WLAN channel and the arrangement of other wireless host devices on each channel with consideration of their respective signal strengths. As a result, an optimal configuration for a deployed wireless host device may be determined and consistently suggested or automatically configured.
Abstract: An embodiment of the invention relates to a method of phase detection in a receiver circuit with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap of the decision feedback equalizer is separated from the feedback of the remaining plurality of taps. The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance.
Abstract: A discrete time (DT) lowpass filter having various advantages is described. In an exemplary design, the DT lowpass filter includes a decimating DT filter (which may include a passive DT FIR filter and/or a passive DT IIR filter) and an active DT filter. The decimating DT filter receives a first DT signal at a first sample rate, filters and decimates the first DT signal by a factor of N, and provides a second DT signal at a second sample rate lower than the first sample rate. N may be greater than one. The active DT filter filters the second DT signal and provides a third DT signal at the second sample rate. A sampler samples a continuous time signal and provides the first DT signal. The sampler may further double the voltage of the first DT signal relative to the voltage of the continuous time signal.
Type:
Grant
Filed:
August 14, 2009
Date of Patent:
February 21, 2017
Assignee:
QUALCOMM Incorporated
Inventors:
Russell John Fagg, Joseph Patrick Burke
Abstract: A data normalization system is described herein that represents multiple data types that are common within database systems in a normalized form that can be processed uniformly to achieve faster processing of data on superscalar CPU architectures. The data normalization system includes changes to internal data representations of a database system as well as functional processing changes that leverage normalized internal data representations for a high density of independently executable CPU instructions. Because most data in a database is small, a majority of data can be represented by the normalized format. Thus, the data normalization system allows for fast superscalar processing in a database system in a variety of common cases, while maintaining compatibility with existing data sets.
Type:
Grant
Filed:
January 13, 2014
Date of Patent:
January 17, 2017
Assignee:
Microsoft Technology Licensing, LLC
Inventors:
Aleksandras Surna, Erik Ismert, Srikumar Rangarajan, Nimish S. Khanolkar
Abstract: The disclosed embodiment may be a parametric equalization hardware that is coupled to computer readable memory software configured to present a command interface to a user and control the equalization hardware to manipulate the frequency, Q, and gain. Additionally, software is configured to simultaneously vary the Q and gain of an equalization curve between two preset values defined by: (1) a high gain and narrow Q (“Fire”); and (2) low gain and wide Q (“Water”).
Abstract: A system and method for representing quasi-periodic (“qp”) waveforms, for example, representing a plurality of limited decompositions of the qp waveform. Each decomposition includes a first and second amplitude value and at least one time value. In some embodiments, each of the decompositions is phase adjusted such that the arithmetic sum of the plurality of limited decompositions reconstructs the qp waveform. Data-structure attributes are created and used to reconstruct the qp waveform. Features of the qp wave are tracked using pattern-ecognition techniques. The fundamental rate of the signal (e.g., heartbeat) can vary widely, for example by a factor of 2-3 or more from the lowest to highest frequency. To get quarter-phase representations of a component (e.g., lowest frequency “rate” component) that varies over time (by a factor of two to three) many overlapping filters use bandpass and overlap parameters that allow tracking the component's frequency version on changing quarter-phase basis.
Abstract: A high-order syndrome calculator includes a serial-to-parallel converter configured to convert serial bit sequences received from a transmitter to a parallel multi-stream, an exclusive OR (XOR) operator configured to perform an XOR operation on bit values of the multi-stream, a zero interpolator configured to insert zero values between the bits on which the XOR operation is performed, and a linear feedback shift register configured to calculate a high-order syndrome value based on a coefficient of a remainder obtained by dividing, by a primitive polynomial, a polynomial generated from the multi-stream in which the zero values are inserted.
Type:
Grant
Filed:
September 29, 2014
Date of Patent:
October 11, 2016
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Chang Soon Park, Hyo Sun Hwang, Young Jun Hong
Abstract: Disclosed are a power adjustment method and an apparatus based on low delay power detection before digital pre-distortion. The method comprises the following steps: according to pre-configured system carrier information, obtaining effective carrier information containing an effective carrier channel corresponding to each effective carrier; performing sampling on carrier data of each effective carrier channel according to the obtained effective carrier information, and then calculating combination power Pa of effective carriers before digital up conversion or digital peak clipping cancellation according to the sampling; and using the combination power Pa of the effective carriers to perform power adjustment before digital pre-distortion. The present invention moves power calculation ahead of an up conversion module, fully utilizes inherent delay of digital up conversion and a peak clipping module to offset time required for the power calculation, and effectively reduces system delay.
Abstract: Examples of a system and method for adaptively tuning a radio frequency (RF) front-end are generally described herein. In some examples, the frequency of a transmit signal of RF front-end circuitry is swept in at least a part of the RF transmit band. RF power in a receiver is detected as a function of the RF frequency of the transmit signal to determine a location of at least one tunable notch or other band stop element in the frequency domain. Information from the detected RF power is determined as a function of the RF frequency of the transmit signal. The RF front-end circuitry is adjusted to a selected frequency response using the determined information.
Type:
Grant
Filed:
December 17, 2013
Date of Patent:
August 30, 2016
Assignee:
Intel IP Corporation
Inventors:
Poul Olesen, Peter Bundgaard, Mikael Bergholz Knudsen
Abstract: Embodiments of the invention provide a method to detect DSSS preambles in smart utility networks. A DSSS signal is received by a receiver and a digital sequence of samples is formed. A difference value is calculated between pairs of samples in the digital sequence of samples to form a sequence of differential values. A known preamble differential value sequence is correlated with the sequence of differential values to form a sequence of correlation values. A location of the preamble is located in the digital sequence of samples corresponding to a peak in the sequence of correlation values that exceeds a threshold value.
Abstract: A device includes interface circuitry. The interface circuitry receives first input signals related to measurements of characteristics of electricity passing through a first power line. The device includes filtering circuitry that filters the first input signals to generate filtered data. The device also includes a processor that estimates an oscillation frequency of the filtered data via a time-domain frequency estimation method.
Type:
Grant
Filed:
October 19, 2011
Date of Patent:
May 24, 2016
Assignee:
General Electric Company
Inventors:
Zhiying Zhang, Ilia Voloh, Jorge Eduardo Cardenas Medina
Abstract: A method relates generally to data transmission. In such a method, a peak detector detects a signal peak of an input signal exceeding a threshold amplitude. This detecting includes sampling the input signal at a sampling frequency to provide a sampled signal. The sampling frequency is in a range greater than a bandwidth frequency of a carrier signal used for providing the input signal and less than twice the bandwidth frequency. Samples of the sampled signal proximate to the signal peak are interpolated to provide a reconstructed peak. A cancellation pulse is applied by a cancellation pulse generator to the samples to reduce the signal peak. A version of the input signal is output after application of the cancellation pulse.
Abstract: A method for generating a signal having a defined bandwidth and a desired crest factor is disclosed. The signal is composed of a number of individual sinusoidal signals, each having an amplitude and a frequency. The method includes determining an exponent to be used in a specific exponential function and corresponding to the desired crest factor, the exponent being determined based on an a priori known relationship between crest factor and exponent; calculating a phase value for each sinusoidal signal using the specific exponential function and the previously determined exponent; and superposing the sinusoidal signals to obtain the signal having the desired crest factor, whereby the phases of the individual signals are maintained.
Abstract: A method is disclosed for setting or modifying a threshold voltage in a NAND flash memory, using an optimization method and based on an error, such as stored in a threshold voltage table. In an embodiment, a method is provided to optimize the read voltage on a NAND flash memory in order to minimize the errors on the NAND flash memory in the fewest reads operations as possible. Advantageously, the method of the present disclosure is more reliability as the method minimizes a Raw Bit Error Rate (RBER) on the NAND flash memory. In an embodiment, a NAND controller adjusts an existing cell read threshold voltage for a selected cell, using an iterative optimization method, based on a difference between first and second error rates, or a difference between first and second probabilities, to generate an adjusted cell read threshold voltage.
Abstract: A digital filter having improved attenuation characteristics is disclosed. The disclosed performs upsampling of model filter response by applying a sampling kernel scaled by a sampling constant. The disclosed filter has good attenuation characteristics with small number of taps and pass bands of the digital filter can be changed with simple parameter variation.
Type:
Grant
Filed:
February 28, 2011
Date of Patent:
December 29, 2015
Assignee:
Industry-University Cooperation Foundation Hanyang University
Inventors:
Sang-Won Nam, Kyoung-Jae Kim, Sung-Il Jung
Abstract: A digital filter bank includes a first sample and hold unit, one or more second sample and hold units one or more quantizers and one or more polyphase component filters. In another aspect, a digital filter bank includes a first sample and hold unit, a discrete time commutator and one or more polyphase component filters. In another aspect, a method for digitally filtering a signal includes sampling an input signal at a first frequency, sampling and holding the first sampled signal at a second frequency, quantizing the one or more second sampled signals to output channelized signals, and filtering the one or more quantized signals and outputting one or more filtered signals using one or more polyphase component filters.
Abstract: A transmission and reception apparatus, system for transmitting and receiving signals, and method for transmitting and receiving signals are disclosed. In one example, a transmitting part produces an output signal including a first digitally modulated signal. A receiving part includes a mixer circuit and receives an input signal including a second digitally modulated signal. A folding signal may be present as a function of the first digitally modulated signal and a clock signal used to produce the first digitally modulated signal. The mixer circuit performs frequency down conversion on the input signal, and may also be configured to perform a harmonic wave removal function on the input signal that reduces the presence of the folding signal from the input signal. The receiving part may further include a filter circuit that receives the frequency-down-converted input signal from the mixer circuit and selects a predetermined reception signal from the frequency-down-converted input signal.
Abstract: Described herein is a framework to facilitate traffic prediction. In accordance with one aspect, training data including historical traffic information and precipitation data is received. An impulse response function may be determined based on the training data. One or more traffic parameters may be predicted by calculating a weighted linear system model based on the impulse response function.
Abstract: Systems and methods are disclosed for altering character body animations to improve subsequent cloth animations. In particular, based on a character body animation, an extra level of processing is performed, prior to the actual cloth simulation. The extra level of processing removes potential areas of pinching or tangling in input character body simulation data, ensuring that the output of the cloth simulation will be have reduced pinches and tangles.
Type:
Grant
Filed:
October 7, 2010
Date of Patent:
August 25, 2015
Assignees:
SONY CORPORATION, SONY PICTURE TECHNOLOGIES INC.
Abstract: A system and method for adaptive motion filtering to improve subpel motion prediction efficiency of interframe motion compensated video coding is described. The technique uses a codebook approach that is efficient in search complexity to look-up best motion filter set from a pre-calculated codebook of motion filter coefficient set. In some embodiments, the search complexity is further reduced by partitioning the complete codebook into a small base codebook and a larger virtual codebook, such that the main calculations for search only need to be performed on the base codebook.
Type:
Grant
Filed:
May 5, 2014
Date of Patent:
August 4, 2015
Assignee:
Intel Corporation
Inventors:
Atul Puri, Daniel Socek, Chang-Kee Choi
Abstract: A frequency reconfigurable digital filter and an equalizer using the same are disclosed. The digital filter includes a sampling kernel storage section configured to store a sampling kernel for performing upsampling of a model filter response scaled by a sampling constant and generating response of Multi images which are repeatedly formed with a constant period; a complementary conversion section configured to generate response of Multi complementary images repeatedly formed with constant period in frequency domain where the Multi images are not generated, the Multi complimentary images having the same characteristic as the Multi images; and an image response operation section configured to operate response of an image corresponding to a selected band among the Multi complementary images and the Multi images. The filter reconfigures frequency to realize various band pass characteristics only through changing very small number of parameter, and a user may change easily band of the filter.
Type:
Grant
Filed:
February 28, 2011
Date of Patent:
August 4, 2015
Assignee:
Industry-University Cooperation Foundation Hanyang University
Inventors:
Sang-Won Nam, Kyoung-Jae Kim, Sung-II Jung
Abstract: A method and apparatus for a radio base station (200) generates a multicarrier communication signal having a reduced crest factor by processing a block of samples (231) with a peak search window (271) to identify and suppress signal peaks exceeding a power threshold value.
Type:
Grant
Filed:
August 7, 2012
Date of Patent:
August 4, 2015
Assignee:
Freescale Semiconductor, Inc.
Inventors:
Jayakrishnan C. Mundarath, Leo G. Dehner, Jayesh H. Kotecha, Peter Z. Rashev
Abstract: A method and apparatus may be used to generate complex exponentials for either frequency domain or time domain applications by programming input parameter values into a complex exponential vector generator (260) having a frequency generator stage (281) and a vector phase accumulator stage (282) arranged with a vector element multiplier stage (283) to generate complex exponential phase index values (?0, ?1, . . . ?v?1) that are processed by a complex exponential generator stage (284) to output a plurality of complex exponential values (e.g., ej2??0, ej2??1, . . . ej2??v?1) that may be rearranged by a permutation unit (286) for use by vector data path.
Abstract: A method and system for providing a finite impulse response, FIR, filter in a power amplification system are disclosed. An FIR filter includes a first signal path having a first delay, ?1. The first signal path is configured to receive an output from a power amplifier. A second signal path is in parallel with the first signal path has a second delay, ?2, and a first scalar multiplier, ?1. A third signal path in parallel with the first and second signal paths has a third delay, ?3, and a second scalar multiplier, ?2. The second and third signal paths are configured to receive a sum of the output of the power amplifier and a reference signal. Delays ?1, ?2, and ?3 are integer multiples of a period of time. An output is a sum of a signal from each of the first, second and third signal paths.
Abstract: To provide a mobile communication terminal test device that can generate a signal with amplitude-frequency characteristics or phase-frequency characteristics which are changed over time. A mobile communication terminal test device 10 includes a data generation unit 12 that generates a bit stream, a sub-carrier generation unit 31 that receives bit stream data and performs, for example, predetermined encoding, symbol mapping, or sub-carrier mapping to convert the received data into a plurality of sub-carriers based on an OFDM modulation system, a frequency characteristic storage unit 13 that stores table data for predetermined amplitude-frequency characteristics and phase-frequency characteristics, and a frequency characteristic calculation unit 32 that sets the amplitude and phase of each sub-carrier input from the sub-carrier generation unit 31 on the basis of the table data.
Abstract: A receiving circuit, use, and method for receiving an encoded and modulated radio signal is provided. The circuit comprise a demodulator and a digital filter connected downstream of the demodulator for moving averaging. The filter has at least two FIFO registers and subtractors. Whereby for subtracting an output value of the FIFO register from an input value of the FIFO register a subtractor is connected to each FIFO register. Wherein the filter has a weighting unit, which is connected downstream of each FIFO register, and wherein the filter has an integrator, which is connected downstream of the subtractors for integration.
Abstract: A method of frequency-domain filtering is provided that includes a plurality of filters, the plurality of filters including at least one constrained filter(s) W=I, I and at least one unconstrained filter(s) W=1,K? The method includes cascading the W k=i,K unconstrained filter(s). A single constraint window C is applied to the cascaded W=i,K unconstrained filter(s). The W=1,I constrained filter(s) are cascaded with the constrained cascaded Wk=1,K unconstrained filter(s) to form a resulting filter Wll=C(W 1{circle around (x)} . . . {circle around (x)} W){circle around (x)} W . . . W. The frequency domain representation of the single constraint window C may be based, at least in part, on a time domain representation of a single constraint window C that has been circularly shifted such that the frequency domain representation of the constraint window matches a property of the frequency domain representation of the cascaded W=1,K unconstrained filters.
Abstract: In this application, a set of orthogonal functions is introduced whose power spectral densities are all rectangular shape. To find the orthogonal function set, it was considered that their spectrums (Fourier transforms of the functions) are either real-valued or imaginary-valued, which are corresponding to even and odd real-valued time domain signals, respectively. The time domain functions are all considered real-valued because they are actually physical signals. The shape of the power spectral densities of the signals are rectangular thus, the Haar orthogonal function set can be employed in the frequency domain to decompose them to several orthogonal functions. Based on the inverse Fourier transform of the Haar orthogonal functions, the time domain functions with rectangular power spectral densities can be determined. This is equivalent to finding the time-domain functions by taking the inverse Fourier transform of the frequency domain Walsh functions.
Type:
Grant
Filed:
March 15, 2010
Date of Patent:
May 19, 2015
Assignee:
SAN DIEGO STATE UNIVERSITY RESEARCH FOUNDATION
Abstract: The present invention addresses the problem of reducing a circuit scale without causing a reduction in processing efficiency. This multi-stage filter processing method measures, at each stage, either the number of input data or the number of intermediate data that is generated by filter calculation processing during the stages before the final stage is reached. Coefficient data regulating for each stage the number of data sufficient to perform the filter calculation processing is held. Input data or the intermediate data that is generated in a current stage is held in a memory until the number of data reaches the number of data sufficient to perform the filter calculation processing in the current stage, on the basis of the coefficient data. When the number of data has reached the number of data sufficient to perform the filter calculation processing, the filter calculation processing for the current stage is performed on the input data or the intermediate data that was held.
Abstract: A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts on the data collection unit. Some of the data collection unit contacts are for communicating physiological data from the subject interface to the data collection unit. Some of the contacts are for powering the data collection unit upon the subject interface being connected to the data collection unit and for powering down the data collection unit upon the subject interface being disconnected from the data collection unit.
Abstract: Techniques are provided which may be implemented using various methods and/or apparatuses in a device comprising a receiver to scan a spectral band of a received signal comprising a desired signal contribution to determine whether signal data associated with at least a sub-band of the spectral band further comprises at least one undesired signal contribution. In response to determining that the signal data comprises at least one undesired signal contribution, the mobile station may initiate at least one notch filter to affect the undesired signal contribution in subsequent signal data associated with the received signal.
Type:
Grant
Filed:
February 10, 2012
Date of Patent:
April 14, 2015
Assignee:
QUALCOMM Incorporated
Inventors:
Jie Wu, Emilija M. Simic, Timothy Paul Pals, Duong A. Hoang
Abstract: Provided is a system for generating coefficient values. The system may include a base function generator and a series of accumulators including a leading and a last accumulator. In the series of accumulators, the data output of each accumulator, except the last, may be coupled to the data input of a successive adjacent accumulator. The base function generator may be configured to output, to the leading accumulator, a series of data values that may correspond to a base function that is a specified order derivative of a filter function. Each accumulator may be configured to: add a data value currently at its data input to a currently stored data value to produce an updated data value that may correspond to a respective value of a specified order integral of the base function; store the updated data value in the accumulator; and output the updated data value at its data output.
Abstract: Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the taps such that a magnitude of a Nyquist response of the digital finite impulse response filter remains within a constraint range.
Abstract: Systems and methods for latency compensation are disclosed. In one embodiment, a computer-based system for latency compensation in a dynamic system comprises a processor and logic instructions stored in a tangible computer-readable medium coupled to the processor which, when executed by the processor, configure the processor to receive at least first parameter data from a first sensor and second parameter data from a second sensor, direct the at least first parameter data and the second parameter data into a combining filter, receive additional parameter data about the dynamic system from at least one additional sensor, construct a model of latency effects on the first parameter data and the second parameter data, and use the model of latency effects to compensate for latency-based differences in the first parameter data and the second parameter data.
Abstract: New hybrid filters are presented based on time and transform domain structures. The hybrid filters have a combined benefit from the advantages obtained by the time and transform domain structures. The overall efficiencies are drawn from combining the pre- and post-processing of the time domain and block based transform domain structures. Further improvements are obtained by interchanging block construction and transforms with linear operations in the pre- and post-processors. The hybrid structures apply to single input, single output, multiple input, and multiple output structures. For the multi input and multi output structures further improvements are obtained by having common processing blocks for the input(s) and common processing blocks for the output(s). They hybrid filters are also efficient in topologies where filter outputs are combined via linear operation(s) generating combined results.
Abstract: A signal filter and accompanying methods. In one embodiment, the filter includes a first mechanism for receiving a first signal. A second mechanism employs one or more modified representations of the first signal to cancel one or more frequency components of the first signal, yielding an output signal in response thereto. In a more specific embodiment, the first mechanism includes a splitter for receiving the first signal and splitting the first signal onto a first path and a second path. The second mechanism further includes one or more delay modules and one or more phase shifters in the first path and/or the second path. One or more controllable amplifiers are optionally included in the first path and/or the second path. The one or more delay modules, phase shifters, or amplifiers are responsive to one or more control signals from a controller. The controller is adapted to modify behavior of the second mechanism so that the filter is characterized by a desired frequency response.
Abstract: A symmetric filter arithmetic apparatus includes a first data shuffling unit which reads a first data string that is a plurality of consecutive pieces of data from a register file and extract, from the first data string, a left-side data string that is a plurality of consecutive pieces of data to be multiplied by a left-side filter coefficient that is a filter coefficient on a left side of a center of the coefficients, and a second data shuffling unit which reads a second data string that is a plurality of consecutive pieces of data from the register file and extract, from the second data string, a right-side data string that is a plurality of consecutive pieces of data to be multiplied by a right-side filter coefficient that is a filter coefficient on a right side of the center and is the same value as the left-side filter coefficient.
Abstract: A power supply control apparatus includes a first adder configured to generate a difference signal based on a target value and a feedback signal; a compensator having a first transfer function Wc(z) and configured to generate a control signal based on the difference signal; a control target having a second transfer function Wp(z) and configured to output an output signal generated in response to the control signal; a disturbance canceller having a third transfer function {1+Wc(z)·Wp(z)}/{Wc(z)·Wp(z)} and configured to generate a disturbance cancelling signal based on the output signal corresponding to a control amount y; a second adder configured to generate a differential disturbance signal based on an output of the first adder and the disturbance cancelling signal; and a filter circuit which generates the feedback signal based on the differential disturbance signal.
Abstract: A data signal delay system may include a delay unit and a phase interpolation unit. The delay unit may include multiple delay elements that each have an element delay. The delay unit may be configured to generate multiple delay signals by delaying a data signal using the delay elements such that each of the delay signals has a different delay. The phase interpolation unit may be coupled to the delay unit and may include a mixer. The mixer may be configured to mix two of the delay signals based on mixing weights selected for the two delay signals to generate a final delayed data signal that is the data signal delayed by a final delay. The mixing weights may be selected based on the final delay.
Abstract: Systems and methods for sample rate tracking are provided. An example method includes computing an actual latency associated with an output sample from an output sample stream. The actual latency is calculated using a phase and a phase increment (conversion rate ratio). A measured latency is determined using an internal clock using a presentation time of the output sample, or an input sample from an input sample stream, or both. The measured latency is compared to the actual latency to generate a latency error. A successive phase increment can be determined based on the latency error by using a low-pass or adaptive filter to adjust the latency error.
Type:
Grant
Filed:
March 12, 2014
Date of Patent:
February 24, 2015
Assignee:
Audience, Inc.
Inventors:
David P. Rossum, Sneha Date, Xiaojun Chen
Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.
Type:
Application
Filed:
February 15, 2013
Publication date:
February 5, 2015
Inventors:
Jerald Yoo, Anantha P. Chandrakasan, Long Yan, Dina Reda El-Damak, Ali Hossam Shoeb, Muhammad Awais Bin Altaf
Abstract: A circuit that provides a rotating coefficient FIR filter with all necessary coefficient sets present at the same time, without the need for delay elements or devices providing for adjustable impedances is described. An input signal is sampled in round robin fashion by a plurality of sample and hold devices. The outputs of the sample and hold devices are connected to sets of impedance devices. Each set of impedance devices implements the coefficients of the desired frequency response of the filter. The impedance devices in each set are connected to the sample and hold devices in a different order from each other set, so that each set of impedance devices will produce the desired frequency response when a different one of the sampling circuits contains a new sample of the input signal. Switches connect the sets of impedance devices to an output, only one switch being closed at a time to provide the output signal.
Abstract: A chromatic dispersion estimator for estimating a chromatic dispersion in an input signal block comprises a transformer for transforming the input signal block into a transformed signal block in frequency domain, a chromatic dispersion compensator for compensating a certain chromatic dispersion in the transformed signal block to obtain a compensated transformed signal block, an inverse transformer for inversely transforming the compensated transformed signal block into time domain to obtain an output signal, an adaptive filter for filtering the output signal to obtain a filtered signal, and a determiner for determining upon the basis of the filtered signal whether the certain chromatic dispersion corresponds to the chromatic dispersion in the input signal block.
Abstract: Disclosed herein is a reception apparatus, including a first equalization section, a second equalization section, and an arithmetic operation section. The first equalization section is adapted to carry out equalization of a signal which represents data transmitted by a transmission method which uses a single carrier. The second equalization section is adapted to carry out equalization of a signal which represents data transmitted by a transmission method which uses multi carriers. The arithmetic operation section is adapted to carry out arithmetic operation for determining information to be used for the equalization by the first equalization section and arithmetic operation for determining information to be used for the equalization by the second equalization section.
Abstract: A digital filter circuit includes an FFT circuit (13) that transforms a complex signal in a time domain into a signal in a frequency domain, an I/Q separation circuit (15) that separates the signal in the frequency domain into a signal in a first frequency domain that corresponds to the real part of the complex signal in the time domain, and a signal in a second frequency domain that corresponds to the imaginary part of the complex signal in the time domain, a filter circuit (21) that performs filter processing on the signal in the first frequency domain, a filter circuit (22) that performs filter processing on the signal in the second frequency domain, an I/Q combination circuit (16) that combines an output from the filter circuit (21) and an output from the filter circuit (22) to generate a signal in a third frequency domain, a filter circuit (23) that performs filter processing on the signal in the third frequency domain, and an IFFT circuit (14) that transforms an output signal from the filter circuit (23