Abstract: A digital all-pass filter has an input port leading to an input sum block and a first feed forward path. Within the first feed forward path is a multiplier. The filter also has an output port coupled to an output sum block that receives a signal from the first feed forward path. A first feedback path is also provided from the output port to the input sum block. The first feedback path includes a multiplier therein. Nested within this structure is a first order all-pass filter having a feed forward path including a forward path delay and forward path that is delayed and a feedback path absent a separate delay element and beginning after the forward path delay element.

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract: Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.

Abstract: A filter engine that performs filtering operations on an input data stream comprising blocks of data. The filter engine includes a first memory element, a second memory element, a first shift register, a second shift register and a processor. The first and second memory elements store blocks of data to be processed. The first shift register receives and stores blocks of data from the first memory element. The second shift register receives and stores blocks of data from the second memory element. The first and second shift registers are adapted to selectively shift their contents by a predetermined number of bits corresponding to the size of a data element, such as a pixel. The processor receives blocks of data from the first and second shift registers and simultaneously performs filtering operations on blocks of data from the first and second shift registers.

Abstract: In one embodiment, a circuit-based apparatus that operates on an input data stream includes delay-line circuitry that characterizes the input data stream, modified over time. A plurality of integrators provide a plurality of integrated signals in response to the delay-line circuitry, and a plurality of weighting amplifiers amplify the plurality of integrated signals by a plurality of respective time-varying weighting factors to provide weighted signals. A signal-combining circuit combines the weighted signals. The circuit-based apparatus also includes a plurality of parallel signal-processing circuit paths that couple the weighted signals to the signal-combining circuit. By combining the weighted signals from the parallel signal-processing circuit paths, the signal-combining circuit provides a signal representative of the input data stream.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: The VEA Detector and Dynamic Range Controller of the invention more accurately measure constant or non-constant, periodic or aperiodic, signals and the use of such measurements to control the upstream and/or downstream processing of program signals, including without limitation audio, video, and power program signals. The invention uses an antilog module acting within the context of a log domain circuit such that the “averaging” at an integrator is linear, not logarithmic. However, since the detection is within the log domain, the dynamic range of the VEA Detector is exponentially larger.

Abstract: A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal.

Abstract: Apparatus and methods for electronic hardware resource management in video processing are provided. A hybrid filter is controllable to apply either Finite Impulse Response (FIR) filtering or Infinite Impulse Response (IIR) filtering for vertical filtering of a video image during a resizing process. A scale factor by which the video image is to be resized in the resizing process is determined, and the hybrid filter is controlled to apply FIR filtering for the vertical filtering where the determined scale factor satisfies a first condition relative to a threshold value ST or to apply IIR filtering for the vertical filtering where the determined scale factor satisfies a second condition relative to the threshold value ST. The first and second conditions are different and exclusive, such that only one type of filtering is applied. This hybrid filtering approach uses each type of filtering to avoid defects of the other.

Abstract: A digital infinite impulse response filter has a plurality of cascaded filter elements, with each filter element defining a pole of the filter and wherein the poles lie inside a unit circle. The filter elements are configured such that the p of the last filter element is a real number. In one embodiment the poles are arranged as complex conjugate pairs. In another embodiment the real part of the output of each filter element is extracted before being passed to the next filter element. This architecture offers improved idle tone with reduced complexity.

Abstract: In one embodiment, a method for signal processing is provided that uses an improved inversion to mitigate the imprecision introduced by fast approximate methods for division. An input signal is received and processed to generate a matrix M. The matrix M is inverted to generate an inverted matrix M?1. Matrix M is inverted by (i) decomposing the matrix M into a plurality of first sub-matrices, (ii) generating, based on the first sub-matrices and without any division operations, numerators for a plurality of second sub-matrices of the inverted matrix M?1, (iii) generating, based on the first sub-matrices and without any division operations, denominators for the second sub-matrices, and (iv) generating the second sub-matrices based on the numerators and denominators. The inverted matrix M?1 is processed to generate an output signal. Accordingly, a reduction in noise level from inaccuracy in division is achieved, and computational complexity is reduced.

Abstract: Certain embodiments of the invention may include systems and methods for implementing a multirate digital interpolating filter. According to an example embodiment of the invention, the method includes sampling symbol data from one sample per symbol to N samples per symbol, wherein sampling includes: convolving the symbol data with a decimated finite impulse response (FIR) aperture impulse response coefficient set, convolving the symbol data with one or more shifted decimated FIR aperture impulse response coefficient sets, and summing the convolution results to produce interpolated bandlimited data.

Abstract: A system and method for filtering a signal comprising: receiving a signal of interest; receiving a signal indicating that a stimulus has been applied; receiving the synchronized stimulus signal and signal of interest; recursively selecting a portion of the signal of interest associated with a stimulus being applied and assign the selected portion of the signal of interest to one of the plurality of buffers; combining all responses in each of said plurality of buffers; transforming the combination of all responses in each buffer to a transform space; comparing the transform components of the buffers to determine a scaling factor; applying the scaling factor to the spectral components of the buffers; performing an inverse transform on the result of combining the buffers to return to the time domain to produce a filtered signal, and outputting the filtered signal received from the processor.

Abstract: A system for correcting infrared (IR) radiances includes an imager for receiving IR radiances and outputting intensity data corresponding to pixels in the imager. Also included is a stray light estimator for receiving the intensity data and estimating stray light in the intensity data. The stray light estimator includes a Bessel filter for low pass filtering the estimated stray light and providing corrected intensity data as an output to a user. The Bessel filter is an n-pole recursive digital filter, which is expressed as a ratio between (a) an (n?1) order polynomial of a complex number and (b) an n order polynomial of a complex number, where n is a positive integer. The Bessel filter includes an infinite response curve, in which the response curve monotonically decreases in amplitude as a function of frequency per pixels.

Abstract: To transmit a multi-carrier signal, a transmitter provides zero symbols for guard subbands, performs OFDM modulation, and filters the resultant time-domain samples with a pulse shaping filter. To transmit a single-carrier signal, the transmitter partitions the single-carrier signal into segments. Each segment contains up to K samples and is padded, if needed, to the length of an OFDM symbol. Each padded segment is transformed from the time domain to the frequency domain to generate a corresponding frequency-domain segment with K symbols. For each frequency-domain segment, the symbols corresponding to the guard subbands are set to zero. Each frequency-domain segment is then transformed from the frequency domain to the time domain to generate a corresponding time-domain segment. A cyclic prefix may or may not be appended to each time-domain segment. Each time-domain segment is filtered with the same pulse shaping filter to generate an output waveform for the single-carrier signal.

Abstract: A noise feedback coding (NFC) system and method that utilizes a simple and relatively inexpensive general structural configuration, but achieves improved flexibility with respect to controlling the shape of coding noise. The NFC system and method utilizes an all-zero noise feedback filter that is configured to approximate the response of a pole-zero noise feedback filter.

Abstract: A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.

Abstract: A digital filter device capable of removing the effect of noise such as chattering from a zero crossing signal is provided. A digital filter device 4 filtering a binary digital signal DIN and outputting a binary digital signal DOUT is provided with a toggle flip-flop 12 which switches a signal level of the digital signal DOUT each time a trigger signal is input; an XOR circuit 13 which outputs a first enable signal EN1 while a signal level of the digital signal DIN does not match with the signal level of the output digital signal DOUT; and a charge counter 14 which counts in synchronization with a clock signal CLK while the first enable signal EN1 is input and resets the count to an initial value and outputs a carry on signal ON_RCO as the trigger signal to the toggle flip-flop 12 when the count has reached an upper limit value.

Abstract: A method and apparatus provide digital frequency channelization of a digitally sampled input stream having a first bandwidth.

Abstract: A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.

Abstract: A waveform equalization circuit includes: a decision feedback equalization unit that feeds back and equalizes an input signal; a clock phase adjustment unit that adjusts a clock phase of a signal equalized by the decision feedback equalization unit based on a signal determined with a prescribed potential as a threshold; and a duo-binary decoder that encodes, into a duo-binary signal, the signal determined with the prescribed potential as a threshold based on a clock adjusted by the clock phase adjustment unit from the signal equalized by the decision feedback equalization unit; wherein the equalized signal is generated by adding the duo-binary signal encoded by the duo-binary decoder to the input signal. A first post-tap of the input signal is equalized by the clock phase adjustment unit without feedback equalization by the decision feedback equalization unit. Second and subsequent post-taps of the input signal are fed back and equalized by the decision feedback equalization unit.

Abstract: Wavelet thresholding using discrete wavelet transforms is a sophisticated and effective approach for noise reduction. However, usage of integer arithmetic implies that not the full range of input values can be used. A method for selectively reducing noise in a digital signal having a first range of values comprises steps of decomposing the digital signal to a plurality of frequency sub-bands, wherein before, during or after the decomposing the digital signal or at least one sub-band is expanded by one or more bits to a second range of integer values, removing in at least one of the frequency sub-bands values that are below a threshold, re-combining the frequency sub-bands, after removing said values that are below a threshold, into an expanded output signal, and de-expanding the expanded output signal, wherein a signal having the first range of values is obtained.

Abstract: A SAR ADC includes a DAC including a first set of capacitors each having a first end connected to a common node, and a second end, and a first set of switches each connecting the second end of a respective one of the capacitors to a first reference voltage. The SAR ADC further includes a second set of capacitors each having a first end connected to the common node and a second end that receives an input to be converted when the common node is connected to ground. The SAR ADC further includes a second set of switches that selectively connect the second end of a first capacitor of the second set of capacitors to ground when the input is disconnected from the second ends of the second set of capacitors and when the common node is disconnected from ground during a first of a plurality of successive approximations.

Abstract: A device for voice identification including a receiver, a segmenter, a resolver, two advancers, a buffer, and a plurality of IIR resonator digital filters where each IIR filter comprises a set of memory locations or functional equivalent to hold filter specifications, a memory location or functional equivalent to hold the arithmetic reciprocal of the filter's gain, a five cell controller array, several multipliers, an adder, a subtractor, and a logical non-shift register. Each cell of the five cell controller array has five logical states, each acting as a five-position single-pole rotating switch that operates in unison with the four others. Additionally, the device also includes an artificial neural network and a display means.

Abstract: An apparatus for processing a plurality of real-valued subband signals using a first real-valued subband signal and a second real-valued subband signal to provide at least a complex-valued subband signal comprises a multiband filter for providing an intermediate real-valued subband signal and a calculator for providing the complex-valued subband signal by combining a real-valued subband signal from the plurality of real-valued subband signals and the intermediate subband signal.

Abstract: A time domain filter receives a double sideband (DSB) input in the frequency domain and compresses this input into a time domain signal filtered by a time gate for providing a time filtered signal that is then expanded back into the frequency domain as a single sideband (SSB) output with one sideband being filtered by the time gate for translating DSB signals into SSB signals well suited for communicating chirped modulated signals as SSB signals along an electrical line or optical fiber without dispersive nulling of the communicated signal.

Abstract: A digital filter having improved attenuation characteristics is disclosed. The disclosed performs upsampling of model filter response by applying a sampling kernel scaled by a sampling constant. The disclosed filter has good attenuation characteristics with small number of taps and pass bands of the digital filter can be changed with simple parameter variation.

Abstract: A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one or more multiply and accumulate (MAC) units, each MAC unit being associated with a coefficient multiplexer unit and determines a product of the retrieved filter coefficient with an input sample; retrieves a previous value stored in an associated register; computes a summation of the previous value and the product; and stores the summation in the associated register. The processor includes an output multiplexer unit to select a register, and to provide a value stored in the register as an output.

Abstract: Disclosed are new approaches to Multi-dimensional filtering with a reduced number of memory reads and writes. In one embodiment, a filter includes first and second coefficients. A block of a data having width and height each equal to the number of one of the first or second coefficients is read from a memory device. Arrays of values from the block are filtering using the first filter coefficients and the results filtered using the second coefficients. The final result may be optionally blended with another data value and written to a memory device. Registers store results of filtering with the first coefficients. The block of data may be read from a location including a source coordinate. The final result of filtering may be written to a destination coordinate obtained by rotating and/or mirroring the source coordinate. The orientation of arrays filtered using the first coefficients varies according to a rotation mode.

Abstract: Approaches for preparing a design of a digital multirate filter. In one approach, an objective function and an input and output characteristic are input for determining an effectiveness of a plurality of filters. The characteristic includes an overall rate change value that specifies a ratio of an input to an output sample rate. The overall rate change value is factored into a plurality of ordered sets, and the overall rate change value is a product of the factors in the ordered sets. Each of the filters corresponds to one of the ordered sets and includes a respective stage for each factor in the ordered set. One of the filters is selected based on respective values determined from evaluating an objective function for the filters, and the factor(s) in the ordered set that corresponds to the selected one of the filters is stored.

Abstract: A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: G = [ F ? ( s + j? 0 ) + F ? ( s - j? 0 ) 2 F ? ( s + j? 0 ) - F ? ( s - j? 0 ) 2 ? j - F ? ( s + j? 0 ) - F ? ( s - j? 0 ) 2 ? j F ? ( s + j? 0 ) + F ? ( s - j? 0 ) 2 ] where F(s) is a transfer function representing the predetermined process, ?0 is a predetermined angular frequency and j is the imaginary unit.

Abstract: Methods and systems for signal filtering in electronic devices are provided. More particularly, methods and systems for filtering of radio frequency (RF) signals are provided. A filter circuit may comprise a down-converter, a filter, coupled to the down-converter and configured to filter the down-converted signal, and an up-converter, coupled to the filter. A filter circuit may also comprise a combining circuit, coupled to the up-converter and configured to combine the filtered, up-converted signal and the input signal.

Abstract: Device for determining an error induced by a high-pass filter in a signal, including a unit (3) for calculating the error according to the formula: E(t)=Ve(t)?Vs(t)=2·?·Fc·??=t0t(Vs(?)? Vs(?))·d?+E(t0) with: E(t) the value of the error induced by the high-pass filter, as a function of the time variable t, ?the trigonometric constant, Fc the cutoff frequency of the high-pass filter, t0 the initial instant, ?integration variable, Ve the signal input to the high-pass filter, Vs the signal output by the high-pass filter, Vs the mean value of the signal Vs. A method of correcting the error induced is also presented and applicable to the error correction of a piezoelectric pressure sensor.

Abstract: In an RF signal transmission network such as the reverse channels of a coaxial cable network, there is provided at least one adaptive equalizer for pre- or post-filtering inter-symbol interference in the transmitted signals, the adaptive equalizer having a series of coefficients for which values are required. In order to improve the transmission efficiency the preamble used in these channels is shortened by coarsely estimating the channel using a short “unique word’ placed at the beginning of the equalizer training sequence. The coarse channel estimate is crudely inverted to produce a set of equalizer coefficients which partially equalize the channel. By initializing the adaptive equalizer with these approximate coefficients, it is possible to reduce the length of the training sequence needed for the equalizer to converge.

Abstract: A method and system for processing Kalman Filter. The system includes: an Unscented Kalman Filter; and a processor device configured to: non-uniform a phase duration of a signal outputted from a plant; inputting the signal to the Unscented Kalman Filter; and restore non-uniformed phase duration of an estimated value calculated in the Unscented Kalman Filter to the phase duration.

Abstract: Techniques for filtering noisy estimates to reduce estimation errors are described. A sequence of input values (e.g., for an initial channel impulse response estimate (CIRE)) is filtered with an infinite impulse response (IIR) filter having at least one coefficient to obtain a sequence of output values (e.g., for a filtered CIRE). The coefficient(s) are updated based on the sequence of input values with an adaptive filter, a bank of prediction filters, or a normalized variation technique. To update the coefficient(s) with the adaptive filter, a sequence of predicted values is derived based on the sequence of input values. Prediction errors between the sequence of predicted values and the sequence of input values are determined and filtered to obtain filtered prediction errors. The coefficient(s) of the IIR filter are then updated based on the prediction errors and the filtered prediction errors.

Abstract: Systems and methods for asynchronous sample rate conversion are provided that allow time-varying arbitrary sample ratios. An uncorrected ratio between two arbitrary sample rates is corrected and subsequently used to perform an efficient sample rate conversion on the samples in a data stream. Coefficients of a (polyphase) finite impulse response filter are interpolated based on a current time register value. Additional computational efficiency (and a smaller finite impulse response filter) may be used due to oversampling the input signal to the finite impulse response filter.

Abstract: A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.

Abstract: The IIR resonator digital filter which is the subject of this patent invention comprises a first register having a plurality of inputs and outputs, a multiplexer/demultiplexer having a plurality of inputs and outputs, a first multiplier having a plurality of inputs and an output, a second multiplier having a plurality of inputs and an output, a third multiplier having a plurality of inputs and an output, an adder having a plurality of inputs and an output, a subtractor having a plurality of inputs and an output, and a second register having an input and a plurality of outputs. The IIR resonator digital filter features a multiplexer/demultiplexer that has five logical states.

Abstract: An apparatus comprising an analog filter, an analog to digital converter coupled to said analog filter; and a digital filter coupled to said analog to digital converter; wherein the apparatus is configured such that distortion introduced into a filtered signal by said analog filter is substantially compensated by said digital filter.

Abstract: An edge detection filter comprising an array of filter coefficients having an odd number of rows and columns, a first set of zero coefficients extending along a direction traversing the array through a center position to form a first and second side, a second set of positive coefficients extending away from the direction on the first side, and a third set of negative coefficients extending away from the direction on the second side.

Abstract: Methods and apparatus are provided for determining coefficients for a digital low pass filter, given cutoff and boost values for a corresponding analog version of the digital low pass filter. Coefficients are determined for a digital low pass filter by obtaining cutoff and boost values for a corresponding analog version of the digital low pass filter; and determining the coefficients for the digital low pass filter based on the obtained cutoff and boost values.

Abstract: Multistage Wiener filters (MWF) represent a component of the MWF as an un-normalized vector of filter coefficients within a finite impulse response (FIR) filter in a manner that avoids reliance on the 2-norm operation of the un-normalized vector of coefficients. The 2-norm operation can be replaced by less expensive operations performed elsewhere in the MWF. Preferably the filter adds only a few additional addition, subtraction and multiplication operations to compensate for the elimination of the square root and the division operations used for the 2-norm operation. As a result, it is possible to eliminate all or nearly all of the square rod and arithmetic division operations of at least some implementations of the MWF.

Abstract: A method and circuit that gives a sequence pattern that represents directions of positive and negative transitions of the phase that continue over a predetermined number from a certain reference symbol to an adjoining next reference symbol; finds (heuristically) one or more interpolate symbols that meet conditions (such as standards for power spectra) of a predetermined frequency spectrum, i.e., band, and a predetermined (range of) amplitude with reference to the given sequence pattern; and stores the found sequence pattern and a phase value and an amplitude value corresponding to the found one or more interpolate symbols in a memory as a lookup table against the prepared memory area.

Abstract: A signal filter and accompanying methods. In one embodiment, the filter includes a first mechanism for receiving a first signal. A second mechanism employs one or more modified representations of the first signal to cancel one or more frequency components of the first signal, yielding an output signal in response thereto. In a more specific embodiment, the first mechanism includes a splitter for receiving the first signal and splitting the first signal onto a first path and a second path. The second mechanism further includes one or more delay modules and one or more phase shifters in the first path and/or the second path. One or more controllable amplifiers are optionally included in the first path and/or the second path. The one or more delay modules, phase shifters, or amplifiers are responsive to one or more control signals from a controller. The controller is adapted to modify behavior of the second mechanism so that the filter is characterized by a desired frequency response.

Abstract: A filter operation unit that performs a multiply-accumulate operation on input data and a filter coefficient group including a plurality of coefficients using Booth's algorithm. The filter operation unit includes: at least two filter multiplier units that multiply the input data and a difference between adjacent filter coefficients in a filter coefficient group to obtain multiplication results; and an adder that adds the multiplication results of the multiplier units adjacent to each other. The filter multiplier units each include: a partial product generation unit that repeatedly generates a partial product according to Booth's algorithm; and an adder that cumulatively adds the partial products generated by the partial product generation unit.

Abstract: A large-scale sound system or communication system is numerically and stably identified. When an input signal is represented by the M(?N)-th order AR model, high-speed H? filtering can be performed with a computational complex 3N+O(M). A processing section determines the initial state of a recursive equation (S201), sets CUk according to an input uk (S205), determines a variable recursively (S207), updates a matrix GkN, calculates an auxiliary gain matrix KUkN (S209), divides it (S211), calculates a variable DkM and a backward prediction error ?m, k (S213), calculate a gain matrix Kk (S215), and updates a filter equation of a high-speed H? filter (S217). To reduce the computational complexity, Kk(:, 1)/(1+&ggr;f?2 Hk Kk (:, 1)) is directly used as the filter gain Ks, k.

Abstract: A method for determining filter coefficients for a mismatched filter is disclosed. The method includes generating a code sequence having a code length, determining a length of the filter, and performing a modified least mean squares (LMS) algorithm. The length of the filter corresponds to coefficients of a transfer function of the filter, and the length of the filter is not equal to the code length. The filter coefficients are iteratively adjusted in the LMS algorithm until an error signal for each of the filter coefficients is below a threshold value.

Abstract: Methods for determining variance properties of a noise component of a raw signal of a machine or a system. An example method includes recording a signal using a noise estimation unit, numerically differentiating the signal using a first module of the noise estimation unit to obtain a differentiated signal, identifying, using a second module of the noise estimation unit, a histogram which corresponds to the differentiated signal, and determining using the histogram, a variance property of the noise component of the signal.

Abstract: An infinite impulse response (IIR) filter is provided. The IIR filter includes an amplifier and a filter coupled in a feedback path of the amplifier. The amplifier generates an output signal according to an input signal. The filter filters the output signal according to a first transfer function and provides the filtered output signal to an input of the amplifier. The IIR filter and the first filter have the same order larger than one.