Abstract: A system and method for dynamically migrating stash transactions include first and second processing cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), and an operating system (OS) scheduler. The first core executes a first thread associated with a frame manager. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers to indicate scheduling-out and scheduling-in of the first thread from the first core and to the second core. The STMMU uses the pre-empt notifiers to enable dynamic stash transaction migration.

Abstract: A switch device that allows a user to use the same non-Bluetooth user console (e.g., keyboard, mouse) to control both non-Bluetooth computers and Bluetooth master machines such as tablet computers, smart phones, etc. The switch device includes a console port for connecting to the console and one or more computer ports for connecting to one or more computers, as well as a Bluetooth module for communicating with Bluetooth master machines. A controller processes input device data received via the console port, and either sends the data to a selected Bluetooth master machine or a selected computer, or perform other functions such as switching, Bluetooth device pairing and disconnecting based on the input device data. The controller stores link information of the Bluetooth master machines already paired with the computer switch for quickly switching to a Bluetooth master machine. The switch device can be with or without video switching.

Abstract: A server blade insertable into a chassis of a blade server system includes a main circuit board coupled to the chassis upon insertion, a plurality of connectors residing on the main circuit board, a plurality of grouped hard disk drives, and a plurality of computer modules, each insertable into a corresponding one of the connectors. Each of the grouped hard disk drives couples to one or more of the computer modules. Each of the grouped hard disk drives includes a first hard disk drive exposed proximate to a front side of the chassis, and a second hard disk drive positioned between the first hard disk drive and a back side of the chassis. A subset of the grouped hard disk drives includes a first grouped hard disk drive and a second grouped hard disk drive stacked on the first grouped hard disk drive.

Abstract: A control circuit performs control to initialize a plurality of interface circuits connected to a communication circuit and each connected to each of a plurality of communication lines, and detects whether or not initialization of each of the interface circuits has been completed. When the control circuit detects that initialization of all of the interface circuits has been completed, the control circuit controls the communication circuit so as to start data communication via the interface circuits.

Abstract: Systems and methods for providing a differentiation of two identical slave devices on a same I2C bus without any hardware (e.g. additional ID pins) or software overhead are disclosed. Each identical slave device is connected to the SDA/SCL lanes by interchanging its SDA/SCL ports. It is up to the slave device to detect its signal connectivity to the SDA/SCL lanes of the I2C bus. The slave devices detect the signal connectivity by interpreting the I2C transfer in normal and interchanged connectivity.

Abstract: A method of providing a synchronization channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D? data signalling lines disabled or disconnected at an upstream connection point; multiplexing synchronization information onto the D+/D? data signalling lines at the upstream connection point; and demultiplexing the synchronization information from the D+/D? signalling lines at a downstream connection point of the cable; whereby the synchronization channel is maintained across the D+/D? data signalling lines.

Abstract: Embodiments provide methods, systems, and articles of manufacture for determining a configuration for system board based on a connector. The connector may have a structure that enables a system board to determine configuration data associated with a system configuration.

Abstract: There is provided a communication apparatus including an HDMI connector complying with HEC (HDMI Ethernet Channel)-compliant HDMI standards, comprising: an HEC communication unit configured to communicate, via HEC, with an HEC-compliant communication apparatus connected to the HDMI connector; a determination unit configured to determine, using a protocol of the HDMI standards, whether or not an HEC-compliant communication apparatus is connected to the HDMI connector; and a control unit configured to stop power supply to the HEC communication unit if it is determined that an HEC-compliant communication apparatus is not connected to the HDMI connector.

Abstract: A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.

Abstract: A Registered DIMM (RDIMM) system with reduced electrical loading on the data bus for increases memory capacity and operation frequency. In one embodiment, the data bus is buffered on the DIMM. In another embodiment, the data bus is selectively coupled to a group of memory chips via switches.

Abstract: A data communication interface for an agricultural utility vehicle, particularly an agricultural tractor, having an interface connector that can be connected either to a first data communication network or to a second data communication network by means of an electrically operatable changeover device, wherein the first data communication network is terminated at a line end associated with the interface connector by means of a disconnectable terminating resistor, and having a control unit that connects the interface connector to the first data communication network by means of appropriate operating of the changeover device exclusively when it infers the presence of a control signal that is provided for disconnecting the terminating resistor.

Abstract: This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined number of least significant bits overlapping a predetermined number of most significant bits. Each client receives the least significant bits. Each client associates captured data with a corresponding set of the least significant bits in a message. A central scheduling unit associates most significant bits of the time stamp value with the least significant bits of the message. This associating compares overlap bits of the most significant bits and least significant bits. The most significant bits are decremented until the overlap bits are equal.

Abstract: A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.

Abstract: In one embodiment, a main circuit board includes a plurality of expansion slots that are operative to receive a corresponding plurality of expansion cards. The plurality of expansion slots include at least one first expansion slot configured at a first position on the main circuit board, that is operative to connect to at least one corresponding first expansion card. At least one second expansion slot configured at a second position on the main circuit board, and the second expansion slot is operative to connect to at least one corresponding second expansion card. The plurality of expansion cards includes at least one secondary expansion card that is different from the main circuit board and that is configured to be operatively coupled to at least one of the plurality of expansion slots. One or more particular expansion slots are selected for connecting one or more corresponding particular expansion cards, based on the size, dimensions, and/or function of the particular expansion cards to be connected.

Abstract: Systems and methods that allow a PSD to be physically shared by multiple servers such that if a server fails, another server can be utilized as a backup server for the PSD without any manual intervention or moving of the PSD and without risking loss of data from the PSD. A PSD is interfaced by an interface device to a system level bus that allows for multiple initiators. An initiator is any server that can access and issue commands over the system level bus to access the PSD. When one of the servers fails, the functionality of the server can be rolled to a backup server which will be able to access the PSD over the bus.

Abstract: A hardware trie structure includes a tree of internal node circuits and leaf node circuits. Each internal node is configured by a corresponding multi-bit node control value (NCV). Each leaf node can output a corresponding result value (RV). An input value (IV) supplied onto input leads of the trie causes signals to propagate through the trie such that one of the leaf nodes outputs one of the RVs onto output leads of the trie. In a transactional memory, a memory stores a set of NCVs and RVs. In response to a lookup command, the NCVs and RVs are read out of memory and are used to configure the trie. The IV of the lookup is supplied to the input leads, and the trie looks up an RV. A non-final RV initiates another lookup in a recursive fashion, whereas a final RV is returned as the result of the lookup command.

Abstract: Communication between a payload services unit (PSU) and a payload unit utilizes a single-wire interface used to power the PSU as well as to communicate telemetry and command signals. A telemetry and command (T&C) system includes a payload unit configured to respond to a plurality of commands and generate a plurality of telemetry data, an embedded service module (ESM) within the payload unit, and a payload service unit (PSU) configured to generate the plurality of commands and receive the plurality of telemetry data. A single-wire interface is coupled between the ESM and the PSU and configured to provide power to the ESM, wherein the payload unit and PSU are configured to communicate the plurality of commands and the plurality of the telemetry data over the single-wire interface.

Abstract: A television includes at least two ports (e.g. HDMI ports). The television polls the ports before presenting a user interface that displays some or all of the ports and before toggling between any two of the ports. The polling ascertains whether a device is connected to each of the ports and whether the device is powered. The television modifies the display and/or toggling based on the current state of each port. For example, in toggling, ports that are not connected and ports that are connected to inactive devices are skipped. In another example, when displaying a list of ports, only those ports that are connected to devices appear in the list.

Abstract: An interface circuit board apparatus can include a shared circuit board base, a transceiver section disposed on the circuit board base, and having circuit transceiver sites configured to receive a plurality of transceiver component types, a termination section disposed on the circuit board base, and having circuit termination sites configured to receive a plurality of termination component types, and a connection section operatively coupled to the transceiver and termination sections, wherein the transceiver section, the termination section and the connection section are configurable to support a plurality of interface types based on the plurality of transceiver component types and the plurality of termination component types.

Abstract: An interface for an industrial controller is provided that enables connection of different types of plug-in I/O modules to the industrial controller. The interface includes several mechanisms, which can be implemented through control logic, circuitry, and/or software, that enable the control/monitoring device to operate in conjunction with different types of plug-in I/O modules. According to certain embodiments, the interface includes setup mechanisms that enable initial communications between the plug-in I/O modules and the control/monitoring device. The interface also may include operational mechanisms that facilitate communication between the plug-in I/O modules and the control/monitoring device during operation. The interface further may include registers that store data for the plug-in I/O modules.

Abstract: A system and method are directed towards a pseudo multi-master operation on a serial bus. The pseudo multi-master operation allows multiple devices without standard multi-master functionality to operate on the serial bus as masters. In a disclosed example, the serial bus is an Inter-Integrated Circuit (I2C) bus, which is isolated when an adapter card requires access to the I2C bus, such as to update vital product data (VPD) to a memory device, and to cache the updated VPD to a chassis management module.

Abstract: Mechanisms are provided for determining the location of computing assets within an organization. These mechanisms determine first location information identifying a location of at least one first physical asset housing in a predetermined physical area of the organization relative to a predetermined coordinate system, and second location information identifying a location of at least one second physical asset housing within the at least one first asset housing. The mechanisms automatically determine third location information identifying a location of at least one computing asset within the at least one second physical asset housing. In addition, the mechanisms generate an asset location map data structure for the organization based on the first, second and third location information. The mechanisms also perform at least one management operation for managing resources of the organization, based on the asset location map data structure for the organization.

Abstract: In one embodiment, a method includes accessing a first field of a first link capabilities register of a first device having a protocol stack including a transaction layer and a link layer according to a first communication protocol and a physical layer of the protocol stack having a physical unit of a second communication protocol, using the first field as a pointer value to a location in a second link capabilities register of the first device, and using information from the location in the second link capabilities register to perform a configuration operation for a physical link coupled to the device. Other embodiments are described and claimed.

Abstract: Mechanisms are provided for determining the location of computing assets within an organization. These mechanisms determine first location information identifying a location of at least one first physical asset housing in a predetermined physical area of the organization relative to a predetermined coordinate system, and second location information identifying a location of at least one second physical asset housing within the at least one first asset housing. The mechanisms automatically determine third location information identifying a location of at least one computing asset within the at least one second physical asset housing. In addition, the mechanisms generate an asset location map data structure for the organization based on the first, second and third location information. The mechanisms also perform at least one management operation for managing resources of the organization, based on the asset location map data structure for the organization.

Abstract: A computing device is provided that includes a computing unit, which has a working memory and a processing unit, and a boot memory having control instructions for operating the computing device. The control instructions are stored in boot memory and are to be transferred to the computing unit at start-up of the computing device. A boot control unit is connected to the computing unit by at least a first and a second interface and connected to the boot memory by a third interface. The boot control unit is configured to transfer a first part of the control instructions from the boot memory via the first interface to the computing unit and to transfer a second part of the control instructions from the boot memory via the second interface to the computing unit.

Abstract: An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is op

Abstract: Methods and apparatus for tunneling platform management messages through inter-processor interconnects. Platform management messages are received from a management entity such as a management engine (ME) at a management component of a first processor targeted for a managed device operatively coupled to a second processor. Management message content is encapsulated in a tunnel message that is tunneled from the first processor to a second management component in the second processor via a socket-to-socket interconnect link between the processors. Once received at the second management component the encapsulated management message content is extracted and the original management message is recreated. The recreated management message is then used to manage the targeted device in a manner similar to if the ME was directly connected to the second processor. The disclosed techniques enable management of platform devices operatively coupled to processors in a multi-processor platform via a single management entity.

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

Abstract: Function approximation circuitry approximates an arbitrary function F over discrete inputs. Discrete values of the function F are stored in a lookup table (LUT) component for various inputs. An addressing module generates an address from an input. An interpolation factor module generates an interpolation factor from the input. An interpolation module generates an output, which is an approximate value of the function F for the input, from the interpolation factor, and from outputs of the LUT component when the LUT component is addressed by the address.

Abstract: Embodiments of the invention are related to methods, systems, and articles of manufacture for transferring data between two devices using an interconnect bus. On each conductive line of the bus, a bit representing a first logic state is transferred if a current bit is the same as an immediately previously transmitted bit. If the current bit is different from the immediately previously transmitted bit, then a bit representing a second logic state is transferred.

Abstract: A processor with real-time signal transmission and storage comprises a motherboard and a display. The motherboard has a power input end, a processing core, a signal input end, a storage device and an image output end. The power input end has one conducting wire to connect to the power source to provide power to the motherboard and a display; the processing core has a processing program inside and connect to the signal input end and the storage device; the signal input end provides a transmission line to connect an input end of a working unit; and the storage device provides space to save signals complied and organized by the processing core. The display has a signal connector to connect to the image output end of the motherboard.

Abstract: An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.

Abstract: A mobile terminal and a control method thereof are provided. The mobile terminal selects a method of interfacing an identification device with the mobile terminal according to whether the mobile terminal enters a sleep mode.

Abstract: To facilitate efficient communications in a multi bus master system that communicates with a plurality of peripheral devices, a two channel bus is used that shares write and read addresses with data on a transmit channel to reduce wiring density and provide efficient, reliable, and high speed data transfers. The two channel bus includes the transmit channel, a receive channel, and a single control channel that provides control information for both the transmit channel and the receive channel further reducing the signaling requirements of the two channel bus. The control information includes a control flag that specifies control information for data transfers on the two channel bus. The control flag and control information may be supplied in two bus cycles or in a single bus cycle depending on the control requirements for two data transfers occurring in parallel on the two channel bus.

Abstract: The present invention provides a wireless communication device and a method for manufacturing a wireless communication device. The wireless communication device includes: an antenna; a main board, including a ground part, where the ground part is connected to the antenna; at least one matching network, connected to the ground part; a USB connector, including a shell and at least one first pin extending from the shell, where the at least one first pin is connected to the at least one matching network, and at least one first pin is one-to-one corresponding to at least one matching network. According to the present invention, a matching network may be connected between a pin of the USB connector of the wireless communication device and the ground part of the main board, and is configured to control wireless performance of an antenna radiation system of the wireless communication device.

Abstract: A scalable portable-computer system is disclosed. A novel portable-computer comprises a cluster connectivity bus, hard-wired to the central and graphics processing units (CPU and GPU, respectively) of said portable computer. An innovative portable-computer module comprises a top and a bottom interconnection port, preferably oriented in a plane perpendicular to the base surface of the computer. Different embodiments include a laptop computer, an extended laptop computer and a tablet computer. Several optional modules are also disclosed, including a memory-extension and a base module. Use of suitable adapters ensures that all modules have the same width, length and interconnectivity ports location. A plurality of portable computers and optional modules are interconnectedly stacked, thereby forming an on-demand supercomputing cluster, advantageously utilizing all available CPUs and GPUs. Each individual computer acts as a node in the cluster.

Abstract: A method is disclosed that includes writing data to predetermined physical addresses of a system memory, the data including metadata that identifies a processing type; configuring a processor module to include the predetermined physical addresses, the processor module being physically connected to the memory bus by a memory module connection; and processing the write data according to the processing type with an offload processor mounted on the processor module.

Abstract: A bus driver circuit divides an internal data bus for an integrated circuit memory into at least two groups, designated by speed. A faster group of data lines and a slower group of data lines are placed in an interleaved fashion in order to provide a two group shielding solution. At the earliest opportunity following the reception of a read command, the data from memory banks in the memory is sorted into these two groups. For a DDR3 memory, the sorting method is based on the A2 column address, known as C2. All of the data is brought out of the banks in parallel and sorted as it enters the main amplifiers. These main amplifiers are also divided into two groups, faster and slower. Each amplifier then connects to a data line (G-line) of the same group. The clock assigned to the fast group fires right away, thereby connecting the data associated with the fast amplifiers to the fast data group. This data group then proceeds to the output buffers through the entire data path as fast as possible.

Abstract: The present invention provides a information transmission device including: a transmission section that transmits information to a first transmission path that transmit information serially; a reception section that receives information from a second transmission path; a waveform shaping section that, according to setting information, shapes at least one of a signal waveform of the information for transmission, and/or a signal waveform of the information for reception; and a controller that, when establishing communication, controls the transmission section to transmit predetermined first information that requests communication establishment, and effects control to change the first setting information and controls the transmission section to re-transmit the first setting information when the reception section has not received the first information within an interval that from the beginning of transmission of the first information until a predetermined duration required for communication establishment has elap

Abstract: The disclosure describes a novel method and apparatus for allowing a controller to access a bus router using a communication occurring in response to one edge of a clock to select one or more devices for access using a communication occurring on the opposite edge of the clock. Additional embodiments are also provided and described in the disclosure.

Abstract: The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

Abstract: In one embodiment, there is provided an extender for extending functions of an electronic apparatus. The extender includes: a connection terminal electrically connected to the electronic apparatus; input signal lines connected to the connection terminal to transmit a video signal that is supplied from the electronic apparatus via the connection terminal; a first video output terminal which complies with a first standard; a second video output terminal which complies with a second standard; and a signal converter configured to convert the video signal into a first video signal that complies with the first standard to output the first video signal to the first video output terminal and configured to convert the video signal into a second video signal that complies with the second standard to output the second video signal to the second video output terminal.

Abstract: A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.

Abstract: A semiconductor device which can consume less power and a method for driving the semiconductor device can be provided. The semiconductor device includes a processor including a control device and an arithmetic unit, a memory device, an input/output device, and a plurality of bus lines which is a path for transmitting and receiving instructions, addresses, or data between the processor and the memory device, or the processor and the input/output device. A first memory storing each piece of information over the bus line is connected to each of the bus lines, and a second memory storing a status flag relating to information over the bus line is connected to the control device.

Abstract: The disclosed embodiments provide a system that enables a portable computing device to receive power through multiple bus interfaces at the same time. When the system senses that a first power source is plugged into a first bus interface in the portable computing device, the system determines whether the first power source is a host or a power adapter. Next, based upon whether the first power source is a host or a power adapter, the system uses a first power manager coupled to the first bus interface to limit a first input current received from the first power source to power the computing device. The system also provides the maximum charging current to a rechargeable battery for the portable computing device by chaining together a second bus interface whether power is present on the second bus interface or not.

Abstract: A data storage device may include a first memory board and a second memory board, where the first memory board and the second memory board each comprise multiple memory chips. The data storage device may include a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, where the controller board includes a high speed interface and a controller that is arranged and configured to receive commands from a host using the high speed interface and to execute the commands, where the first memory board and the second memory board are each separately removable from the controller board.

Abstract: A communication system for transmitting data, for example, within a System-in-Package. The system includes a first circuit configured for: a) dividing the data into a plurality of packets having a determined size; and b) creating for each of the packets a transmission segment including a segment header and the respective packet as payload. The system also includes a second circuit configured for: a) separating the transmission segments into a plurality of physical units, where the physical units have a determined size; and b) transmitting the physical units over a physical communication channel. In particular, the segment header includes at least one field that identifies the number of physical units that are to be transmitted.

Abstract: An interface circuit for a switch array having an array of switches, each closeable to couple a row conductor of a plurality of row conductors to a column conductor of one or more column conductors, comprises a current generator and a current detector. The current generator has a plurality of row interface ports for coupling to different ones of the row conductors and is arranged to generate a switch array current for coupling to the row interface ports, the switch array current having a different one of a plurality of different switch array current magnitudes for different ones of the row interface ports, and generate one or more reference currents each having a different reference current magnitude.

Abstract: A method for fully-automatically aligning the quality of an image is provided. The method processes the video signals provided by the Video Graphic Array (VGA) display card in the computer system through the multi-sync display itself, and further interprets whether a computer host ID stored in the VGA display card or the computer host matches with a computer host ID stored in the multi-sync display, so as to avoid repetitious aligning to the same computer system, and achieve full automatic aligning to the quality of the image displayed on the multi-sync display. Therefore, even if the multi-sync display is situated under different computer hosts or VGA display cards and placed where an user cannot touch, the inconvenience of pressing a button on the multi-sync display to align the quality of the image displayed on the multi-sync display in conventional techniques can be prevented.