Abstract: A bus interconnect interfaces a host system to a radio frequency (RF) generator that is coupled to a plasma chamber. The bus interconnect includes a first set of host ports, which are used to provide a power component setting and a frequency component setting to the RF generator. The ports of the first set of host ports are used to receive distinct variables that change over time. The bus interconnect further includes a second set of generator ports used to send a power read back value and a frequency read back value to the host system. The bus interconnect includes a sampler circuit integrated with the host system. The sampler circuit is configured to sample signals at the ports of the first set at selected clock edges to capture operating state data of the plasma chamber and the RF generator.

Abstract: An information processing apparatus includes a plurality of modules connected in a ring shape via a bus, and each module processes a packet flowing in a single direction on the ring in a predetermined order. The module includes a communication unit for transmitting a packet received from a first direction in the ring via the bus to a second direction, a discrimination unit for discriminating a packet from among the packets received from the first direction as a processing packet to be processed by the module, and a processing unit which is connected with the communication unit one by one and configured to process the processing packet. The communication unit transmits the packet processed by the processing unit at an interval equivalent to processing time or more for a processing packet processed by a module in a latter stage in the predetermined order among packets transmitted by the communication unit to the second direction.

Abstract: An audio system including a first audio unit and a second audio unit coupled to the first audio unit through an audio bus. A first processor is coupled to the first audio unit. The first processor is configured to transmit bits comprising audio content to the second audio unit over the audio bus. The first processor is further configured to receive a control command selected from a plurality of control commands, and in response, interrupt the bits comprising audio content and send a preamble and a control message on the audio bus, wherein the control message corresponds to the control command. A second processor is coupled to the second audio unit. The second processor is configured to monitor the audio bus for a preamble, and if a preamble is detected, then process the control message and execute the corresponding control command.

Abstract: A method of balancing input/output (I/O) device interrupt service loading in a computer system comprises: assigning priorities to a plurality of I/O device interrupts of a processing unit of the computer system; servicing the plurality of interrupts according to the assigned priorities thereof; collecting data on the interrupt servicing of the plurality of interrupts over a time interval; reassigning the priorities of the plurality of interrupts based on the collected interrupt service data; and repeating the collecting and reassigning steps to balance input/output (I/O) device interrupt service loading of the processing unit.

Abstract: A control system includes a gateway controller and a remote controller. The gateway controller is configured to embed an HTTP request in a CAN bus-compatible message and transmit the CAN bus-compatible message onto a CAN bus. The remote controller is configured to receive the CAN bus-compatible message from the CAN bus, extract the HTTP request from the CAN bus-compatible message, and create an HTTP response to the HTTP request.

Abstract: A data interface is provided for point-to-point communications between two devices, such as a read channel and a disk controller in an HDD system. An interface for communications from a transmitting device to a receiving device comprises a data bus configured to communicate m bits of data and a corresponding n bit data tag, wherein a given n bit data tag identifies a data type of a corresponding m bits of data on the data bus. An acknowledge signal from the receiving device optionally indicates that data on the data bus has been received and that the data on the data bus can be changed to a new value. A valid flag optionally indicates when a new predefined m-bit data value and corresponding n-bit tag value are on the data bus.

Abstract: A computer program product is provided for performing input/output (I/O) processing. The computer program product is configured to perform: generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data discard field; generating an address control structure specifying a local channel memory location of a corresponding ACW; receiving one or more data transfer requests from a network interface that each corresponding address control structure information; accessing an ACW and routing the data transfer request to a host memory location specified in the ACW; and responsive to encountering an error during at least one of the accessing and the routing, discarding the one or more data transfer requests and setting the data discard field to a value configured to instruct a channel to discard any subsequent data transfer requests associated with the ACW.

Abstract: A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.

Abstract: A bus system includes a plurality of master devices each of which issues a transaction request having a first transaction identifier with a first bit width and a slave device responding to the transaction request having a second transaction identifier with a second bit width and supplying a transaction response having the second transaction identifier to the plurality of master devices. The embodiment further comprises a bus configured to connect one of the plurality of master devices and the slave device; and an ID converter configured to connect the bus and the slave device and to map the first transaction identifier to the second transaction identifier for providing the second transaction identifier to the slave device and map the second transaction identifier to the first transaction identifier for providing the first transaction identifier to the one of the plurality of master devices.

Abstract: A shared network interface controller (NIC) interfaces a plurality of operating system domains as part of the load-store architecture of the operating system domains. A bus interface couples the NIC to a load-store domain bus (such as PCI-Express), using header information to associate data on the bus with an originating operating system domain. Transmit/receive logic connects the NIC to the network. Association logic allows the NIC to designate, and later lookup which destination MAC address (on the Ethernet side) is associated with which operating system domain. Descriptor register files and Control Status Registers (CSR's) specific to an operating system domain are duplicated and made available for each domain. Several direct memory access (DMA) engines are provided to improve throughput. Packet replication logic, filters (perfect and hash) and VLAN tables are used for looping back packets originating from one operating system domain to another and other operations.

Abstract: A method including intercepting a OFR for a file issued by an application to a FS, forwarding the OFR to the FS, receiving from the FS a FD for the file, issuing a SR for the file to the FS. The further method includes receiving from the FS status information for a target device on which the file is located, where the status information includes an OID for the file, storing a mapping of FD to the OID, intercepting a first FOR for the file, making a determination the that the first FOR is one of a read request and a write request, based on the determination, making another determination that the target device supports the direct I/O protocol, and issuing a DI request to the target device using the OID for the file, where the DI request is not processed by the FS.

Abstract: A method for setting addresses of slave devices in a communication network is provided. In the communication network, a master device identifies address-collided slave devices and requests the address-collided slave devices to return their unique identification data. The master device sets addresses of the address-collided slave devices so that each of the slave devices in the communication network has a different address from one another.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: Embodiments of the present disclosure are directed toward an automation control device including a base having a module slot, a functional module including communication and control circuitry configured to communicatively couple with the base via the module slot, a terminal block configured to communicatively couple the base and the first functional module with field wiring, a first power bus configured to transmit a first power to the functional module, and a second power bus configured to transmit a second power to the functional module.

Abstract: A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed.

Abstract: Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration.

Abstract: A collective communication apparatus and method for parallel computing systems. For example, one embodiment of an apparatus comprises a plurality of processor elements (PEs); collective interconnect logic to dynamically form a virtual collective interconnect (VCI) between the PEs at runtime without global communication among all of the PEs, the VCI defining a logical topology between the PEs in which each PE is directly communicatively coupled to a only a subset of the remaining PEs; and execution logic to execute collective operations across the PEs, wherein one or more of the PEs receive first results from a first portion of the subset of the remaining PEs, perform a portion of the collective operations, and provide second results to a second portion of the subset of the remaining PEs.

Abstract: A method includes executing microcode in a processing unit of a processor to implement a machine instruction, wherein the microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction. A processor includes a public communication bus, a peripheral device coupled to the public communication bus, and a processing unit. The processing unit is to execute microcode to implement a machine instruction. The microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction.

Abstract: A CPU outputs a high level ENB signal to a USB-IC via an ENB line and monitors, after outputting the ENB signal, whether or not there is an overcurrent in the USB-IC on the basis of the voltage level of the ENB line. The USB-IC outputs, when it receives the ENB signal, a 5 V voltage to a VBUS line and stops, when an overcurrent occurs, output of the 5 V voltage to the VBUS line. A connector changes the voltage level of the ENB line to a high voltage level using the 5 V voltage of the VBUS line and changes, when output of the 5 V voltage is stopped, the voltage level of the ENB line to a low level. Thus, the ENB line may be shared for outputting the ENB signal from the CPU and for providing notification of an overcurrent from the USB-IC.

Abstract: Service dependency is determined for services in a service oriented architecture (SOA) environment. The steps in determining service dependency include: recording a first triple describing a first service call where the first service calls the second service, and determining the first service is dependent upon the second service based, at least in part, upon the first triple. The recording action is performed dynamically, the recording occurring when the first service call is made. Other related steps include recording the first triple to a timestamp indicating when the first service call is made.

Abstract: A dual host system and method with back to back non-transparent bridges and a proxy packet generating mechanism. The proxy packet generating mechanism enables the hosts to send interrupt generating packets to each other.

Abstract: A verified cluster configuration is collected and stored by a central management entity. Servers within the cluster are connected to network cables, where each of the servers has at least one network port and memory storing a port identification code for each network port, and where each network cable has memory storing a cable identification code. For each verified connection between a network cable and a network port, the port identification code is stored in the memory of the network cable and the cable identification code is stored in the memory of the corresponding server. The data identifying each connection is stored by the central management entity and includes the port identification code for a particular network port in association with the network cable identification code for the corresponding network cable. Any miswiring of the configuration is identified by the central management entity and easily corrected by the administrator.

Abstract: In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a packet for communication along an interconnect and to transmit the packet. This packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.

Abstract: In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles.

Abstract: A communication interface hub includes multiple ports, where one of the ports is an upstream port operative to be in direct and/or indirect communication with a host and at least one other of the ports is a downstream port operative to be in direct and/or indirect communication with at least one device. At least one hub core is coupled to the ports and implements at least one physical hub, and at least one virtual hub core is coupled to the ports and implements at least one virtual hub. The virtual hub is detectable as at least one physical hub by the host to cause the host to allocate an additional time delay in waiting for responses to signals output by the host.

Abstract: The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.

Abstract: In one embodiment, a computer system comprises one or more processors, a circuit board assembly having at least one SATA port, a general purpose input/output port proximate the SATA port, signal generating logic to generate a signal when the general purpose input/output port is coupled to a connector, and a memory module communicatively connected to the one or more processors and comprising logic instructions stored in a computer readable medium which, when executed on the one or more processors, configure the one or more processors to configure the SATA port according to the signal generated by the signal generating circuitry.

Abstract: A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.

Abstract: A communication network for a low-voltage switchboard comprising three types of communication bus. The first communication bus is designed to provide a first communication channel with at least one electronic protection device. A second communication bus is designed to provide a second communication channel with said electronic protection device. At least one third communication bus (13) is designed to provide a third communication channel between said at least one protection and control unit and one or more additional electronic modules (6A, 6B, 6C, 6E, 6F). The second communication bus is associated with a second, higher user access level than the first user access level associated with said first communication bus.

Abstract: A plug connector with external contacts is provided. The connector has one pair of contacts for transmitting data and one pair of contacts for receiving data. All data transmitted and received using the plug connector is serialized/de-serialized to enable data transmission at a very high rate. A corresponding receptacle connector has configurable contacts that are configured based on the orientation of the plug connector with respect to the receptacle connector. The receptacle connector may be included in a host device and has associated circuitry to detect orientation of the plug connector and to configure the contacts of the receptacle connector.

Abstract: Methods and apparatus relating to observing an internal link via an existing port for System On Chip (SOC) devices are described. In one embodiment, a logic within an SOC device may allow an external logic analyzer to observe communication between a first and second component of the SOC through an existing (e.g., shared and/or non-dedicated) interface. Other embodiments are also disclosed.

Abstract: It is provided to implement a different number of logical slaves in a field device for use in an AS interface network as a function of the assigned address, which slaves may be addressed using the assigned address in the standard or in the expanded addressing mode. Thus, in a field device, it is possible to provide slaves having different profiles, via which different data types may be exchanged. Furthermore, a method is provided, with which a field device having different slaves is able to be addressed in a simple manner while avoiding double addressing.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Abstract: The present disclosure includes systems and techniques relating to booting to a network storage target. In general, in one implementation, a bus-to-network device driver is loaded during a machine boot, where the bus-to-network device driver is capable of sending machine bus commands over a network, providing access to the network for a network device driver, and distinguishing between received responses to the machine bus commands and other network traffic corresponding to the network device driver. Loading of the bus-to-network device driver can occur in response to an operating system load of bus drivers. For example, the bus-to-network device driver can be an iSCSI driver, and the operating system load of bus drivers can be the operating system load of SCSI drivers.

Abstract: A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select for delivering a chip select signal that indicates when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device. The interface also includes a differential clock pair for delivering a differential clock signal. A read data strobe is included in the interface for delivering a read data strobe signal from the peripheral device. The interface includes a data bus for delivering command, address, and data information. The read data strobe indicates when valid data is present on the data bus.

Abstract: Systems and methods for streaming data. Systems allow read/write across multiple or N device modules. Device modules on a bus ring configure at power up (during initialization process); this process informs each device module of its associated address values. Each ringed device module analyzes an address indicator word, which identifies an address at which a read/write operation is intended for, and compares the address designated by the address indicator word to its assigned addresses; when the address designated by the address indicator word is an address associated with the device module, the device module read/writes from/to the address designated by the address indicator word. Memory controller (ring controller or master bus) is not required to ‘know’ which memory chip/device module in a daisy chain the address command word is intended for. Therefore, system embodiments allow streaming without consideration of a number of memory chips/device modules on bus.

Abstract: The invention relates to an automated system in which a targeted search may be made for connecting terminals without having to actuate a load connected thereto. For this purpose, the automated system has a communication network, a programmable control unit, and at least one modular bus subscriber which are connected to the communication network. The modular bus subscriber has multiple groups of connecting elements, a display element being associated with each group of connecting elements. An evaluation and control unit is also provided which actuates at least one selected display element in response to signaling information originating from the programmable control unit. The programmable control unit is designed to provide this type of signaling information.

Abstract: Systems and methods for encoding a slot table for a communications controller of a communications network are described. In one embodiment, a method for encoding a slot table for a communications controller of a communications network includes classifying branches of the communications network that are connected to the communications controller into at least one group, where each of the at least one group includes multiple branches, and generating a slot table entry for a time slot for accessing the communications network through the communications controller based on the at least one group. Other embodiments are also described.

Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.

Abstract: A close proximity memory arrangement maintains a point to point association between DQs, or data lines, to DRAM modules employs a clockless state machine on a DRAM side of the memory controller-DRAM interface such that a single FIFO on the memory controller side synchronizes or orders the DRAM fetch results. Addition of a row address (ROW-ADD) and column address (COL-ADD) strobe reducing latency and power demands. Close proximity point to point DRAM interfaces render the DRAM side FIFO redundant in interfaces such as direct stacked 3D DRAMs on top of the logic die hosting the memory controller. The close proximity point to point arrangement eliminates the DRAM internal FIFO and latency scheme, resulting in just the memory controller internal clock domain crossing FIFOs.

Abstract: A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus.

Abstract: One aspect of the invention relates to a network node for connecting to a Local Interconnect Network (LIN). In accordance with one example of the present invention, the network node includes a bus terminal which is operably coupled to a data line for receiving a data signal, which represents serial data, via that data line. The data signal is a binary signal having high and low signal levels. The network node further includes a receiver circuit which employs a comparator to compare the data signal with a reference signal. The comparator generates a binary output signal representing the result of the comparison. The network node also includes a measurement circuit that receives the data signal and provides a first voltage signal such that it represents the high signal level of the data signal.

Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.

Abstract: A method and system for network interface naming is described.

Abstract: A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency.

Abstract: A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.

Abstract: A data storage system includes a first server including: a first plurality of storage disks configured to store data, and a first host bus adapter including a first processor configured to provide a first virtual expander and a first logic component; and a second server including: a second plurality of storage disks configured to store data, and a second host bus adapter including a second processor configured to provide a second virtual expander and a second logic component, wherein the first host bus adapter of the first server is coupled to the second host bus adapter of the second server via a SAS connection, and wherein each of the first plurality of storage disks and the second plurality of storage disks are accessible by each of the first server and the second server.

Abstract: A semiconductor device includes a plurality of bus lines, a plurality of bus bar lines grouped in pairs with the plurality of bus lines, respectively, and a parameter register including a plurality of parameter groups coupled to the plurality of bus lines and a plurality of bus bar lines, wherein the parameter groups store parameters for different operating modes.

Abstract: A technology for implementing a method to build a virtual device as at least one of a virtual Peripheral Controller Interconnect (PCI) device or a virtual Input/Output (I/O) device is disclosed. A method of the disclosure includes receiving a request for a PCI compatible device. The method further includes building a virtual device based on the request for the PCI compatible device, where the virtual device is built as at least one of a virtual PCI device or a virtual I/O device.

Abstract: A storage network includes at least one storage processor. At least one switch is coupled to the at least one storage processor. At least one nontransparent bridge is coupled to the at least one switch. The at least one nontransparent bridge includes at least one addressable endpoint. At least one storage device is coupled to the nontransparent bridge. At least one baseboard management controller is coupled to the at least one addressable endpoint.