Abstract: This invention provides a device and method for enhancing flexibility of interface between 3G communication module and application processor. The device comprises the 3G communication module, the AP and an interface transfer module connected between them, wherein the interface transfer module is configured to perform bus transfer. A bus interface of the 3G communication module adapted to voice service data and a bus interface of the AP adapted to voice service data are directly connected. The bus transfer in the present invention is: the interface transfer module converts the bus data format of the non-voice service data adapted to the 3G communication module or the AP into the bus data format of the non-voice service data adapted to the AP or the 3G communication module. With this invention, the 3G communication module can be connected with various APs conveniently, and the generality of the 3G communication module is improved.

Abstract: Apparatus and associated methods for a simplified multi-client initiator/target within a SAS device. Features and aspects hereof provide a simplified initiator/target component to enable cost reduction and simplification of SAS devices requiring only limited initiator/target functionality. In one embodiment, a SAS expander may incorporate simplified SSP/STP/SMP initiator/target features and aspects hereof to permit simple management of devices coupled to the expander or coupled downstream through other expanders. The simplified multi-client initiator/target suffices for simple management functions while reducing cost and complexity of the SAS expander. Features and aspects hereof may be implemented with shared circuits for each of multiple client protocols coupled with firmware operable in a general or special purpose processor embedded in the SAS device.

Abstract: A subsea broadcast serial bus system includes a broadcast serial bus having a first signal line and a second signal line. One or more nodes are connected in parallel to the first signal line and the second signal line of the broadcast serial bus. Each node connects the first signal line to the second signal line via a node impedance. A subsea node connected to the broadcast serial bus includes an adjustable impedance that may be adjusted based on the number of nodes connected to the broadcast serial bus.

Abstract: An apparatus for identification of an input data against one or more learned signals is provided. The apparatus comprising a number of computational cores, each core comprises properties having at least some statistical independency from other of the computational, the properties being set independently of each other core, each core being able to independently produce an output indicating recognition of a previously learned signal, the apparatus being further configured to process the produced outputs from the number of computational cores and determining an identification of the input data based the produced outputs.

Abstract: A control apparatus has a number of modules arranged next to one another in a longitudinal direction. The modules each comprise at least one module part having a housing. Furthermore, the module part comprises a first electrical bus connector on a first side of the housing for electrical connection to a first neighboring module part adjacent in the longitudinal direction, and a second electrical bus connector on a second side, opposite the first side, of the housing for electrical connection to a second neighboring module part adjacent in the longitudinal direction. The module part further comprises at least one movable element, movable between a first position and a second position. In the first position, the movable element provides an electrical connection between the first bus connector and the second bus connector and, in the second position, provides an insulation point between the first bus connector and the second bus connector.

Abstract: A diabetes management system is provided that supports connectivity of applications residing on a medical device. The diabetes management system includes a medical device that performs a diabetes care function in relation to a patient and a diabetes care management device in data communication with the medical device. The diabetes care management device is comprised generally of a connection management module and at least one application separate from the connection management module. The connection management module is configured to receive an associate request from the medical device and operable to establish a data connection with the medical device in accordance with IEEE standard 11073, such that the applications interacts with the connection management module to communicate via the data connection with the medical device.

Abstract: A USB-to-SDIO bridge (UTSB) to efficiently transmit SD/SDIO commands in USB packets. The UTSB may allow the majority of the device drivers for a given SD/SDIO device to remain intact, requiring changes only in the lowest hardware adaptation layer to put a USB wrapper around native SD commands. These commands may be sent over USB-to-SD card reader devices that may include various embodiments of a UTSB, where they may be unwrapped and transmitted to the SD port as if the port were native to the host controller. Additionally, the SD/SDIO commands may be packaged into groups of commands, or transactions, to optimize performance. The host driver may instruct the UTSB bridge device to repeatedly read data from the SDIO device until a communications FIFO on the device is empty (corresponding to a termination condition), and return the collected data to the host.

Abstract: A method for determining a topology based on input/output criteria includes selecting a predefined topology, measuring the fitness of the topology, and breeding individuals from the topology by combining elements from the fittest individuals. The topology is then updated with the new individuals and the fitness of the new topology is measured. Iterations continue similarly until certain criteria are met.

Abstract: A micro grid apparatus and a method for forming the micro grid apparatus. A selected complex shape is placed on a circuit board. At least two irregular shaped modules are selected. Each selected irregular shaped module is inserted into a respective docking bay of the complex shape to form the micro grid apparatus on the circuit board. The micro grid apparatus includes a central area and at least three radial arms connected to the central area. The radial arms are external to and integral with the central area. Each radial arm extends radially outward from the central area. Each pair of adjacent radial arms defines a docking bay. The central area includes at least two processors that are linked together wirelessly or by direct electrical connection. The at least two processors are linked wirelessly or by direct electrical connection to each inserted irregular shaped module.

Abstract: Structures and methods are disclosed relating to a multi-protocol transceiver including lane-based Physical Coding Sublayer (“PCS”) circuitry that is configurable to adapt to one of a plurality of communication protocols. Particular embodiments of the present invention include lane based configurable data paths through PCS transmit and receive circuitry.

Abstract: A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.

Abstract: The present invention is a method for providing multi-pathing via Small Computer System Interface Input/Output (SCSI I/O) referral between an initiator and a storage cluster which are communicatively coupled via a network. The method includes receiving an input/output (I/O) at a first target device from the initiator via the network. The I/O includes a data request. The method further includes transmitting a SCSI I/O referral list to the initiator when data included in the data request is not stored on the first target device, but is stored on a second target device. The referral list includes first and second port identifiers for identifying first and second ports of the second target device respectively. The first and second ports of the target device are identified as access ports for accessing the data requested in the data request.

Abstract: A subscriber node of a communication system, a communication system and a method for transmitting a message in the communication system. The message is transmitted from a first subscriber node of the communication system via a data bus of the communication system to a second subscriber node of the communication system. An application program of the first subscriber node files the message, that is to be sent, in a message memory, from where it is retrieved by a communication controller, upon a sending command of the application program, and is transmitted via the data bus.

Abstract: A method for visually mapping network ports to network interface cards, applied to a network device having a plurality of network ports and a plurality of network interface cards, is provided. A network port layout corresponding to a configuration of the plurality of network ports on the network device is received. An unplugging order of the plurality of network ports is provided according to the network port layout. Numbers of the plurality of network interface cards are recorded according to an occurrence order of unplugging events occurring in the plurality of network interface cards when unplugging the plurality of network ports according to the unplugging order into an unplugging event record. The numbers of the plurality of network interface cards are combined into the network port layout according to the unplugging event record to generate a network port mapping layout Then the network port mapping layout is displayed.

Abstract: An electronic device includes a device connected to a bus controller, a memory that stores a program, and a processing unit that executes access to the device through the bus controller according to the program. The processing unit generates a prediction value of executing access to the device based on the result of executing access in the past in parallel with the access to the device, and executes, prior to completing access to the device, using the prediction value of the execution of the access to the device, post-processing of the access to the device using the result of executing access to the device when a number of times which the result of executing access in the past matches a prediction value of execution of access in the past reaches a specified number of times.

Abstract: A method according to one embodiment may include discovering, by software, at least one variable from at least one component populated on a shelf system. The method may also include performing, by the software, at least one shelf management function based on at least one variable. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: In an embodiment, a host computing device includes an internal display and also includes a connector to connect to an external display. A cable is provided to connect to the connector and to connect to the external display. The cable includes video processing capabilities. For example, the cable may include a memory configured to store a frame buffer. The frame buffer may store a frame of video data for further processing by the video processing device in the cable. The video processing device may manipulate the frame in a variety of ways, e.g. scaling, rotating, gamma correction, dither correction, etc.

Abstract: A method includes providing a non-motherboard level Input/Output (I/O) interface in a data processing device including a processor communicatively coupled to a memory, and providing a driver component of an external processor in the memory of the data processing device and/or a memory associated with the external processor. The method also includes installing the driver component in the data processing device to render the data processing device compatible with the external processor, and coupling the external processor to the data processing device through the non-motherboard level I/O interface to provide boosting of processing through the data processing device, thereby dispensing with a need to make a motherboard level modification in the data processing device therefore.

Abstract: A circuit arrangement includes a plurality of functional units each of which comprises a plurality of data processing modules and a local controller. The plurality of data processing modules run a common system clock and are connected by a streaming data bus running a handshake-type streaming data transfer protocol. A profiling module of the circuit arrangement assesses control signals tapped at predefined interfaces of the streaming data bus during real time operation, for determining link performance and communication patterns for profiling and debugging purposes, and hence constitutes a simple and low cost approach for assessing intra-component and inter-component link performance and communication patterns on large SoCs. A method for profiling data flow for use in such a circuit arrangement is also provided.

Abstract: One embodiment includes an I/O multiplexer bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O multiplexer bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.

Abstract: Apparatus and methods are provided for alleviating processing requirements of a central computer in a vessel. Each apparatus is placed in close proximity to one or more pieces of electronic equipment implementing a legacy interface. The apparatus processes data to and from the electronic equipment, including converting data to formats consistent with the formats used by the intended recipient.

Abstract: A electronic device includes a bus, two electronic elements connected to the bus, and a controller. Each of the two electronic element is designated a logic unit number (LUN) and a first temporary buffer identified by the LUN for storing messages transmitted from or to the corresponding electronic element by the bus. The controller for obtaining the LUN of the message transmitted from/to the at least two electronic element, determining the temporary buffer which the message is stored according to the obtained LUN, storing the message to the determined temporary buffer, and transmitting the message stored in the temporary buffer to the corresponding electronic element or processing the message stored in the temporary buffer.

Abstract: Provided is a Field Programmable Gate Array (FPGA) application merging system for multiple platforms of a same series, which is used in a testing or manufacturing system comprising an adapter and at least two platforms. The FPGA application merging system comprises: at least two functional modules corresponding to the at least two platforms respectively; an IO selector connected to the at least two functional modules respectively, configured to select one of the at least two functional modules adaptively; and an IO attribute controller connected to the IO selector, configured to select an attribute in accordance with the selected functional module, wherein each IO has a three-state logic attribute. The FPGA application merging system may significantly reduce the cost of the FPGA version in later development, maintenance, storage, upgrading and so on, mitigate the difficulty of storage, loading and other operations on the board, and significantly increase the operation efficiency.

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract: Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.

Abstract: A method for communication between function modules in drive engineering is described, wherein a first function module has a first sensor interface, wherein a second function module has a second sensor interface, wherein the first sensor interface is functionally assigned to the second sensor interface, wherein the first function module is assigned to a first automation component, wherein the second function module is assigned to a second automation component, wherein an address, in particular a logical address, for the transfer of sensor data is automatically specified.

Abstract: A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: A semiconductor device comprising an interface logic module for transmitting data frames across an interface, and controller logic module arranged to control a rate at which the interface logic transmits data across the interface. Upon receipt of data frames to transmit across the interface, the controller logic module is arranged to determine a sequence of data rates with which to transmit sequential data frames across the interface, and to configure the transmission of the data frames across the interface according to the determined data rate sequence. The selection of these data rates will be dependent on specific critical RF frequencies where EMI impacts have to be minimized.

Abstract: The present invention permits an I/O port to be used with a variety of different I/O devices, regardless of their device type implementation. Thus, one set of pins may be used for various different I/O devices.

Abstract: In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

Abstract: There is disclosed a system and method executable in a wireless mobile communication device for dynamically configuring processing speed for a main processor in the device during device initialization. In an embodiment, the method comprises: initiating a boot-rom procedure; determining whether a battery is present in the device, and in response to the presence of the battery, determining whether the battery charge level is above a predetermined threshold; determining whether a USB connection to the device is present, and in response to the presence of a USB connection, enumerating the USB connection; and wherein, in response to the presence of the battery and the battery charge level being above a predetermined threshold, or in response to the USB connection being enumerated at a higher current, the processing speed of the main processor is increased.

Abstract: A data storage device (DSD) is disclosed comprising a SATA connector and control circuitry comprising a communication module for communicating with a host. At least one pin of the SATA connector is evaluated to detect a host type. When the host type is SATA, the communication module is configured to operate according to a SATA protocol, and when the host type is non-SATA, the communication module is configured to operate according to a non-SATA protocol.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus.

Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Abstract: A high-speed data transmission interface circuit used in a network switch device is provided. The high-speed data transmission interface circuit comprises a main circuit hoard, a connector and a daughter circuit board. The main circuit board comprises a transmission port interface module and a first wire. The transmission port interface module comprises a reduced pin extended attachment unit interface (RXAUI). The first wire connects the connector and the main circuit board. The daughter circuit board comprises a high definition multimedia interface (HDMI) module and a second wire. The HDMI module is connected to an external network device through a HDMI signal wire. The second wire connects the connector and the HDMI module. The transmission port interface module communicates with the external network device through the connector and the daughter board.

Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.

Abstract: A wireless base station that performs wireless communication with a mobile terminal is connected to a plurality of time information notification servers. The wireless base station selects any of a plurality of pieces of time information notified from a plurality of time information notification servers, respectively, and corrects an internal clock based on the selected piece of time information. This can keep the internal clock of the wireless base station highly accurate.

Abstract: Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.

Abstract: A method for sharing data contained on a peripheral device amongst a plurality of blade servers is disclosed. The method includes storing a copy of data from a peripheral device to a memory device. The memory device is partitioned into at least ‘n’ memory areas, each memory area storing one copy of the data. The method also includes assigning one of the at least ‘n’ memory areas to each of a plurality ‘n’ of servers. The method also includes establishing communication between the plurality of servers and the plurality of assigned memory areas via a switch controller. The switch controller is configured to access the plurality of assigned memory areas via a processor.

Abstract: Systems and methods for streaming data. Systems allow read/write across multiple or N device modules. Device modules on a bus ring configure at power up (during initialization process); this process informs each device module of its associated address values. Each ringed device module analyzes an address indicator word, which identifies an address at which a read/write operation is intended for, and compares the address designated by the address indicator word to its assigned addresses; when the address designated by the address indicator word is an address associated with the device module, the device module read/writes from/to the address designated by the address indicator word. Memory controller (ring controller or master bus) is not required to ‘know’ which memory chip/device module in a daisy chain the address command word is intended for. Therefore, system embodiments allow streaming without consideration of a number of memory chips/device modules on bus.

Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched.

Abstract: Nowadays, many architectures have processing units with different bandwidth requirements which are connected over a pipelined ring bus. The proposed invention can optimize the data transfer for the case where processing units with lower bandwidth requirements can be grouped and controlled together for a data transfer, so that the available bus bandwidth can be optimally utilized.

Abstract: In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.

Abstract: An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller configured to control a position in said queue to which said respective responses to said requests are written. The position is controlled such that the responses are read out of said queue in an order which corresponds to an order in which the requests are issued.

Abstract: A computer system arrangement for minimizing communication and integration complexity between a plurality of software applications having each an individual data model defining an individual set of application parameters, includes a bus arrangement having connections to each one of said plurality of applications, the bus being arranged to interpret between each application and to orchestrate incoming and outgoing requests from each application, the bus arrangement including, a generic information model defining a set of generic parameters in relation to the application parameters of each application, an adaptor together with said generic information model, in connection with an incoming request, arranged to map parameters of that individual data model to said generic parameters, a device arranged to transfer the mapped generic information model together with the request to a process execution engine, which includes a device arranged to handle the request to identify a corresponding adaptor to which the reques

Abstract: A bus node for an electric coupling of a bus system to a functional module arrangement, having an electronic circuit for converting electrical signals between a bus protocol provided by the bus system and an internal communications protocol provided by the functional module arrangement, and having a first coupling means for electrically connecting the electronic circuit to the functional module arrangement, and having a second coupling means for electrically connecting the electronic circuit to the bus system, wherein the first coupling means comprises a first contact means that is configured for a direct electrical contact with a ground connection of the functional module arrangement.

Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Abstract: A method for computing includes connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and includes multiple connection pins that are specified by the standard, including a plurality of ground pins. At least one pin, selected from among the pins on the bus that are specified as the ground pins, is used in order to indicate to the peripheral device that the host device has an extended operational capability.