Abstract: A storage network includes at least one storage processor. At least one switch is coupled to the at least one storage processor. At least one nontransparent bridge is coupled to the at least one switch. The at least one nontransparent bridge includes at least one addressable endpoint. At least one storage device is coupled to the nontransparent bridge. At least one baseboard management controller is coupled to the at least one addressable endpoint.

Abstract: Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.

Abstract: A detecting circuit includes a network interface, a switch, a baseboard management controller (BMC) having first and second signal pins, and a detecting unit. The first and second signal pins receive low level signals when the network line is disconnected from the network interface. The first signal pin receives a high level signal and the second signal pin receives a low level signal when the network line is connected to the network interface but the network card is malfunctioning. The first and second signal pins receive high level signals when the network line is connected to the network interface and the network card works normally.

Abstract: A system and method for facilitating smart power meter monitoring are provided. The system for facilitating smart power meter monitoring includes a standards-based frame detector, a CDR, at least one 8b/10 encoder/decoder and data links to receive input signals and transmit output signals. The system provides for the conversion of incoming SerDes signals, like those that may be transmitted from an optical module, into UART signals that can be communicated to the smart power meter directly through a UART port of the meter. The method includes receiving SerDes signals from an optical module and converting the signals to UART signals. The UART signals are converted to comply with industry standard protocols for communication with the smart power meter. The UART signals are then transmitted to the smart power meter through the meter's UART port.

Abstract: A system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device. In operation, a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being known by the device. Further, the plurality of write commands are ordered in the determined order.

Abstract: An image processing apparatus includes a chipset unit which processes data; a connector which includes a plurality of terminals, and is configured to connect with a cable so that the chipset unit can transmit and receive a signal to and from an external device; a switching unit which supplies power to the external device through a first terminal of the connector, and selectively controls a switching operation regarding whether or not to supply power to the first terminal on the basis of a signal state of a second terminal of the connector when the cable is connected to the connector. A control method of the image processing apparatus is also disclosed.

Abstract: A disk array for a storage system that includes a dual controller disk array and a server includes a disk frame and two controller nodes. Each controller node includes a switch, where a port of the switch is connected to a port of a switch of a peer controller node. Each controller node is configured to detect whether the peer controller node is invalid through the port. When it has been detected that the peer controller node is invalid, a local controller node enables the peer controller node to send, through the port of the switch of the peer controller node, received data from the server to a port of a switch of the local controller node.

Abstract: An underlaying device includes a main signal port, an expanding signal port, a signal process component, and a power connector. The main signal port is receiving and sending a communication signal from/to the computer device by means of a main signal wire. The expanding signal port is receiving and sending the communication signal from/to an external expanding device. The signal process component is coupled between the main signal port and the expanding signal port for transforming the communication signal into a signal which is able to be received and sent between the main signal port and the expanding signal port. The power connector is supplying power by means of a power wire. The underlaying device is suitable for various computer devices and is able to integrate the functionality of connection ports.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: A system includes a plurality of processors, a message fabric, and a plurality of hardware units. Each of the plurality of processors comprises a plurality of communication FIFOs and has an instruction set including at least one instruction to send a message via at least one of the plurality of communication FIFOs. The message fabric couples the processors via at least some of the plurality of communication FIFOs . Each of the processors is associated with a respective one or more of the hardware units and coupled to each of the associated hardware units via respective hardware unit input and output communication FIFOs. Each of the processors is enabled to send messages to others of the processors via respective processor output communication FIFOs. The respective hardware units associated with each of the processors are enabled to send messages to the associated processor via the respective hardware unit input communication FIFOs.

Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.

Abstract: An information-processing method performed in an information-processing apparatus, the information-processing apparatus performing wireless communication with a first apparatus and wire communication with a second apparatus, the information-processing method including the steps of: transmitting an interrupt signal to the second apparatus by using the wire communication when data is received from the first apparatus; receiving, by using the wire communication, a clock signal from the second apparatus which receives the interrupt signal; and transmitting and receiving, by using the wire communication, data between the information-processing apparatus and the second apparatus.

Abstract: A method includes, in a memory system that includes a host and a storage device connected by a bus interface, assessing in the storage device a power supply state of the memory system. In the storage device a latency tolerance is selected for the bus interface based on the assessed power supply state. The selected latency tolerance is indicated from the storage device to the host, for application to the bus interface.

Abstract: A storage device with multiple interfaces and multiple levels of data protection includes a first memory area and a second memory area utilizing data protection for protecting second data stored in the second memory area, the second memory area being distinct from the first memory area. The storage device also includes a first interface through which the storage device writes first data into the first memory area or reads first data stored in the first memory area and a second interface through which the storage device writes second data into the second memory area or reads second data stored in the second memory area, the second interface being distinct from the first interface. A controller controls access to the first memory area and the second memory area, and the second memory area is inaccessible through the first interface.

Abstract: A bridge circuit may be used to interface between dynamically reconfigurable circuitry and dedicated circuitry or other circuitry having static configurations during normal operation of the device. The bridge circuit may include interface circuitry coupled between first and second interfaces that communicate with the dynamically reconfigurable circuitry and the dedicated circuitry. Control circuitry may control the interface circuitry based on variable communications requirements of the second interface without interrupting communications with the dedicated circuitry at the first interface. The variable communications requirements may be dependent on which configuration of the dynamically reconfigurable circuitry is currently implemented.

Abstract: A device includes a bus interface to couple to a shared bus of a sensor network. The device also includes a sensor interface to couple to a sensor of the sensor network. The device further includes a gated pulse width modulation circuit coupled to the bus interface and to the sensor interface. The gated pulse width modulation circuit is configured to transmit, during a time slot determined based on a timing signal received via the shared bus, an analog pulse width modulated representation of a signal received from the sensor.

Abstract: A high-current Multi-Port USB hub has a microcontroller that selectively switches the hub between low current synchronizing state and high current charging state. During charging state in excess of two Amps of current can be provided to each device connected to the hub. Each USB port circuit includes a power FET to selectively provide current to the USB port according to the state of the hub. Current sensors on each of the USB ports detects an amount of current being drawn by a device connected to the USB port. Each USB port is provided with indicators to indicate the charged state of the device connected to that port. The charge state of the device is also provided to the microcontroller which provides a summary status indication of the set of devices connected to the USB hub.

Abstract: Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.

Abstract: CPU architecture is modified so that content of the interrupt mask register can be changed directly based on a decoding result of an instruction decoder of a CPU. Such modification does not require a great deal of labor in changing a CPU design. In addition, an extended CALL instruction and an extended software interrupt instruction are added to the CPU, and each of the extended CALL instruction and the extended software interrupt instruction additionally has a function of changing the value of the interrupt mask register. Atomicity is achieved by: allowing such a single instruction to concurrently execute a call of a process and a value change of the interrupt mask register; and disabling other interrupts during execution of the single instruction.

Abstract: Embodiments of the present invention provide a method, an apparatus, and a system for performing time synchronization on PCIE (PCI Express, peripheral component interconnect express) devices. The method mainly includes: a PCIE device receiving, through a hardware interface, a time synchronization signal sent from a clock source device; parsing, by the PCIE device, the time synchronization signal to obtain clock information carried in the time synchronization signal, and using the clock information as a clock of the PCIE device. The PCIE devices are supported to access a synchronous network, and the PCIE devices are supported to be used as a global clock source.

Abstract: Method and system for configuring a serial interface. The system includes one or more input nodes each coupled to a corresponding serial bus. One or more output nodes are coupled to a respective serial bus, each output node having a respective driver. A voltage detection circuit determines the voltage at a configuration node. Mode of serial bus operation is based on the voltage level detected at the configuration node. In at least one mode of serial bus operation, the configuration node is used as a mode select input and power source for at least one output driver.

Abstract: Systems and methods for streaming data. Systems allow read/write across multiple or N device modules. Device modules on a bus ring configure at power up (during initialization process); this process informs each device module of its associated address values. Each ringed device module analyzes an address indicator word, which identifies an address at which a read/write operation is intended for, and compares the address designated by the address indicator word to its assigned addresses; when the address designated by the address indicator word is an address associated with the device module, the device module read/writes from/to the address designated by the address indicator word. Memory controller (ring controller or master bus) is not required to ‘know’ which memory chip/device module in a daisy chain the address command word is intended for. Therefore, system embodiments allow streaming without consideration of a number of memory chips/device modules on bus.

Abstract: In accordance with embodiments of the present disclosure, an interface for an information handling system comprising a connector, wherein the connector comprises a legacy portion and an expanded portion. The legacy portion may comprise a plurality of signal pins defining a first set of lanes of communication between the information handling system and an information handling resource coupled to the connector. The expanded portion comprising a plurality of signal pins defining a second set of lanes of communication between the information handling system and an information handling resource coupled to the expanded portion.

Abstract: A microcontroller for a control unit or a vehicle control unit, includes a central processing unit (CPU), at least one interface-unspecific input module, at least one interface-unspecific output module, at least one routing unit and at least one arithmetic unit for processing interface-specific information. The microcontroller is configurable so that the at least one interface-unspecific input module, the at least one interface-unspecific output module, the at least one routing unit and the at least one arithmetic unit for processing interface-specific information fulfill the functions corresponding to one of multiple serial interfaces, in particular of SPI, UART, LIN, CAN, PSI5, FlexRay, SENT or Ethernet. In addition, the arithmetic unit is configured to generate an entire output message frame from the second payload data as output data and to transmit the same to the interface-unspecific output module.

Abstract: This invention is a low level programmable logic that can communicate with Media Independent Interface (MII) (Ethernet) interface in a highly configurable manner under the control of a CPU. This invention is highly configurable for various existing and new Ethernet based communication standards, programmable in an easy to learn assembly language, low power and high performance.

Abstract: Techniques are disclosed relating to coding data in an apparatus. In one embodiment, the apparatus includes a coder circuit coupled to a data bus, where the coder circuit is configured to receive an indication that data is being transmitted over the data bus from a first circuit to a second circuit. The coder circuit is configured to perform a coding operation on the data in response to receiving the indication. In some embodiments, the coder circuit is configured to operate in a mode in which the coder circuit captures data of a data transmission via the data bus without being specified as a participant of the data transmission. When the coder circuit is not operating in the mode, the coder circuit is not configured to capture data of a data transmission without being specified as a participant of the data transmission.

Abstract: An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.

Abstract: A distributed server system is disclosed that can handle multiple networked applications. A system can include at least one main processor; a plurality of offload processors connected to a memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch configured to receive memory read/write data over the memory bus.

Abstract: Systems, methods, and other embodiments associated with unified information bus are described. One example method includes receiving a unified information object that includes data and associated meta-data; identifying an object type for the unified information object, selecting one or more data transfer components that perform operations on the identified object type and transferring the unified information object to the one or more selected data transfer components.

Abstract: A chip package includes a micro-link between components disposed on a substrate. The micro-link may be an ultra-short multi-conductor transmission line with shared reference planes that results in a distribution of impedance values. Furthermore, the composite signal traces in the transmission line each can support communication of one symbol at a time by ensuring that multiple reflections reach a substantial fraction of a steady-state value within a symbol time. In this way, the micro-link may facilitate continued scaling of the communication bandwidth between the components with low latency to increase the performance of computer systems that include the chip package.

Abstract: This invention relates to a method, a computer program product, an apparatus and a system for switching a first switching unit of an apparatus into a state out of a set of states, wherein said apparatus comprises a first serial interface and a second serial interface, each of this first and second serial interfaces comprises at least one data line and a power supply line, and wherein said first switching unit is coupled to the power supply line of both said first serial interface and said second serial interface, wherein said set of states comprises a first state for connecting the power supply of said first serial interface to the power supply of said second serial interface, and a second state for connecting the power supply of said first serial interface to a first further power supply line, said first further power supply line being configured to be connected to a first power supply.

Abstract: The invention relates to a bus coupler which converts a network-specific telegram arriving from an external network to an internal data telegram which transmits only the payload data from the network-specific telegram. The internal data telegram also contains at least one state information field for internal control information. The internal data telegram is transferred from the bus coupler to an internal bus system to which multiple bus users are connected in series. Each bus user connected to the internal bus system is able to monitor, in a decentralized and preferably autonomous manner, the communication quality of the lower-level bus system, and to initiate actions, depending on the implementation, on the basis of the internal control information received from the bus coupler, the internal control information generated by the particular bus user, and/or the internal control information received from the directly adjacent bus users.

Abstract: A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data redriving/retiming circuits connected to the D/Q terminals of the plurality of DRAM chips. The data redriving/retiming circuits may provide isolation between a system memory bus and the D/Q terminals of the DRAM chips.

Abstract: A system and method embodying some aspects for communicating between nodes in a network-on-chip are provided. The system comprises a microprocessing chip and a plurality of connection paths. The microprocessing chip comprises sixteen processing nodes disposed on the chip. The plurality of connection paths are configured such that each is at most three hops away front any other node. Each node also has connection paths to at most three other nodes.

Abstract: An electronic device includes a housing, or a ‘cover’, the housing material molded into a desired target shape and to at least partially embed a plurality of functional elements and an enabling arrangement, optionally at least partially embedded in the housing, the enabling arrangement including: a first connector with a first plurality of connecting elements to establish a connection between the plurality of functional elements and the enabling arrangement, a second connector with one or more second connecting elements to be connected a host device utilizing the functionalities associated with the functional elements, a memory for storing and retrieval of instructions, and processing elements capable of transforming signals from a one known format to another predetermined format according to stored instructions. A corresponding method is presented.

Abstract: A data communication system is provided. The data communication system includes a data bus, and a line replacement unit including a terminal controller, and a plastic optical fiber serial interface module (POFSIM) coupled between the terminal controller and the data bus. The POFSIM is configured to transmit digital optical signals to the data bus based on electrical signals received from the terminal controller, and transmit electrical signals to the terminal controller based on digital optical signals received from the data bus.

Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.

Abstract: A method of communication between a master circuit and two slave circuits over a serial bus wherein: the two slave circuits simultaneously transmit their associated identifiers; the two slave circuits simultaneously transmit the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine an order of communication between the two circuits.

Abstract: An interfacing device is configured to process one or more rules, based on sensor data, to perform a predetermined action. During operation, the device can receive a device configuration that includes a rule for the interfacing device. The rule can include an action description for performing an action, and can include a condition that takes sensor data as input and indicates criteria for performing the action. The device can store the rule in a rule repository, and determines a remote interfacing device that generates data associated with the rule's condition. The device can also subscribe to the data from the remote interfacing device.

Abstract: A monitoring system including a first and a second portion. The first portion includes a controller for receiving a code sequence. The first portion is configured to connect the system to a common data bus. The first portion is configured to provide a synchronization signal to the second portion when the two portions are in a predetermined position. The second portion includes a controller for providing the code sequence to the first portion and the first portion being further configured to output the code sequence for verification by a verification entity.

Abstract: The present invention relates to an improved USB connection cable, comprising: a first electrical connector, a second electrical connector and a third electrical connector, wherein the first electrical connector is used for connecting to a host computer, the second electrical connector is adopted for connecting to a first electronic device, and the third electrical connector is adopted for connecting to a second electronic device; Moreover, by way of electrically connecting the internal pins of the first USB electrical connector to the internal pins of the second USB electrical connector and the third USB electrical connector, the first USB electrical connector is able to transmit data to the second USB electrical connector and the third USB electrical connector, respectively; such that the improved USB connection cable can not be a media for data transfer used between the electronic device having an USB 3.0 electrical connector and the host computer with an USB 3.

Abstract: A mechanism for facilitating configuration of port-type Peripheral Component Interconnect Express/Serial Advanced Technology Attachment host controller architecture is described. In one embodiment, an apparatus includes a plurality of PHYs to be used as Peripheral Component Interconnect Express (PCIe) ports and Serial Advanced Technology Attachment (SATA) ports, and logic to facilitate swapping of one or more of the plurality of PHYs between being the PCIe ports and the SATA ports.

Abstract: In one embodiment a system comprises an integrated circuit, a plurality of voltage regulators; and a data bus coupled to the integrated circuit and the plurality of voltage regulators. In some embodiments the integrated circuit comprises logic to embed a timing signal on the data bus. Other embodiments may be described.

Abstract: A conversion module contains an asynchronous analog-to-digital converter (AADC) with the output signal generated at irregular time intervals, whose output is connected to the input of the buffer memory module (BUF), and the output of the buffer memory module (BUF) is connected through the internal bus (BUS) simultaneously to the source address module (SADR), to the configuration registers module (REG), to the control module of the interface (CM), which the reference generator (RG) is connected to, and to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and moreover the control inputs/outputs (1, 2, . . .

Abstract: A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

Abstract: A method for a covert communication system comprising a pair of flash memory devices having encrypted boot instructions and communication software thereon whereby the flash memory devices once plugged into a computer's USB ports and the computer is powered on, the flash memory boot load tests for the presence of a flash memory device dongle having an encrypted key that that once validated starts the encrypted communication software designed to create, edit, send and receive a report comprising data files forming a data package, which can only be transmitted by restarting the computer.

Abstract: An apparatus and method for operating a connector of a mobile terminal are provided. The apparatus includes a connector including a plurality of pins, a plug of a peripheral device, a display unit for displaying a menu for setting a connector mode, an input unit for receiving selection of one connector mode from the menu for setting a connector mode, a main processor for connecting with a switch unit through a data line, a sound line, a microphone line, and a control line, for receiving connector mode selection information from the input unit, and for transferring switching information through the control line, and the switch unit for connecting with a subset of the pins of the connector, and selectively connecting the subset of the pins to at least one of the data line, the sound line, and the microphone line.

Abstract: Embodiments of a system and method are disclosed. One embodiment is an I2C compatible device. The I2C compatible device includes an SDA interface for connection to an SDA line and a single-line I2C module configured to transmit a sync word from the SDA interface over the SDA line and following the sync word, to transmit I2C data from the SDA interface over the SDA line such that digital data is communicated via a single line. In an embodiment, the sync word is a sync byte+NACK.

Abstract: Retrieval of status information from a remote device performed on a host system is provided, wherein the remote device is connected to the host system via a bus system comprising at least two signal lines terminated with resistors on the host system side and on the remote device side. The retrieval method includes: activating a sensing phase; sensing the at least two terminated signal lines during the sensing phase; and determining operating state of the remote device based on the sensing result; wherein at least a first operating state representing a connected and powered remote device is detectable.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.