Abstract: A given port at a storage controller is used for communication with storage devices. In response to an indication that at least a portion of the given port is to be dedicated to a group of at least one of the storage devices, the storage controller divides the given port into multiple smaller ports.

Abstract: An IEEE 802.3 compliant physical layer device provides efficient loading of configuration information of the physical layer device. The configuration information is written into a volatile memory in the physical layer device, and then uploaded to at least one EEPROM. The configuration information is downloaded to the volatile memory during startup of the physical layer device. The system controller can also directly access the EEPROMs, bypassing the volatile memory. By providing a bridge between the system controller and the EEPROMs and providing additional bits in the volatile memory of the physical layer device, the system controller can read and write the EEPROMs one byte at a time. During reset time, the content of the EEPROMs is written to registers in the physical layer device to configure the physical layer device.

Abstract: USB apparatus suitable for interconnection with a USB host having a D? bus coupled to ground via a pull-down resistance, the USB apparatus including a microcontroller having a first port and a second port, the first port being coupled via a resistance to a voltage source and a switch, operated by the microcontroller via the second port, selectably interconnecting the first port and the bus of the USB host.

Abstract: There is provided an information processing apparatus including one host controller which communicates with other devices via multiple ports, a monitoring unit which monitors an amount of traffic for each of the ports, a processing unit which gives notification of an required amount of traffic for performing predetermined processing by a device connected to a certain port of the multiple ports, and a communication control unit which controls an amount of traffic for each of the ports, based on a required amount of traffic, notification of which is given from the processing unit, and an actual amount of traffic acquired by the monitoring unit.

Abstract: In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer, detecting the assertion signal in the accelerators and communicating a request for a lock, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer. Other embodiments are described and claimed.

Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

Abstract: A system and method for providing redundant video signals from a server blade in a blade center. A blade center is described that includes a capture system for capturing a video stream off a PCI-x bus in a server blade and delivering the pair of video streams to a midplane in the blade center; and a switch module that inputs the pair of video streams and generates an unroutable video signal and a routable video signal.

Abstract: Systems and methods for trace multicast across a bus structure are provided. Preferably, the bus structure is that of a System-on-a-Chip (SoC), where the SoC includes a number of master components and a number of slave components connected via the bus structure. The bus structure supports a trace multicast feature. In one embodiment, the bus structure receives a bus transaction from a master component and, in response, outputs the bus transaction to a corresponding slave port. In addition, the bus structure determines whether a trace multicast is desired for the bus transaction. If a trace multicast is desired, the bus structure generates an additional bus transaction having one or more transaction attributes that include a translated version of the bus transaction and outputs the additional bus transaction to a trace slave port of the bus structure. The trace multicast feature provides a non-invasive mechanism for driver-level trace.

Abstract: In an embodiment, a host computing device includes an internal display and also includes a connector to connect to an external display. A cable is provided to connect to the connector and to connect to the external display. The cable includes video processing capabilities. For example, the cable may include a memory configured to store a frame buffer. The frame buffer may store a frame of video data for further processing by the video processing device in the cable. The video processing device may manipulate the frame in a variety of ways, e.g. scaling, rotating, gamma correction, dither correction, etc.

Abstract: In a network protocol processing system in which variables of each of TCP transmission processing and TCP reception processing depend on each other, asynchronous parallel processing is realized between a transmission processing block and a reception processing block for updated protocol processing. Specifically, the system includes a high priority queue for transferring control data to be processed with high priority, a low priority queue for control data other than the above control data, and priority control means for distributing the control data to two kinds of queues. When a request for session establishment and the session disconnection of a new TCP session is issued from an application during transmission of TCP data, data related with the session establishment and the session disconnection is notified preferentially through the high priority queue, and other control data is transferred through the low priority queue.

Abstract: In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver.

Abstract: Methods, apparatuses, and computer program products for dynamically determining a primary or slave assignment based on an order of cable connection between two devices are provided. Embodiments include detecting, by a first device, insertion of one end of a cable into a port of the first device; determining, by the first device, whether a power signal is received from the cable at the port of the first device; if the power signal is received, performing, by the first device, a data transfer operation over the cable as a slave device to a second device that is coupled to the other end of the cable; and if the power signal is not received, performing, by the first device, a data transfer operation over the cable as a primary device to the second device that is coupled to the other end of the cable.

Abstract: A processor-based system, including systems without keyboards, may receive user inputs prior to booting. This may done using the graphics controller to generate a window which allows the user to input information. The system firmware may then compare any user inputs, such as passwords, and may determine whether or not to actually initiate system booting.

Abstract: A pattern detector for a bus node for a system bus having a plurality of stations that are coupled together by means of an arrangement of bus lines, the bus node comprising: decoding circuitry configured for an analysis of sub-patterns in a stream of data on at least one bus line, and analyzing circuitry configured to determine a series of digital relative length information of said sub-patterns, wherein said relative length information is generated by comparison of an actual sub-pattern with a preceding sub-pattern in the stream of data on said at least one bus line.

Abstract: An apparatus includes multiple media processing modules and a control unit. The media processing modules are configured to exchange digital media signals over a shared bus. The control unit is configured to determine a desired connectivity scheme among the media processing modules, to adaptively define, based on the desired connectivity scheme, connections that transfer the media signals among the media processing modules over the shared bus, and to instruct the media processing modules to establish the connections, by communicating with the media processing modules over a control interface that is independent of the shared bus.

Abstract: In accordance with embodiments of the present disclosure, a system may include a driver, a plurality of drops, and a plurality of transmission lines, including one transmission line between the driver and one of the plurality of drops and one transmission line between successive adjacent drops. Each particular transmission line of the plurality of transmission lines may be manufactured to have a desired impedance based on a corresponding effective impedance as seen at a drop located on an end of the particular transmission line furthest from the driver in a direction away from the driver.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: Provided is a two-way RAID controlled storage device of a serial attached small computer system interface/serial advanced technology attachment (PCI-Express) type, which provides data storage/reading services through a PCI-Express interface. The RAID controller typically comprises multiple sets of RAID equipment coupled to one another via a hardware host connect, an adaptive host interface controller, a host connect controller, a two-way RAID controller, a disk connect controller, an adaptive disk mount controller, and a hardware disk connect. Coupled to the hardware disk connect are a set of DDR, SSD memory disk units. Further, each set of RAID equipment typically comprises a programmable host interface unit, a disk controller, a high speed host interface, a disk monitoring unit, a disk plug and play controllers, and a programmable disk mount.

Abstract: In an embodiment, an apparatus comprises a bus network having a set of lines, and a number of communication system devices associated with a number of electronics equipment connected to the bus in which each communication system device configures the electronics equipment to send and receive a plurality of signals on a line of the set of lines in a noise region of the set of lines.

Abstract: A method to interact with a local USB device is disclosed. Messages are transmitted to a remote host controller driver from a host controller associated with the local USB device. Messages are received from the remote host controller driver for the host controller. In some embodiments, a transfer descriptor prototype is received from the remote host controller driver. A completed transfer descriptor is received from the remote host controller driver. The completed transfer descriptor and the transfer descriptor prototype are transformed into a modified transfer descriptor in part by using a collection of rules. The modified transfer descriptor is submitted to the local host controller without intervention from the remote host controller driver.

Abstract: Circuits, methods, and apparatus that reduce the power consumed by transactions initiated by a number of USB host controllers. Peripheral devices on a number of USB networks are accessed in a coordinated manner in order to reduce power dissipated by a CPU and other circuits when reading data needed by the host controllers. The resulting memory reads are temporally clustered. This allows the CPU to process a greater number of requests each time it leaves a low-power state. As a result, the CPU may possibly remain in a sleep state for a longer period of time, thus saving power. This is accomplished at the host controller level by synchronizing the time frames used by each host controller in a system. The synchronizing signal may be one or more bits of a frame count provided by one host controller to a number of other frame controllers.

Abstract: There is provided a field device performing a communication through a communication line. The field device includes: first circuits involved with a smart communication; second circuits involved with a fieldbus communication; a token detecting circuit that detects a token in the fieldbus communication; and a control circuit. The control circuit is operable to: i) cause the second circuits to operate when the token is detected within a given time by the token detecting circuit; and ii) cause the second circuits not to operate when the token is not detected within the given time by the token detecting circuit.

Abstract: Computer readable storage mediums, electronic devices, and accessories having stored thereon data structures. A data structure includes a pin selection field operable to identify a connector pin and cause a host device to select one of a plurality of communication protocols for communicating with an accessory over the identified connector pin. The data structure also includes an accessory capability field defining an accessory identifier that uniquely identifies the accessory.

Abstract: An invention for generating a slot table entry address for a communications device of a communications network includes a method that involves processing a slot counter value according to a configuration setting value to produce a processed slot counter value, the slot counter value identifying a time slot of data communications of the communications network, masking a cycle counter value according to the configuration setting value to generate a masked cycle counter value, where the cycle counter value identifies a communications cycle containing the time slot, and processing the processed slot counter value and the masked cycle counter value to generate a slot table entry address such that a corresponding slot table entry of the time slot of the communications cycle in a slot table is accessed by the communications device at the slot table entry address.

Abstract: A device for distributing data about a vehicle, has a first sensor data reception interface for receiving first sensor data from a first sensor, a second sensor data reception interface for receiving second sensor data from a second sensor, and a transmission interface for transmitting the data about the vehicle on the basis of the first sensor data and the second sensor data to a receiver. A vehicle and an on-board system which incorporate the devise are also encompassed herein.

Abstract: An electronic device provided with a multimedia interface having a cross-device control function and a general-purpose serial bus interface is provided with a control unit that prohibits the use of the cross-device control function whenever an external device is connected via the general-purpose serial bus interface during a state permitting control by the cross-device control function from an image display device connected via the multimedia interface.

Abstract: A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface.

Abstract: A subscriber of a communication system includes a microprocessor, at least two communication controllers and a peripheral bus. The microprocessor is connected to the communication controllers via the peripheral bus and is also connected via the communication controllers respectively to a communication link of the communication system, via which messages are transmitted. In order to optimize the gateway functionality within the subscriber, a provision is made that at least one of the communication controllers has an active interface via which the communication controller is connected to the peripheral bus and has a logic circuit for independently implementing a gateway functionality.

Abstract: Methods and apparatus for implementing a port management protocol which can be used to manage communication between one or more USB devices and a USB host at a distance greater than that allowed by the USB Specifications are provided. In one aspect, a method for prolonging a bus event of a USB device at least until a notification is received that a corresponding bus event has been completed by the USB host is provided; and subsequently exchanging bus traffic between the USB host and USB device upon completion of the bus event by both devices.

Abstract: Methods and devices for manipulating HDMI-CEC messages transmitted over a network including at least two HDMI-CEC display devices with their associated at least two HDMI-CEC cluster trees that at least partially overlap, and enabling each of the HDMI-CEC display devices to communicate using HDMI-CEC with its associated HDMI-CEC cluster tree according to its current HDMI-CEC network view.

Abstract: A transmission interface system includes a connector; a detecting unit, a control unit, a chipset and a resetting unit. The connector includes lots of transmission interfaces. The detecting unit detects the data type of the current transmitting data and outputs a detecting signal; the control unit receives the detecting signal and informs the resetting unit to output a resetting signal to the chipset. The chipset is reset after receiving the resetting signal, and then the control unit informs the chipset to output a data signal corresponding to the data type of the current transmitting data to the connector.

Abstract: The invention relates to an automation device, with which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The device has a microcontroller (110), which is assigned at least one clock generator (120) and one memory unit (150), and which is connected at least to one data source (140), which is designed to output a data bit-stream to be transmitted.

Abstract: A method for data transmission by telegram via a fieldbus of process automation technology, wherein information is transmitted via the fieldbus in the form of data in at least one telegram, and wherein the information, especially the same information, is transmitted in the at least one telegram in a first data format and in a second data format, wherein the first data format differs from the second data format.

Abstract: A node having a node input is configured to receive a plurality of transactions intended for a plurality of different targets. The node has multiple node outputs. At least one target is provided, that target including an input configured to receive a respective output of the node. The node is configured to direct transactions to the at least one target or an output (for passing to a different partition) depending on whether the transactions are intended for the target or a different target. This determination is made in response to a conversion operation which converts a target address of the transaction to an identification associated with the target or the output.

Abstract: A method for communication over an SMB, I2C bus, or other serial bus between an auxiliary display subsystem and a secondary processor of a notebook including the auxiliary display subsystem, and systems, circuits and notebooks configured to perform the method. Typically, communication over the serial bus between the auxiliary display subsystem and secondary processor can occur when the notebook is in a standby or other low-power state (e.g., to obtain system status data or cause the notebook to wake up) or a fully-powered normal operating state. Typically, the auxiliary display subsystem is coupled not only to the notebook's secondary processor by the serial bus but also to the notebook's central processing unit by another link (e.g., a USB).

Abstract: In accordance with an embodiment, a method of operating a bus interface circuit includes detecting a start sequence on a plurality of input terminals, determining whether a first input terminal and a second input terminal is a data terminal and a clock terminal, respectively, or whether the first input terminal and the second terminal is a clock terminal and a data terminal, respectively. The method also includes routing the first input terminal to a data terminal and the second input terminal to a clock terminal if first input terminal and the second input terminal are determined to be a data terminal and a clock terminal, respectively, and routing the first input terminal to the clock terminal and the second input terminal to the data terminal if first input terminal and the second input terminal are determined to be a clock terminal and a data terminal, respectively.

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract: The present invention provides a method and apparatus for controlling the operating condition of a peripheral device based on the mode of interconnection of the peripheral device of a host device. The apparatus includes a first connector for connecting the peripheral device, a second connector for connecting the host device and a coupling system operatively interconnecting contacts of the first connector and contacts of the second connector. The coupling system is further configured to provide a supply signal to the peripheral device via the first connector, wherein the supply signal is at least in part indicative of one or more characteristics of the power available to the peripheral device from the host device. The supply signal may provide a means for the peripheral device to control operation thereof in light of the characteristics of the power available.

Abstract: A method and an apparatus for providing a configurable, object-oriented, protocol-neutral interface between a physical device and a server. The method includes coupling an application gateway with the physical device, where the application gateway includes a protocol gateway module configured for physical communication with the physical device, and an object adapter module configured for virtual communication between the physical device and a client application running on a server. The method further includes configuring a service starter to launch and bind the object adapter module with the protocol gateway module, configuring the protocol gateway module to define the physical interface between the physical device and the protocol gateway, and establishing communication between the protocol gateway module and the physical device, such that the physical device is exposed as a network device on the server.

Abstract: Implementations of discovery functionalities in accordance with the present invention are characterized by being exceptionally minimalistic. A primary reason and benefit for such minimalistic implementations relate to these discovery functionalities being implemented via a management processor and associated resources of a system on a chip (SoC) unit as opposed to them being implemented on data processing components of a cluster of nodes (i.e., central processing core components). By focusing on such a minimalist implementation, embodiments of the present invention allow discovery functionalities to be implemented on a relatively low-cost low-power management processor coupled to processing cores that provide for data serving functionality in the cluster of nodes.

Abstract: Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream.

Abstract: Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.

Abstract: An ExpressCard adapter able to accept a PCI-E-type or a USB-type ExpressCard in a single ExpressCard slot includes the ExpressCard slot, a PCI-E port, a data conversion unit, a switch unit, and a detection unit. The data conversion unit is connected to the PCI-E port, and converts between USB data and PCI-E data. The switch unit connects the ExpressCard slot to the PCI-E port or to the data conversion unit. The detection unit detects the type of ExpressCard which is inserted and controls the switch unit to connect the ExpressCard slot either to the PCI-E port or to the data conversion unit as required.

Abstract: A bus interconnect interfaces a host system to a radio frequency (RF) generator that is coupled to a plasma chamber. The bus interconnect includes a first set of host ports, which are used to provide a power component setting and a frequency component setting to the RF generator. The ports of the first set of host ports are used to receive distinct variables that change over time. The bus interconnect further includes a second set of generator ports used to send a power read back value and a frequency read back value to the host system. The bus interconnect includes a sampler circuit integrated with the host system. The sampler circuit is configured to sample signals at the ports of the first set at selected clock edges to capture operating state data of the plasma chamber and the RF generator.

Abstract: A processing circuit comprises a plurality of modules connected in series to form a module pipeline. Each module comprises one or more registers having corresponding addresses within an address range for the module. A register request, including a target register address, is passed from one module to succeeding modules down the module pipeline until the register request is received at the module containing the targeted register. Data is written into or read out from the targeted register.

Abstract: Computing unit enclosures are often configured to connect units (e.g., server racks or trays) with a wired network. Because the network type may vary (e.g., Ethernet, InfiniBand, and Fibre Channel), such enclosures often provide network resources connecting each unit with each supported network type. However, such architectures may present inefficiencies such as unused network resources, and may constrain network support for the units to a small set of supported network types. Presented herein are enclosure architectures enabling flexible and efficient network support by including a backplane comprising a backplane bus that exchanges data between the units and a network adapter using an expansion bus protocol, such as PCI-Express.

Abstract: A verified cluster configuration is collected and stored by a central management entity. Servers within the cluster are connected to network cables, where each of the servers has at least one network port and memory storing a port identification code for each network port, and where each network cable has memory storing a cable identification code. For each verified connection between a network cable and a network port, the port identification code is stored in the memory of the network cable and the cable identification code is stored in the memory of the corresponding server. The data identifying each connection is stored by the central management entity and includes the port identification code for a particular network port in association with the network cable identification code for the corresponding network cable. Any miswiring of the configuration is identified by the central management entity and easily corrected by the administrator.

Abstract: A device for exchanging data between at least two data consuming and/or emitting applications, has two modules with input/outputs connected to a corresponding application each including two internal communication submodules respectively for emission and for reception; a control module; a synchronization clock; and a closed-loop transmission line, each submodule for emission including an emission FSM circuit with an emission request output connected to the module, an emission authorization request input connected to an output of the module, and an output interface for data attached to the application A1, A2 that is linked therewith, each submodule for reception including a reception FSM circuit with a reception request input connected to an output of the module and an input interface for the data attached to the application that is linked therewith, elements also being provided for coupling the output and input interfaces with the transmission loop.

Abstract: An orthogonal layout generation method can include receiving, in a computer system, data related to a plurality of devices for a schematic layout, generating, in the computer system, a node for each of the plurality of devices, hereby generating a plurality of nodes, generating, in the computer system, a link for each of the plurality of nodes, thereby generating a plurality of links, orthogonalizing, in the computer system, the plurality of nodes, initializing, in the computer system, a route for each of the plurality of links, thereby generating a plurality of routes, orthogonalizing, in the computer system, the routes and selecting, in the computer system, a direction for each of the plurality of routes.

Abstract: A circuit arrangement for signal pick-up and signal generation and a method for operating this circuit arrangement. The circuit has at least one timer module for providing a time basis to a plurality of time control modules connected to it, and has a time routing unit, which is connected to it for the interconnection of the named modules and their signals.