Abstract: One embodiment of a method includes loading, by a memory controller, a boot image from a solid state drive to an operating memory of a computing system during an initialization operation of the computing system. The initialization operation initializes components of the computing system.

Abstract: The solid state drive device includes a memory device including a plurality of flash memories and a memory controller connected with a host and configured to control the memory device. The memory controller includes first and second cores, a host interface configured to interface with the host, and a flash memory controller configured to control the plurality of flash memories. The first core is configured to control transmission and reception of data to and from the host. The second core is configured to control transmission and reception of data to and from the memory device.

Abstract: A virtual logical unit that stores learning metadata is allocated in a first storage server having a first plurality of clusters, wherein the learning metadata indicates a type of storage device in which selected data of the first plurality of clusters of the first storage server are stored. A copy services command is received to copy the selected data from the first storage server to a second storage server having a second plurality of clusters. The virtual logical unit that stores the learning metadata is copied, from the first storage server to the second storage server, via the copy services command. Selected logical units corresponding to the selected data are copied from the first storage server to the second storage server, and the learning metadata is used to place the selected data in the type of storage device indicated by the learning metadata.

Abstract: A storage controller calculates an access frequency of each logical disk; that is selects a first logical disk device of which the access frequency exceeds a first predetermined value, the first logical disk device being allocated to a first physical disk device; selects a second logical disk device which has the access frequency equal to or less than a second predetermined value, the second logical disk device being allocated to a second physical disk device; and reallocates the first and second logical device; and reallocates the first and second logical devices to the second and the first physical disk device, respectively.

Abstract: Memory management units (MMUs) are disclosed. In one aspect, an MMU may have a first interface to a component. The first interface may receive one of a read of updated data from, and a write of updated data to, a virtual memory address. The virtual memory address may initially correspond to a first physical memory location in an only one time programmable (OTP) non-volatile memory (NVM). The MMU may have a remapping unit to remap a correspondence of the virtual memory address from the first physical memory location to a spare physical memory location. The MMU may also have a second interface to the OTP.NVM. The second interface may allow the updated data to be read from or written to the spare physical memory location of the OTP NVM. Methods performed by the MMUs, and methods and articles useful for manufacturing MMUs, are also disclosed.

Abstract: A method and an apparatus for selecting one or more applications running in a data processing system to reduce memory usage according to information received from the applications are described. Notifications specifying the information including application specific memory management capabilities may be received from the applications. A status of memory usage indicating lack of available memory may be determined to notify the selected applications. Accordingly, the notified applications may perform operations for application specific memory management to increase available memory.

Abstract: The storage apparatus comprises a storage unit storing data read/written by the host apparatus, and a control unit controlling writing of the data to the storage unit. The control unit configures one or more pools from the storage unit and divides one of the pools into first pages having an area of a first size and divides the first pages into second pages having the second area, and manages the pages, manages a data storage area of a first volume storing the data by using the first-size area and manages a data storage area of a second volume storing the data by using the second-size area, assigns the first page to the data storage area of the first volume, and assigns the first page in units of the second volume and assigns the second page obtained by dividing the first page to the data storage area of the second volume.

Abstract: Methods and apparatus for dispatching memory operations are disclosed. An example memory controller for controlling operation of a data storage device includes a command dispatcher that dispatches memory operation commands for execution by a plurality of memory devices. The command dispatcher includes a command buffer that separately and respectively queues the memory operation commands by maintaining a respective linked list of memory operation commands for each memory device. The command dispatcher also includes a selection circuit with a plurality of leaf nodes. Each leaf node corresponds with one of the linked lists and indicates whether its corresponding linked list includes memory operation commands awaiting dispatch. The selection circuit also includes an OR-reduction tree that reduces the plurality of leaf node indications to a root node indication. The selection circuit iterates over the nodes of the OR-reduction tree to select memory operation commands for dispatch by the command dispatcher.

Abstract: Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.

Abstract: Computer system having cache subsystem wherein demote requests are performed by the cache subsystem. Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.

Abstract: Storage management systems and methods are presented. In one embodiment, a storage management method comprises: establishing a cluster including one or more logical unit number storage components (LUNs) communicatively coupled to one or more host nodes, wherein one of the one or more nodes is a master host node; performing a LUN naming process wherein a master host node assigns a name to each of the one or more LUNs respectively, even if the one or more LUNS are communicatively coupled to a slave host node; and operating the cluster, wherein the one or more host nodes refer to the one or more LUNs by the name. In one embodiment, the master host node stores information associated with the name in a computer readable medium. The cluster can include one or more slave host nodes.

Abstract: A method can include receiving memory configuration information that specifies a memory configuration; receiving memory usage information for the memory configuration; analyzing the received memory usage information for a period of time; and, responsive to the analyzing, controlling notification circuitry configured to display a graphical user interface that presents information for physically altering a specified memory configuration. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: A network device allocates a particular number of memory blocks in a ternary content-addressable memory (TCAM) of the network device to each database of multiple databases, and creates a list of additional memory blocks in an external TCAM of the network device. The network device also receives, by the external TCAM, a request for an additional memory block to provide one or more rules from one of the multiple databases, and allocates, by the external TCAM and to the requesting database, an additional memory block from the list of additional memory blocks.

Abstract: A management system is coupled to a storage system group including a scale-out storage system (a virtual storage system). The management system has storage management information, which includes information denoting, for each storage system, whether or not a storage system is a component of a virtual storage system. The management system, based on the storage management information, determines whether or not a first storage system is a component of a virtual storage system, and in a case where the result of this determination is affirmative, identifies, based on the storage management information, a second storage system, which is a storage system other than the virtual storage system that includes the first storage system, and allows a user to perform a specific operation only with respect to this second storage system.

Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.

Abstract: A storage system includes a first storage apparatus and a second storage apparatus including a second controller for sequentially transferring a copy of the part of the segments of data from a second buffer into a second storage device segment by segment in the same sequence as the second buffer have received a copy of the part of segments of data from a first buffer of the first storage apparatus. The second controller producing a backup copy in a backup data storage portion by copying a copy of one of the segments of the data stored in the second storage device that has been transferred from the second buffer into the second storage device while transferring a copy of the subsequent segment of the data next to said one of the segments of the data in the sequence from the second buffer to the second storage device.

Abstract: Systems, methods, and devices for efficient cache coherence between memory-sharing devices are provided. In particular, snoop traffic may be suppressed based at least partly on a table of block tracking entries (BTEs). Each BTE may indicate whether groups of one or more cache lines of a block of memory could potentially be in use by another memory-sharing device. By way of example, a memory-sharing device may employ a table of BTEs that each has several cache status entries. When a cache status entry indicates that none of a group of one or more cache lines could possibly be in use by another memory-sharing device, a snoop request for any cache lines of that group may be suppressed without jeopardizing cache coherence.

Abstract: An apparatus includes a nonvolatile memory, an interface that at least receives an erase command of the nonvolatile memory, a first controller that controls the nonvolatile memory to execute data erasing on the basis of the erase command output from the interface, an external input unit which is installed independently of the interface, a second controller that controls the nonvolatile memory to execute data erasing on the basis of an erase instruction signal output from the external input unit, and a change-over circuit that switches between connection of the first controller with the nonvolatile memory and connection of the second controller with the nonvolatile memory, wherein the second controller controls the nonvolatile memory to execute data erasing on the basis of the erase instruction when the connection of the second controller with the nonvolatile memory is established by the change-over circuit.

Abstract: Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.

Abstract: A data processing system includes a host computer that executes a storage-aware component which (1) dynamically determines a need of the host computer for data storage resources of a necessary size and a necessary class, and (2) generates a storage allocation request message representing a request by the host computer that data storage resources of the necessary size and the necessary class be allocated to the host computer. The necessary class is one of a set of classes of a predetermined class-of-storage (CoS) scheme by which storage resources in the data processing system are classified. The details and complexity of the CoS scheme may vary from system to system. A data storage system communicatively coupled to the host computer includes available data storage resources of at least the necessary size and the necessary class which can be allocated for use by the host computer.

Abstract: A memory reset system including a first memory socket and a second memory socket. A reset signal generator can generate a reset signal to the first memory socket. A dampener circuit can receive the reset signal from the reset signal generator and transmit a dampened reset signal to the second memory socket.

Abstract: A solid state disk (SSD) caches disk-based volumes in a heterogeneous storage system, improving the overall storage-system performance. The hottest data blocks are identified based on two factors: the frequency of access, and temporal locality. Temporal locality is computed using a logarithmic system time. IO latency is reduced by migrating these hottest data blocks from hard-disk-based volumes to the solid-state flash-memory disks. Some dedicated mapping metadata and a novel top-K B-tree structure are used to index the blocks. Data blocks are ranked by awarding a higher current value for recent accesses, but also by the frequency of accesses. A non-trivial value for accesses in the past is retained by accumulating the two factors over many time spans expressed as a logarithmic system time. Having two factors, access frequency and the logarithmic system time, provides for a more balanced caching system.

Abstract: Created is transfer order information indicating an order of transfer from multiple memory areas in accordance with an order of logical addresses and memory locations which are specified by read commands. Readout from the multiple memory areas in accordance with the transfer order information is performed by controlling memory controllers in accordance with the created transfer order information.

Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.

Abstract: A method of managing a memory of an apparatus, the apparatus executing one or more processes using the memory. The method comprises maintaining a plurality of lists of identifiers, wherein each list has an associated size value and an associated threshold corresponding to a maximum number of identifiers in that list, wherein each identifier identifies a corresponding region of the memory that had been allocated for a process but that is currently not required by any of the one or more processes, and wherein the size of a region of the memory identified by an identifier of a list equals the size value associated with that list.

Abstract: Activity level of memory pages is repeatedly classified in a virtual machine environment, so that live VM migration can be carried out more efficiently. The time intervals upon which the activity level of the memory pages are repeatedly classified can be dynamically adjusted to better align its performance with the live VM migration process.

Abstract: A method of managing memory may include selecting an object of a memory heap to be de-allocated and initiating a deferred lock configured to delay de-allocation of the object. The deferred lock may be acquired in response to a thread leaving a computing space, and the object may be de-allocated.

Abstract: In one embodiment, the semiconductor device includes a data control unit configured to selectively process data for writing to a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a write operation, the group of processing functions including at least three processing functions. The enabled processing function may be performed based on a signal received over a single pin associated with the group of processing functions. In another embodiment, the semiconductor device includes a data control unit configured to process data read from a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a read operation. Here, the group of processing functions including at least two processing functions.

Abstract: A method for regulating I/O requests in a RAID storage system may comprise: receiving a first request to access a first set of one or more logical block addresses (LBAs) of a RAID volume; receiving a second request to access at least one of the first set of one or more LBAs of the RAID volume; and queuing the second request. A system for regulating I/O requests in a RAID storage system may comprise: means for receiving a first request to access a first set of one or more logical block addresses (LBAs) of a RAID volume; means for receiving a second request to access at least one of the first set of one or more LBAs of the RAID volume; and means for queuing the second request.

Abstract: Disclosed is a method of operating a data storage system. The method comprises generating first metadata describing storage of a volume of data in a first storage volume, storing the volume of data within a second storage volume, generating second metadata describing storage of the volume of data in the second storage volume, and processing the first metadata and the second metadata to increase sparseness of the volume of data stored in the second storage volume.

Abstract: In one embodiments, one or more first computing devices receive updated values for user data associated with a plurality of users; and for each of the user data for which an updated value has been received, determine one or more second systems that each have subscribed to be notified when the value of the user datum is updated and each have a pre-established relationship with the user associated with the user datum; and push notifications to the second systems indicating that the value of the user datum has been updated without providing the updated value for the user datum to the second systems.

Abstract: A data storage device is disclosed including a non-volatile media having a plurality of physical locations for storing user data, each physical location associated with a logical block address (LBA), a translation table having a plurality of entries, each entry having a mapping of one or more LBAs to a corresponding number of physical locations on the non-volatile media. The data storage device further includes control circuitry that divides the translation table into a plurality of segments, each segment including a group of entries corresponding to a range of LBAs, determines a first score for each segment using a first metric, and selects a segment for defragmentation by utilizing the first score for each segment.

Abstract: A dispersed storage unit within a dispersed storage network is configured with registry information including a slice name assignment indicating a range of slice names assigned to a vault associated with at least one user of the dispersed storage network. The slice names further corresponding to a plurality of potential data slices to be subsequently created and received for a pillar of the vault. The dispersed storage unit allocates a portion of physical memory therein to store the potential data slices based on the slice name assignment.

Abstract: A data block may be moved between a first medium and a second medium. The movement of the data block involves measuring the access characteristic of the data block as the data block is stored on the first medium. The performance characteristics of the first medium and the second medium are then determined, in which each performance characteristic has a static performance characteristic component and a dynamic performance characteristic component. Alternatively or concurrently, the static performance characteristic components of the first medium and the second medium may be compared, and the dynamic performance characteristic components of the first medium and the second medium are compared. Accordingly, the data block is moved from the first medium to the second medium when at least one of these comparisons indicate that the second medium is more suitable for storing the data block having the access characteristic than the first medium.

Abstract: A method of processing data for storage in a storage medium coupled to a processing unit adapted to access data stored in the storage medium as one or more pages of data, each page having a predetermined page size and a corresponding virtual memory address, the method comprising: obtaining a compressed data item including compressed data corresponding to a first memory page of uncompressed data; dividing the compressed data item into an initial part and a supplementary part, the initial part having an initial part size; determining respective second memory locations for the supplementary parts so as to reduce the number of sectors occupied by the supplementary parts; allocating the initial part together with an index data item at a first memory location associated with the first memory page, the index data item being indicative of a second memory location; allocating the supplementary part at the second memory location.

Abstract: A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance.

Abstract: A non-volatile storage system is provided with reduced delays associated with loading and updating a logical-to-physical mapping table from non-volatile memory. The mapping table is stored in a plurality of segments, so that each segment can be loaded individually. The segmented mapping table allows memory access to logical addresses associated with the loaded segment when the segment is loaded, rather than delaying accesses until the entire mapping table is loaded. When loading mapping segments, segments can be loaded according to whether there is a pending command or by an order according to various algorithms.

Abstract: A method, system and computer program product are provided for implementing feedback directed Non-Uniform Memory Access (NUMA) mitigation tuning in a computer system. During a page frame memory allocation for a process, predefined monitored performance metrics are compared with stored threshold values. Responsive to the compared values, selected use of local memory is dynamically modified during the page frame memory allocation.

Abstract: A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage devices and hosts. The storage control layer includes: a first virtual layer interfacing with the hosts, operable to represent a logical address space characterized by logical block addresses and available to said hosts and characterized by an Internal Virtual Address Space (IVAS) and operable, responsive to a configuration or I/O request addressed to the logical block addresses, to translate said logical block addresses into IVAS addresses; and a second virtual layer interfacing with the physical storage devices, operable to represent an available physical space to said hosts and characterized by a Physical Virtual Address Space (PVAS), addresses in PVAS having corresponding address in IVAS. The second virtual layer is operable to translate said respective IVAS addresses into addresses in the physical address space.

Abstract: Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.

Abstract: A method for performing a write to a volume x in a cyclic point-in-time-copy architecture is described. In one embodiment, such a method includes determining whether the volume x has a child volume. The method then determines whether the target bit maps (TBMs) of both the volume x and the child volume are set. If the TBMs are set, the method finds a higher source (HS) volume from which to copy the desired data to the child volume. Once the HS volume is found, the method determines whether the HS volume and the child volume are the same volume. If the HS volume and the child volume are not the same volume, the method copies the data from the HS volume to the child volume. The method then performs the write to the volume x. A corresponding computer program product is also described.

Abstract: A data storage system having a slow tier and a fast tier maintains hot data on the fast tier by migrating data from the slow tier to reserve space on the fast tier as data becomes hot over time. The system maintains a reserve space table and performs a mass migration of data from the fast tier to the slow tier. Data migration is frequently unidirectional with data migrating from the slow to the fast tier, reducing overhead during normal operation.

Abstract: A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, associated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.

Abstract: Reversing a communication path between a first volume on a first storage device and a second volume on a second storage device includes suspending communication between the first and second volumes while maintaining operations for other volumes of the storage devices, causing the first volume to change from a source volume to a destination volume without destroying the first volume, causing the second volume to change from a destination volume to a source volume without destroying the second volume, and resuming communication between the first and second volumes. Causing the first volume to change from a source volume to a destination volume may include modifying a table of the first storage device. Causing the second volume to change from a source volume to a destination volume may include modifying a table of the second storage device.

Abstract: Methods for managing a single memory pool comprising frame buffer memory and display list memory are presented. The single memory pool can comprise sub-pools including: a super-block pool comprising a plurality of super-block objects; a node pool comprising a plurality of node objects; and a block-pool comprising a plurality of blocks. The method may comprise: receiving a memory allocation request directed to at least one of the sub-pools; allocating an object local to the sub-pool identified in the memory request, if local sub-pool objects are available to satisfy the memory request; allocating an object from super-block pool, if the memory request is directed to the node-pool or block-pool and there are no available local objects in the respective sub-pools to satisfy the memory request; and applying at least one of a plurality of memory freeing strategies, if the sub-pools lack available free objects.

Abstract: A memory device and method for performing a write-abort-safe firmware update are disclosed. In one embodiment, a location in a memory of a memory device for a firmware update is allocated. The firmware update is written into the allocated location in the memory. A pointer is written to the firmware update in a directory, and a pointer is written to the directory in a location in the memory that is read during boot-up. In another embodiment, a block in a memory of a memory device is allocated for updated file system data comprising a firmware update and a directory. The updated file system data is written into the allocated location in the memory. A pointer is written to the firmware update in the directory, and a pointer is written to the updated file system data in a boot block in the memory, wherein the boot block is read during boot-up.

Abstract: A method for automatically optimizing an allocation amount for a data set includes receiving an extend request, specifying an allocation amount, for a data set in a storage pool. The method increments a counter in response to receiving the extend request. In the event the counter has reached a threshold value, the method automatically increases the allocation amount of the extend request, such as by multiplying the allocation amount by a multiplier. In the event the allocation amount is larger than a largest free extent in the storage pool, the method automatically decreases the allocation amount of the extend request to correspond to the largest available free extent. Such a method reduces or eliminates the chance that an extend request will fail, and reduces overhead associated with extending and consolidating extents. A corresponding apparatus and computer program product are also disclosed herein.

Abstract: Disclosed is a method and apparatus for allowing a user to select, from a plurality of partitions on a memory device, which partitions may be visible to hosts connecting to the memory device.

Abstract: A method to implement parallel, single-pass compaction in a garbage collector is described. In one embodiment, such a method includes conducting a planning phase for multiple regions to be compacted. During the planning phase, the method determines new locations for data entities in the multiple regions. The method then performs a move phase for the multiple regions to move the data entities to their new locations. During the move phase, the method initiates multiple compaction threads to move the data entities to their new locations. While executing, the compaction threads dynamically build a dependency graph of the regions being compacted. The dependency graph guarantees that no data entity is moved to its new location until all data entities that it overwrites have been moved to their new locations. A corresponding computer program product and apparatus are also disclosed herein.

Abstract: Provided is a computer system capable equalizing the storage capacity immediately and reliably to multiple real logical areas dynamically providing storage capacity to virtual logical areas. This computer system is characterized by, during the course of executing an operation of dynamically allocating a storage area to a virtual volume in response to an access from a host system, detecting an occasion where balance of a storage capacity among a plurality of logical areas is disrupted; and subsequently moving the storage area among a plurality of logical areas to maintain balance of the storage capacity.