Abstract: In various embodiments, methods and systems are disclosed for integrating a remote presentation protocol with a datagram based transport. In one embodiment, an integrated protocol is configured to support lossless or reduced loss transport based on Retransmission (ARQ) combined with Forward Error Correction (FEC). The protocol involves encoding and decoding of data packets including feedback headers and FEC packets, continuous measurement of RTT, RTO and packet delay, dynamically evaluating loss probability to determine and adjust the ratio of FEC, congestion management based on dynamically detecting increase in packet delay, and fast data transmission rate ramp-up based on detecting a decrease in packet delay.

Abstract: In iterative decoding, a data recovery scheme corrects for corrupted or defective data by determining reliability metrics for blocks of decoded data. Block or windowed detectors generate block reliability metrics for data blocks (rather than individual bits) of decoded data using soft information from the regular decoding mode or from new iterative decoding iterations performed during error recovery mode. An error recovery system triggers corrective decoding of selected data blocks based on the block reliability metrics, by for example, comparing the block reliability metrics to a threshold or by selecting an adjustable number of the least reliable data blocks.

Abstract: A method includes receiving a Code Division Multiple Access (CDMA) carrier carrying at least a pilot channel. Differences are computed between selected soft pilot symbols received on the pilot channel. Based on the computed differences between the selected soft pilot symbols received on the pilot channel, a level of noise is estimated for a data channel that is to be transmitted on the CDMA carrier.

Abstract: A method which makes use of the syndrome information at each iteration, combined with the bit reliability information available at a FEC decoder, to extract the minimum estimated bit error configuration, i.e. the block which is closest to the transmitted codeword during the decoding process, and to select such block if the result at the final decoding iteration has a higher number of estimated bit errors.

Abstract: An encoding method changes an encoding rate of an erasure correcting code. One cycle is defined as 12k bits (wherein k represents a natural number) which is an encoding output using LDPC-CC with an encoding rate of ½, and includes information and parity. From the one cycle, only the information is arranged in the output order of the encoding output to obtain 6k bit information X6i, X6i+1, X6i+2, X6i+3, X6i+4, X6i+5, . . . , X6(i+k?1) X6(i+k?1)+1, X6(i+k?1)+2, X6(i+k?1)+3, X6(i+k?1)+4, and X6(i+k?1)+5. Known information is inserted in 3k pieces of information (Xj) among the 6k bit information, so that when 3k pieces of mutually different j is divided by 3, there is a remainder of 0 regarding k pieces, there is a remainder of 1 regarding k pieces, and there is a remainder of 2 regarding k pieces, to thereby obtain the parity from the information containing the known information.

Abstract: The embodiments include an error correction processing unit and an error correction history recording unit. The error correction processing unit performs an error correction process based on data read from a non-volatile semiconductor memory and a second-step error correction code corresponding to the data. The error correction history recording unit records error correction history indicating whether first error correction is successful through the first error correction process, in association with unit data. When error correction history of target unit data to be read indicates that correction is not successful, the second error correction process is executed without executing the first error correction process.

Abstract: A convolutional encoder (50) comprises an expurgation unit (22) and a first component convolutional encoder section (24). A convolutional turbo encoder (20) comprises an expurgation unit (22); a first component convolutional encoder section (24); a second component convolutional encoder section (26); and an interleaver (28). For both the convolutional encoder (50) and the expurgating convolutional turbo encoder (20) the expurgation unit (22) inserts predetermined values at selected bit positions of an input bit sequence and thereby provide an expurgated input bit sequence. A lower rate convolutional code is obtained from a higher rate code via expurgation.

Abstract: A multimedia information receiving apparatus receives multimedia information which is transmitted by a broadcast system and receives multimedia information which is simultaneously transmitted by another transmission system such as IP communications, and generates one received information by selecting elements having a few errors from elements of demodulated broadcast system information and elements of demodulated other transmission system information and then arranging the selected elements.

Abstract: Embodiments of the present invention provide a rate matching method and apparatus. The method includes: receiving bit data of a first, a second, and a third input subblock, inserting dummy data into bit data in each subblock to respectively form even-numbered rows and odd-numbered rows of a matrix to be buffered for each subblock; inputting bit data of the even-numbered rows in the even-numbered row buffer and bit data of the odd-numbered rows in the odd-numbered row buffer of each subblock to a second buffer, and forming a matrix by using the bit data of the even-numbered rows and the bit data of the odd-numbered rows; controlling the second buffer to send data at the specified address; selecting data sent by the second buffer; and deleting the dummy data from the selected data to obtain valid output data.

Abstract: Described herein are embodiments of methods and systems for detecting communications of a first meter board by a second meter board and correlating the time and duration of the communications with metrology data gathered during that time. In accordance with one aspect, a method is provided for diagnosing metrology errors caused by communication activities of a meter board. In one embodiment, the method includes: receiving a signal, wherein the signal indicates a presence of communication activities between a first processor of a meter and another device over a network; recording a time of receipt and duration of the communication activities between the first processor of the meter and another device over the network; and correlating the time and duration of the communication activities between the first processor of the meter and another device over the network with metrology data of the meter measured at the same time and duration.

Abstract: Method and System for Utilization of an Outer Decoder in a Broadcast Services Communication System is described. Information to be transmitted is provided to a systematic portion of a plurality of transmit buffers and encoded by an outer decoder communicatively coupled to the transmit buffer. The resulting redundant bits are provided to a parity portion of each transmit buffer. The content of the transmit buffers, is multiplexed and encoded by an inner decoder to improve protection by adding redundancy. The receiving station recovers the transmitted information by an inverse process. Because a decoding complexity depends on the size of a systematic portion of the transmit buffer, reasoned compromise between a systematic portion size and number of transmit buffers yields decreased decoding complexity.

Abstract: The present invention is directed toward reconfigurable barrel shifters and rotators. A barrel shifter comprises an array of multiplexers, the array having a plurality of inputs and a plurality of outputs and wherein the array of multiplexers is configured to rotate a set of n input messages applied to the inputs by a selected number of positions at the outputs and wherein the number n of messages contained in the set is selectable from among a plurality of values, by changing only select control signal inputs to the array of multiplexers.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: A system and method for decoding data. Multi-dimensional encoded data may be received that potentially has errors. The multi-dimensional encoded data may encode each input bit in a set of input bits multiple times in multiple different dimensions to generate encoded bits. The encoded bits may be decoded in at least one of the multiple dimensions. If one or more errors are detected in a plurality of encoded bits in the at least one of the multiple dimensions, an intersection sub-set of the encoded data may be decoded that includes data encoding the same input bits encoded by the plurality of encoded bits in at least a second dimension of the multiple dimensions. The values of the input bits by decoding the intersection sub-set may be changed.

Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.

Abstract: A circuit and a method for parallel perforation in rate matching can adopt three selector arrays and three register groups. The first selector array is configured to remove null bits in input data and output the remaining data to the first register group; the second selector array is configured to combine the first register group and the third register group and then output the combined data to the second register group; during the combination, the valid data in the third register group are preferentially selected, and then the data in the first register group are selected; Further, the third selector array is configured to output remaining valid data in the first selector group to the third register group if the valid data in the first selector group are not used out while combining the first register group and the third register group by the second selector array.

Abstract: An image processing apparatus and a method for controlling an image processing apparatus are disclosed. The method includes: primarily processing a first thread from among a plurality of threads for a preset process; generating and storing a first error correction code for data recorded in a stack area of a random access memory (RAM) corresponding to the first thread when a primary process terminates; processing a second thread which is different from the first thread from among the plurality of threads; determining whether the data of the stack area is valid on the basis of the stored first error correction code at a point of time when the process for the second thread terminates and a secondary process for the first thread begins; and secondarily processing the first thread by restoring the data having an error in the stack area in response to a determination that the data of the stack area is invalid.

Abstract: The inventive concept enables backward-compatible extension of existing interleaver-based transmission systems to the effect that in addition to an existing logical transport channel, which is interleaved using a standardized interleaver profile, further logical transport channels may be transmitted via the same physical transmission channel. In this context, the first transport channel obviously is reduced in terms of data rate, so that the additional transport channels may actually obtain a transmission capacity that is needed accordingly. Interleaver profiles of the further logical transport channels are derived, to this end, from the interleaver profile of the first transport channel.

Abstract: A receiver for receiving a layer-modulated signal includes: a base layer decoding unit configured to calculate a bit metric including code bit information of a base layer based on the reception signal and decode an information bit of the base layer; and at least one enhancement layer decoding unit configured to decode an information bit of an upper layer of a lower layer based on the decoding results of the lower layer, wherein the base layer decoding unit and the at least one enhancement layer decoding unit are sequentially connected according to the order of the corresponding layers.

Abstract: Described embodiments provide a wideband code division multiple access (W-CDMA) system that employs a rate matching rule having a modified puncturing algorithm. The modified puncturing algorithm defines the input variables of the rate matching rule in a manner that provides for identification of relations between non-punctured data bit position addresses in the output data stream through an iterative process, from which absolute bit position addresses of non-punctured output bits might then be generated. A counter, in accordance with instruction generated by a processor or state machine, for example, might implement the modified puncturing algorithm on an input string of bits to provide an output string of bits based on the absolute bit position addresses of non-punctured output bits, thereby providing for rate matching in the communications channel.

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Abstract: Positions holding different bit values between a first code word, which is obtained by coding an information bit sequence based on a coding method utilizing quasi-cyclic codes, and a second code word, which has the close Hamming distance from the first code word and satisfies a parity check of the coding method, are identified. Thereafter, a code word is generated by inserting bit values known to the transmitter and receiver into the identified positions of the information bit sequence and coding the information bit sequence. Upon reception of a signal based on the generated code word, the receiver judges whether known bit values held by corresponding positions in a code word obtained by decoding the received signal are the same as preset bit values. If the judgment result is negative, the code word based on the received signal is judges as erroneous even when it satisfies the parity check.

Abstract: Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. Variable modulation encoding of LDPC coded symbols is presented. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis.

Abstract: A multiple access scheme is described. One or more encoders are configured to encode a plurality of bit streams using Low Density Parity Check (LDPC) coding. The bit streams correspond to a respective plurality of terminals. The plurality of bit streams are converted to provide a multiple access scheme for the terminals.

Abstract: An apparatus and method for processing fast feedback payload data to generate symbols for transmission through a fast feedback channel in a wireless network are presented. The technique first encodes payload data using a tail biting convolutional code. The encoded bits are then de-multiplexed to five different data subblocks in a sequential fashion. Subblock interleaving is then used to interleave the data of the subblocks according to a predetermine scheme. A bit selector then selects interleaved subblock bit for output. The selected bits may then be modulated by a modulator using quadrature phase shift keying (QPSK). The resulting symbols may then be mapped to a predetermined fast feedback subcarriers within a feedback channel.

Abstract: In a communication system, a transmitter receives an input bit, and in response thereto, generates at least an n-bit codeword, each bit of which is generated by a respective one of n generators of which m are exactly the same, m being greater than n/2. A receiver comprises: m detectors, each adapted to receive the bit generated by a respective one of the m generators, and provide a respective one of m partial detection signals if a strength of the received bit exceeds a predetermined minimum threshold; and a majority logic element adapted to receive each of the m partial detection signals, and provide an output bit indicative of the input bit only if more than m/2 of the received m partial detection signals exceeds the minimum threshold.

Abstract: A first sequence of states associated with a surviving path and a second sequence of states associated with a non-surviving path are determined. A possible error event is determined based at least in part on the first sequence of states and the second sequence of states. The first sequence of states is replaced with the second sequence of states by applying the possible error event to the first sequence of states.

Abstract: A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder (10) for partial parallel decoding of low-density parity-check convolutional codes, the decoder having: a plurality of pipeline processors (11) to receive channel messages and edge-messages; each processor (11) having: a plurality of block processing units (BPUs) (13), each BPU (13) having a plurality of check node processors (CNPs) (14) to process check nodes that enter into the processor (11) and a plurality of variable node processors (VNPs) (15) to process variable nodes that are about to leave the processor (11); and a plurality of Random Access Memory (RAM) blocks (30) for dynamic message storage of the channel messages and the edge-messages; wherein in each processor (11), the VNPs (15) are directly connected to corresponding RAM blocks (30), and the CNPs (14) are directly connected to corresponding RAM blocks (30) such that the connections from the VNPs (15) and CNPs (14) to the corresponding RAM blocks (30) are pre-defined and fixed accor

Abstract: A method of interleaving blocks of indexed data of varying lengths is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

Abstract: Systems and methods are provided for decoding data. A decoder retrieves data related to a symbol and identifies a plurality of candidate values for the symbol. The decoder determines a distance between each of the plurality of candidate values and a reference value associated with the symbol to obtain a plurality of distances, and the decoder determines whether to update a value of the symbol based at least in part on the plurality of distances.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data set quality determination.

Abstract: The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads.

Abstract: A centralized DVR includes a dispersed storage error encoding module, storage nodes, and a distribution module. The dispersed storage error encoding module encodes a broadcast of data in accordance with an error coding dispersal storage function to produce a plurality of sets of encoded data slices, which is stored in the storage nodes. For a first playback request, the distribution module determines a first unique combination and retrieves, as a first unique copy of the broadcast data from the storage nodes, encoded data slices of the plurality of sets of encoded data slices in accordance with the first unique combination. For a second playback request, the distribution module determines a second unique combination and retrieves, as a second unique copy of the broadcast data from the storage nodes, encoded data slices of the plurality of sets of encoded data slices in accordance with the second unique combination.

Abstract: An apparatus and method are disclosed to receive information and to generate, store, and read, a plurality of error correction coded data sets using that information. Applicants' storage controller receives information and generates (N) sets of error correction coded data, wherein (N) is greater than or equal to 2. The method writes, for each value of (i), the (i)th set of error correction coded data to the (i)th data storage medium, wherein (i) is greater than or equal to 1 and less than or equal to (N). If Applicants' storage controller receives a request to read the information, then Applicants' method reads each of the (N) error correction coded data sets, generates the information using the (N) error correction coded data sets, and returns the information to the requestor.

Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: Various embodiments of the present invention provide systems and methods for data processing using variable scaling.

Abstract: To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N?K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes.

Abstract: A method for receiving and storing a packet of symbols. The method decodes the packet of symbols using a first decoding algorithm, and if the first decoding algorithm fails to correctly decode the packet of symbols, then the method decodes the packet of symbols using a second decoding algorithm. If the second decoding algorithm fails to decode the packet of symbols, then a third decoding algorithm is used. The third decoding algorithm can be sub-packet decoding, where a first sub-packet is part of the packet of symbols. If the first sub-packet is decoded successfully, then the method generates a channel estimate using the properly decoded information, and then uses that channel estimate to decode a subsequent sub-packet using the channel estimate, where the second sub-packet is a set of symbols that are a portion of the packet of symbols.

Abstract: In one embodiment, a Television (TV) receiver to perform a method of synchronizing a demodulator at a Viterbi decode input in the TV receiver using one or more bit de-interleaved even and odd Orthogonal Frequency Division Multiplexing (OFDM) symbols is provided. The method includes (i) performing a Viterbi decoding on the bit de-interleaved even and odd OFDM symbols when a frame boundary does not exist for the bit de-interleaved even and odd OFDM symbols, (ii) performing a convolutional encoding on an decoded data output of the Viterbi decoding, (iii) determining whether an output of the convolutional encoding of the bit de-interleaved OFDM symbols matches an input at a Viterbi decode, and (iv) determining whether the output of the convolutional encoding of the bit de-interleaved even and odd OFDM symbols matches with a SYNC pattern or a SYNC? pattern to obtain a RS packet align boundary.

Abstract: A method and apparatus are provided for determining bits in a convolutionally decoded output bit stream to be marked for erasure. K-bits and p-bits of the convolutionally encoded output bit stream may be compared with a corresponding k-bits and p-bits of a delayed version of the input bit stream. For each bit of the k-bits (p-bits) in the convolutionally encoded output bit stream and in the corresponding k-bits (p-bits) of the delayed version of the input bit stream, a number of or pattern of conflicting bits and whether the number of conflicting bits exceeds a threshold number or pattern of conflicting bits may be determined. The output bit stream may be sent to a block decoding component for decoding with the k-bit streams marked for erasure.

Abstract: A system receives a first word on which to perform error correction; identifies combinations in which encoded bits, within the first word, can be inverted; generates candidate words based on the first word and the combinations; decodes the candidate words; determines distances between the decoded words and the first word; selects, as a second word, one of the decoded words associated with a shortest distance; compares the second word to the first word to identify errors within the first word; generates a value to cause a reliability level of the first word to increase when a quantity of the errors is less than a threshold; generates another value to cause a reliability level of the first word to decrease when the quantity of the errors is not less than the threshold; and outputs a third word based on the first word, and the value or the other value.

Abstract: A method for communication includes receiving at a receiver a signal from a transmitter embodying data encoded with an error correction code. The signal is processed in order to extract a sequence of samples in a complex signal space. Scalar values are extracted from the samples and the scalar values are processed so as to define one or more clusters of scalar data points. Gain and noise of the signal are estimated responsively to the defined clusters. Bit value metrics for the signal are computed based on the samples and the estimated gain and noise of the signal. The error correction code is decoded using the bit value metrics.

Abstract: Apparatuses and methods for resolving trapping sets are provided. One example method can include attempting to decode a codeword using initial values for confidence levels associated with digits of the codeword. For a trapping set, the confidence levels associated with the digits corresponding to a failed parity check are adjusted. The method further includes attempting to decode a codeword using the adjusted value for the confidence levels of the digits corresponding to the failed parity check.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for skewed orthogonal coding techniques. In one aspect, a method includes receiving a block of data comprising a plurality of data chunks. One or more rows of word code chunks are generated using a first linear error-correcting code in systematic form and the data chunks. For each of m rows of the data chunks, one or more split row code chunks are generated using the data chunks of the row, wherein the split row code chunks are generated so that a linear combination of m split row code chunks from different rows forms a first word code chunk of a first codeword including the data chunks and the word code chunks. The rows of data chunks and the split row code chunks and the word code chunks are stored.

Abstract: In an aspect, in general, a forward error correction algorithm (FEC) utilizes an FEC block structure in a manner that extends the effective error correction such that it can approach an “infinite” length to obtain benefits typical of very large FEC block size without the commensurate computation cost.

Abstract: A multistage difference cyclic permutation unit (106) for performing multistage cyclic permutation, an address administration unit (104) for administering addresses of the cumulative LLR memory (101), a received value arrangement unit (103) for generating records during writing of received values to the cumulative LLR memory (101), and a control unit (110) for generating parameters to control each unit from information of a parity check matrix and the current cyclic permutation size are prepared. The address administration unit (104) controls reading/writing addresses of the cumulative LLR memory (101) based on a reading start address from the cumulative LLR memory (101) corresponding to the column block. After the start of reading of a column block, the control unit (110) generates a reading start address in the next decoding of the column block and stores it into the address administration unit (104).

Abstract: Embodiments of the invention provide a decoder arrangement (400), wherein a decoder (420) which is adapted to decode a bitstream which has been encoded with a non-recursive convolutional encoder is used to at least partially perform the decoding of a recursive convolutionally encoded bitstream, with pre-or post-processing (410) of the bitstream being performed to complete the decoding. More particularly, in one embodiment of the invention a recursively encoded bitstream is input into a conventional decoder (420) which is adapted to decode a non-recursively encoded bitstream. The resulting intermediate output does not represent the correct decoded bitstream, but can then be subject to a post-processing step in the form of a non-recursive encoding operation (410), which effectively completes the decoding operation and provides as its output the correct decoded bitstream. Both hard decision or soft decision inputs can be used.

Abstract: An error correction encoding method is provided for encoding in parallel source digital data, having the form of a frame, wherein said data can be classified into N classes, where N is an integer at least equal to 2. The encoding method includes: a first recursive systematic convolutional encoding step of data to be encoded, formed by the data of the class 1; and an implementation of the following steps, for each n ranging from 1 to M, where M is a positive integer equal to or lower than N?1: nth mixing of a set formed by the data of the class n+1 and the systematic data of the preceding encoding; and (n+1)th recursive systematic convolutional encoding of data to be encoded, formed by the result of the nth mixing. Also disclosed is a related decoding method, as well as an associated encoding and decoding devices.

Abstract: LDPC coding systems for 60 GHz millimeter wave based physical layer extension. LDPC (Low Density Parity Check) encoding in cooperation with sub-carrier interleaving, in the context of orthogonal frequency division multiplexing (OFDM), and appropriate symbol mapping is performed in accordance with transmit processing as may be performed within a communication device. In a receiving communication device, receive processing may be performed on a received signal based on the type of LDPC, sub-carrier interleaving, and symbol mapping thereof. The LDPC code employed in accordance with such LDPC encoding may have a partial-tree like structure. In addition, appropriate manipulation of the bits assigned to respective sub-carriers may be performed to ensure that the bits emplaced in the MSB (Most Significant Bit) location of various symbols has some desired diversity (e.g., from different codewords, from appropriately different locations within a given codeword, etc.).