Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: The present inventions are related to LDPC decision-driven equalizer adaptation. For example, a data processing apparatus is disclosed that includes an equalizer operable to yield equalized data, a low density parity check decoder operable to decode the equalized data to yield decoded data, and an equalizer adaptation circuit operable to adapt settings in the equalizer based in part on the decoded data.

Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.

Abstract: The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.

Abstract: A method for exiting receiver processing in a FLO-EV receiver comprises receiving a communication signal comprising at least one received symbol, deriving a channel performance metric based on the received symbol, determining whether the metric exceeds a threshold, and when the metric exceeds the threshold, providing a logic signal to signal receiver processing cessation.

Abstract: A readdressing decoder for QC-LDPC decoding including a memory, a controller and parallel processors is provided. The memory stores a QC-LDPC matrix including sub-matrices respectively addressed with a corresponding address. The controller readdresses each of the sub-matrices into divided matrices and defines each of the divided matrices into a first address group and a second address group. The controller further respectively transmits the divided matrices of the first address group and the second address group to the parallel processors to perform correction algorithm.

Abstract: In exemplary embodiments of the present invention, methods and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, which is also suitable for both ASIC and FPGA implementations, are provided. In exemplary embodiments of the present invention, the overhead associated with correction data sent along the transmission channel can be minimized. In exemplary embodiments of the present invention, an LDPC decoder is suitable for both ASIC and FPGA implementations. Method and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates are presented. In exemplary embodiments of the present invention, such an LDPC decoder can be implemented in both ASIC and FPGA implementations. In exemplary embodiments of the present invention such an LDPC decoder can be optimized for either eIRA based H matrices or for general H matrices, as may be desirable.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for skewed orthogonal coding techniques. In one aspect, a method includes receiving a block of data comprising a plurality of data chunks. One or more rows of word code chunks are generated using a first error-correcting code in systematic form and the plurality of data chunks. For each row of a plurality of rows of the data chunks, one or more row code chunks for the row are generated using a second error-correcting code in systematic form and the data chunks of the row. The rows of data chunks and the row code chunks and the rows of word code chunks are stored.

Abstract: A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver ?(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver ?(i) is generated based at least in part on the first and second intermediate interleaver permutations.

Abstract: Systems and methods for encoding and decoding check-irregular non-systematic IRA codes of messages in any communication or electronic system where capacity achieving coding is desired. According to these systems and methods, IRA coding strategies, including ones that employ capacity-approaching non-systematic IRA codes that are irregular and that exhibit a low error floor, are employed. These non-systematic IRA codes are particularly advantageous in scenarios in which up to half of coded bits could be lost due to channel impairments and/or where complementary coded bits are desired to transmit over two or more communications sub-channels. An encoder includes information bit repeaters and encoders, one or more interleavers, check node combiners, a check node by-pass and an accumulator. A decoder includes a demapper, one or more check node processors, an accumulator decoder, a bit decoder, and one or more interleavers/deinterleavers.

Abstract: An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula.

Abstract: An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements connected in a series configuration. An input of a first one of the delay elements is adapted to receive a sum of first and second signals, the first signal generated as a sum of the input data sample and at least one of the delayed samples, and the second signal generated as an output of a single one of the delay elements. A third delay line in the encoder is operative to generate an output data sample as a function of the sum of the first and second signals and a delayed version of the sum of the first and second signals.

Abstract: A system and method for Viterbi decoding utilizes a general purpose processor with application specific extensions to perform Viterbi decoding operations specified in a Viterbi decoding algorithm stored in memory.

Abstract: A method for forming a bit sequence having a number of M bits from a bit sequence having a number of N bits, wherein M/2<N<M, involves extending said bit sequence by M-N bit positions, segmenting said extended bit sequence into at least two blocks with different numbers of bit positions such that the number of bit positions in the first block is less than the number of bit positions in the last block, and filling empty bit positions with bits having a pre-determined value.

Abstract: Techniques for supporting high decoding throughput are described. A transmitter may encode a code block of data bits with a Turbo encoder. A receiver may perform decoding for the code block with a Turbo decoder having multiple soft-input soft-output (SISO) decoders. A contention-free Turbo interleaver may be used if the code block size is larger than a threshold size. A regular Turbo interleaver may be used if the code block size is equal to or smaller than the threshold size. The contention-free Turbo interleaver reorders the data bits in the code block such that information from the multiple SISO decoders, after interleaving or deinterleaving, can be written in parallel to multiple storage units in each write cycle without encountering memory access contention. The regular Turbo interleaver can reorder the data bits in the code block in any manner without regard to contention-free memory access.

Abstract: Decoder and communications devices including such decoders can obtain a convolutional coded bit stream including a plurality of coded data bits. According to some implementations, if a signal quality associated with the convolutional coded bit stream is above a predetermined threshold, a decoded value for each information bit may be calculated at least from a modulo 2 sum of a coded data bit added to at least one other coded data bit, at least one previously calculated information bit, or a combination of at least one other coded data bit and at least one previously calculated information bit. Also, according to some implementations, if the signal quality associated with the convolutional coded bit stream is not above the predetermined threshold, the convolutional coded bit stream may be decoded with a conventional convolutional decoding scheme. Other aspects, embodiments, and features are also claimed and described.

Abstract: An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula.

Abstract: The present invention relates to a method, a terminal device and a network device for providing redundancy parameters for an automatic repeat request processing at a terminal device. The method includes selecting a redundancy strategy for an automatic repeat request processing at the terminal, and transmitting information indicating the selected redundancy strategy to the terminal device for generating redundancy parameters for the automatic repeat request processing at said terminal device. The information includes at least one of an index and a pointer to the selected at least one sequence.

Abstract: A method for soft remodulation in a receiver of transmissions over a wireless telecommunication system, the method including obtaining from a FEC decoder a-posteriori LLR values, converting the a-posteriori LLR values into bit probabilities and computing improved soft symbols estimates as expected values using the bit probabilities in a recursive algorithm. Preferably, the step of converting is implemented using a pre-computed Look Up Table (LUT). Preferably, the step of computing is implemented in a Multiplier-Accumulator having a SIMD structure.

Abstract: The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (?) values and check edge message (?) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.

Abstract: A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

Abstract: A memory efficient, accelerated implementation architecture for BCJR based forward error correction algorithms. In this architecture, a memory efficiency storage scheme is adopted for the metrics and channel information to achieve high processing speed with a low memory requirement. Thus, BCJR based algorithms can be accelerated, and the implementation complexity can be 5 reduced. This scheme can be used in the BCJR based turbo decoder and LDPC decoder implementations.

Abstract: A decoding apparatus for performing decoding processing of encoded data by using non-binary LDPC codes, includes: a logarithmic Fourier transform processing section, a variable node processing section, an edge coefficient processing section, and a check node processing section, wherein the logarithmic Fourier transform processing section performs Fourier transform processing and logarithmization processing on a probability vector of a symbol of an encoded frame data to output an initial value of logarithmic Fourier domain probability vector, and the variable node processing section, the edge coefficient processing section, and the check node processing section perform iteration processing by using a logarithmic Fourier domain probability vector.

Abstract: A set of one or more receiver parameters is adjusted. It is determined whether to adjust the set of receiver parameters. In the event it is determined to adjust the set of receiver parameters, a new set of values is generated for the set of receiver parameters using a cost function (where the cost function does not assume a noise signal in a receive signal to have a particular statistical distribution) and the set of receiver parameters is changed to have the new set of values.

Abstract: A receiver of a wireless communication system and method thereof include antennas configured to receive data, wherein the data comprises a preamble, a header, and a payload. The receiver also includes a synchronizer configured to perform time synchronization of the data received through corresponding paths of each antenna using corresponding preambles of the data. The receiver includes a header detector configured to detect a header from the data of each of the paths. A surviving path selector in the receiver is configured to select a signal of a surviving path from among the paths based on the header or the preamble. The receiver also includes combiner configured to combine the signal existing in the surviving path to demodulate the payload.

Abstract: The present invention discloses a method and apparatus for performing forward error correction with a multi-dimensional Bose Ray-Chaudhuri Hocquenghem (BCH) product code, and a method for detecting false decoding errors in frame-based data transmission systems.

Abstract: An embodiment of a method for transmitting data through at least a channel in a wireless communication system, the method comprising at least the steps of: encoding the data by performing a forward-error-correction encoding, forming a sequence of symbols from the encoded data, forming an M-by-T coding matrix from said sequence of symbols, each column of the coding matrix comprising N different symbols of the sequence of symbols and M?N zeros, N being an integer equal at least to one, T representing the number of consecutive transmission intervals, M representing the total number of transmit antennas, and using the coding matrix for transmitting the sequence of symbols during the T consecutive transmission intervals, by transmitting one different column of the coding matrix at each transmission interval through the M transmit antennas, only N transmit antennas are enabled during a given transmission interval.

Abstract: An error correction apparatus comprises an input for receiving data. The received data includes error-check data. The apparatus also includes a processing resource arranged to calculate parity check data. A data store is coupled to the processing resource for storing look-up data for identifying, when in use, a location of an error in the received data. The look-up data is a compressed form of indexed error location data.

Abstract: A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction and expanding the FEC-coded enhanced data. The packet generator generates enhanced data packets including the pre-processed enhanced data and main data packets and multiplexes the enhanced and main data packets. Each enhanced data packet includes an adaptation field in which the pre-processed enhanced data are inserted. The RS encoder performs RS encoding on the multiplexed data packets for second forward error correction, and the trellis encoder performs trellis encoding on the RS-coded data packets.

Abstract: Provided is a rate matching apparatus. The rate matching apparatus includes interleavers, dummy bit removers, a bit collector, a memory and a selector. The interleavers interleave code blocks, respectively. The dummy bit removers remove dummy bits of the interleaved code blocks, respectively. The bit collector collects code blocks with the dummy bits removed by bit units, and divides a collected data bit stream into systematic data and parity data. The memory stores the systematic data and the parity data in parallel. The selector outputs in parallel a plurality of data bits which are selected from the systematic data and parity data of the memory.

Abstract: The present disclosure is directed to a system and method for error correction utilizing turbo code and signal transmission with error correction utilizing turbo code. A sequence of data is divided into a plurality of elements. Each element is encoded separately in parallel utilizing turbo encoding and decoded separately in parallel utilizing turbo decoding. The encoding and decoding of each element may be performed by an encoder and a decoder dedicated to that respective element. The control mechanism that controls each encoder and decoder may be identical, similar to a SIMD (single instruction, multiple data) architecture, allowing each element to be encoded and decoded separately in parallel utilizing turbo encoding and decoding. The encoding and decoding of each element separately in parallel utilizing turbo encoding and decoding may utilize the same interleaver permutation.

Abstract: A pre-decoded tail-biting convolutional code (TBCC) decoder and a decoding method thereof are provided. The decoder includes a pre-decoder, a storage module, and a control module. The pre-decoder receives a current state, a neighboring state, and a current path status corresponding to sequential data encoded in TBCC, generates predicted decoded bits, and determines whether states corresponding to minimum path metrics of neighboring stages are in continuity according to the current state, the neighboring state, and a current path status. The storage module is connected to the pre-decoder and stores the predicted decoded bits. The control module is connected to the storage module and the pre-decoder. In addition, the control module selects to output the decoded bits from the storage module when the continuity between the states corresponding to the minimum path metrics of the neighboring stages reaches a truncation length.

Abstract: A method for reporting uplink control information (UCI) on a user equipment (UE) is described. It is determined a number of bits in a sequence of bits for transmission is greater than 11 and less than or equal to 21. The sequence of bits for transmission is segmented into a first segment and a second segment using a floor function. The first segment is encoded using a first Reed-Muller encoder. The second segment is encoded using a second Reed-Muller encoder.

Abstract: A receiver apparatus comprises a LDPC decoder that can apply an accelerated belief propagation method for iteratively decoding each code block. When the number of iterations reaches a certain threshold value, the accelerated belief propagation method can adjust the initial condition used in each iteration. The initial condition is adjusted so as to enhance the likelihood of convergence in the iterative method. As a result, performance of the decoder and receiver apparatus can be improved.

Abstract: There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder connects a first encoder to a second encoder to perform encoding and thereby carry out LDPC-CC encoding, the first encoder performing encoding based on an partial parity check matrix for information bits obtained by extracting a sequence corresponding to the information bits in a parity check matrix and the second encoder performing encoding based on a partial parity check matrix for parity bits obtained by extracting a sequence corresponding to the parity bits in the parity check matrix. A termination sequence generator generates a termination sequence including the same number of bits as the memory length of the first encoder and provides the generated termination sequence as an input sequence.

Abstract: One embodiment of the present invention relates to a method of detecting potential performance degradation caused by neighboring identical scrambling codes. The method includes detecting an existence of identical scrambling codes in received signals from different cell at the user equipment, and selectively eliminating one or more signals from consideration in processing of received signals based upon the detection. The invention also includes a receiver configured to detect potential performance degradation caused by neighboring identical scrambling codes. The receiver includes a detection component configured to detect an existence of identical scrambling codes in received signals from different base stations at the user equipment, and an elimination component configured to selectively eliminate one or more signals from consideration in processing of received signals based upon the detection by the detection component.

Abstract: A digital television (DTV) transmitter and a method of processing data in the DTV transmitter/receiver are disclosed. In the DTV transmitter, a pre-processor pre-processes the enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded data. A packet formatter generates one or more groups of enhanced data packets, each enhanced data packet including the pre-processed enhanced data and known data, wherein the data formatter adds burst time information into each group of enhanced data packets. And, a packet multiplexer generates at least one burst of enhanced data by multiplexing the one or more groups of enhanced data packets with at least one main data packet including the main data, each burst of enhanced data including at least one group of enhanced data packets.

Abstract: A network coding method includes receiving a plurality of message packets each having a packet length. Encoding the plurality of message packets by applying a convolutional code across symbols in corresponding positions of the plurality of message packets obtaining a number of encoded packets. The number of encoded packets obtained being more than the number of message packets.

Abstract: An encoding processing apparatus in which reception precision characteristics are improved by specially adapting puncture processing in respect of the code words for each encoding system. A puncture section switches between a puncture pattern for a first code word partial sequence obtained on the basis of the head and tail in a fixed information block, and a puncture pattern for a second code word partial sequence obtained on the basis of the middle portion, excluding the head and tail. Also, the puncture section receives the number of retransmissions of information from a retransmission control section and switches the puncture pattern for the second code word partial sequence in accordance with the number of retransmissions. In addition, the puncture section prioritizing systematic bits over parity bits when puncturing the first code word partial sequence.

Abstract: Disclosed are an apparatus and a encoding method using a turbo code and a unit and a method of permutation. The apparatus for encoding using a turbo code according to an exemplary embodiment of the present invention includes: a first encoder that encodes 3 bits inputted from first to third blocks each of which is formed of N bits respectively, with recursive systematic convolutional codes to output a first parity bit; a permutation unit that permutates the 3 bits; a second encoder that encodes the permutated 3 bits with the recursive systematic convolutional codes to output a second parity bit; and a puncturing unit that optionally removes the first parity bit and the second parity bit in consideration of a coding rate of a predetermined turbo code to control the coding rate.

Abstract: Data communication, with improved error detection, of a signal having a plurality of data blocks, by: error checking a received data block in a first sequence using a first polynomial, beginning with a first predetermined initial error checking state, producing a first checksum; error checking the received data block in a second sequence using a second polynomial, using the first checksum as a second predetermined initial error checking state, producing a second checksum; comparing the second checksum to the first predetermined initial error checking state to detect errors in the data communication; and repeating the above steps for sequential data blocks of the data communication, wherein the first polynomial is an inverse of the second polynomial.

Abstract: Various embodiments of the present invention provide systems and methods for decoding data. As an example, a data processing circuit is disclosed that includes a multi-tier decoding circuit having a first tier decoding circuit operable to decode portions of an encoded data set exhibiting low row weight, and a second tier decoding circuit operable to decode portions of an encoded data set exhibiting high row weight.

Abstract: An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information.

Abstract: A loss correction encoding device having an improved capability of loss correction using LDPC-CC is disclosed. In the loss correction encoding device (120), a rearranging unit (122) rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q?1)/q of a cheek polynomial of the loss correction code used in a loss correction encoding unit (123). Specifically, the rearranging unit (122) rearranges the information data in such a way that continuous Kmax×(q?1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit (122) distributes the information data to information blocks from n information packets (n satisfies formula (1)). Kmax×(q?1)?n??(1).

Abstract: k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n?<n bits. The punctured codeword is exported to a corrupting medium such as a communication channel or a memory. A representation of the punctured codeword is imported from the corrupting medium and is decoded using a matrix H? that is smaller than H. For example, H has at most m rows and fewer than n columns but more than n? columns.

Abstract: k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n?<n bits. The punctured codeword is exported to a corrupting medium such as a communication channel or a memory. A representation of the punctured codeword is imported from the corrupting medium and is decoded using a matrix H? that is smaller than H. For example, H has fewer than m?=m?(n?n?) rows and fewer than n? columns.

Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract: A system for decoding data includes a symbol based error correction code device. The error correction code device includes a channel detector configured to generate probability mass function (PMF) information. The error correction code device further includes a decoder coupled to the channel detector. The decoder is configured to use the PMF information from the channel detector to perform an error correction code operation. The decoder also is configured to generate PMF information. The channel detector is configured to receive extrinsic PMF information in a turbo equalization scheme.

Abstract: An apparatus and method for rate dematching in a communication system are provided. The apparatus includes an input sequence generator, an error calculator, and a puncture/repetition determiner. The input sequence generator calculates if current input data among data, which are input in interleaved sequence, corresponds to any nth sequence among before-interleaved sequence. The error calculator calculates an error for the current input data using the calculated sequence. The puncture/repetition determiner determines type of the current input data using the error for the current input data.

Abstract: A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.