Abstract: Methods and systems of low density parity check coded (LDPCC) coding are disclosed herein in which a set of LDPC codes ensure reliable transmission for channels in which modulation symbols may undergo attenuation in a random fashion. Methods and systems of LDPC coding disclosed herein include choosing a code blocklength and concatenating codewords into which a data packet can be encoded. To optimize the coding scheme, first, codeword shortening is performed to ensure an integer number of codewords for a desired packet length. The codewords may then be punctured or repeated to ensure an integer number of channel symbols per codeword. Shortening and puncturing repetition methods are implemented to yield minimum overhead while keeping the effective coding rate low.

Abstract: Disclosed herein is a decoding apparatus for decoding channel input bits from a partial-response channel output in accordance with a trellis obtained by combining a coding constraint and state transitions of a partial response for a case in which the length of a memory required for describing the coding constraint is greater than the length of a channel memory of the partial response. The apparatus may include a first calculation unit configured to carry out a first calculation on first branch information, which may be defined as information on first branches included in three or more branches merging in a state determined in advance, and first path information defined as information on first paths for the first branches; and a second calculation unit configured to carry out a second calculation on a first calculation value obtained as a result of the first calculation.

Abstract: An error correction code includes a separate error code portion for each of two or more separate burst erasure durations (or burst error durations). For each burst erasure duration, the code can be employed to recover from the burst erasure with a different delay time. Each error code portion has a particular parameter for burst duration (B) and delay (T), meaning that the code can be used to recover from a burst erasure of duration B with delay T. Each error code portion is based on separating the source symbols into sub-symbols and diagonally interleaving the sub-symbols based on the (B,T) parameters for the error code portion. Accordingly, different burst erasures are recovered from with different delays.

Abstract: A tree decoding method for decoding a linear block code is provided. According to the tree decoding method, an estimated path metric of node v is f(y)=g(v)+h(v), where g(v) represents a sum of bit metrics of all bits on a path from the root node to the node v, and h(v) represents a lowest bound of estimated accumulated bit metrics from the node v to the goal node. The present invention creatively improves the approach for calculating h(v). According to the present invention, some parity bits are only related to a part of the information bits, according to which the edge metric h(v) of the parity bits can be preliminarily incorporated into the path metric of the part of the information bits. As such, some nodes having inferior path metric could be eliminated in advance, thus minimizing the searching range and simplifying the decoding complexity.

Abstract: A system includes a clock having a clock frequency. A first buffer configured to buffer a plurality of encoded data frames. An iterative decoder configured to iteratively decode, in accordance with the clock frequency. A first encoded data frame of the plurality of encoded data frames buffered in the first buffer. The iterative decoder generates a confidence result. The iterative decoder compares the confidence result to a predetermined value. The iterative decoder stops iteratively decoding the first encoded data frame based on the comparison of the confidence result to the predetermined value or based on a total number of decoding iterations. The clock frequency of the clock is based on a total number of encoded data frames buffered in the first buffer.

Abstract: An apparatus and method are disclosed to generate convolution encoded data. The method supplies a convolution encoder. The method receives original data and generates convolution encoded original data. The method receives revised data. The method generates an XOR data stream by Exclusive OR'ing the original data with the revised data, forms a convolution encoded XOR data stream using the convolution encoder, and Exclusive ORs the convolution encoded XOR data stream with the convolution encoded original data to generate convolution-encoded revised data.

Abstract: A method for synchronizing receivers that receive turbo encoded signals to a received signal. Turbo encoding may enable signals to be decoded at a much lower signal to noise ratio than previously practical. A traditional method of synchronizing a receiver to an incoming signal is to use a slicer to determine a received symbol and then to compare the determined symbol to the incoming waveform, in order to adjust the phase of the slicer with respect to the incoming signal. At signal low levels, at which turbo encoded signals may be decoded, this slicing method may be prone to errors that may disrupt the synchronization of the receiver to the incoming signal. By replacing the slicer by a Viterbi decoder with zero traceback (i.e., one which does not consider future values of the signal only past values) a prediction as to what the incoming signal is can be made.

Abstract: The present disclosure is directed to a system and method of correcting video data errors. In a particular embodiment, the method includes receiving a stream of data packets at a re-generator of an Internet Protocol (IP) video transport stream. The stream of data packets includes a plurality of IP media packets and a plurality of forward error correction (FEC) packets. The method also includes determining an error profile of an error within the plurality of IP media packets. The method includes identifying one of the plurality of FEC packets, where the identified FEC packet is associated with an error correction code corresponding to the error profile. The method also includes selecting an inverse FEC function from a plurality of inverse FEC functions. The selected inverse FEC function corresponds to the identified FEC packet.

Abstract: Serial concatenated trellis coded modulation (SCTCM) includes an outer coder, an interleaver, a recursive inner coder and a mapping element. The outer coder receives data to be coded and produces outer coded data. The interleaver permutes the outer coded data to produce interleaved data. The recursive inner coder codes the interleaved data to produce inner coded data. The mapping element maps the inner coded data to a symbol. The recursive inner coder has a structure which facilitates iterative decoding of the symbols at a decoder system. The recursive inner coder and the mapping element are selected to maximize the effective free Euclidean distance of a trellis coded modulator formed from the recursive inner coder and the mapping element. The decoder system includes a demodulation unit, an inner SISO (soft-input soft-output) decoder, a deinterleaver, an outer SISO decoder, and an interleaver.

Abstract: A Viterbi decoder which is based on a special instruction set implemented in the processor, enabling it to handle the Viterbi processing with a much lower CPU loading without significantly increasing the hardware complexity. By careful application of appropriate design constraints specific to the SV navigation and analysis of the Viterbi algorithm an optimised architecture can be realised for embedding Viterbi acceleration logic efficiently into a GNSS chipset.

Abstract: Data are encoded using convolutional coding prior to storage in a nonvolatile memory array, so that errors that occur when the data are read may be corrected even where there is a large number of such errors. Coding rates of less than one increase the amount of data to be stored but allow correction of large numbers of errors.

Abstract: A method of providing forward error correction for data services uses a parallel concatenated convolutional code which is a Turbo Code comprising a plurality of eight-state constituent encoders wherein a plurality of data block sizes are used in conjunction with said Turbo Code. A variation uses the method in a cellular radio system. Another variation uses the method in both forward and reverse likes of a cellular radio system.

Abstract: Method and decoding device for decoding a convolutionally coded input data signal y. The input data signal is multiplied with a scaling factor Lc(8) and then demultiplexed (6). The demultiplexed input data signal LcS is then turbo decoded (5) in order to obtain decoder output likelihood ratio data ?. The scaling factor Lc is updated (7) for a next iteration in dependence on a combination of a posteriori likelihood data based on turbo decoded output data ? and a priori likelihood data based on the demultiplexed signal LcS.

Abstract: A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub-codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed.

Abstract: A method of providing forward error correction for data services uses a parallel concatenated convolutional code which is a Turbo Code comprising a plurality of eight-state constituent encoders wherein a plurality of data block sizes are used in conjunction with said Turbo Code. A variation uses the method in a cellular radio system. Another variation uses the method in both forward and reverse likes of a cellular radio system.

Abstract: A digital broadcasting transmission apparatus and robust stream coding method thereof. The digital broadcasting transmission apparatus includes a robust processor that codes a robust stream of a dual transport stream where a normal stream and the robust stream are combined. The robust processor includes a demultiplexer (DE-MUX) that separates the normal stream and the robust stream from the dual transport stream; a robust encoder that appends a parity to the separated robust stream; a robust interleaver that interleaves the robust stream having the appended parity; and a MUX that combines the interleaved robust stream and the separated normal stream. Accordingly, a receiver of a simple structure can be provided.

Abstract: An apparatus for accessing and transferring optical data has a memory supporting the page-mode function, an accessing device used to access an error correction block from the optical storage medium and store it into the memory to make the portion of data in the same column of the error correction block stored in a particular locality greater than the portion of data in the same row of the error correction block stored in the particular locality, and an error correction decoder used to access the data of the error correction block to perform the error correction process. The apparatus uses the feature of the DRAM, such as page-mode function, and the data arrangement of the memory to improve the access efficiency of the memory. The apparatus can thus increase the access speed of the error correction decoder and improve the accessing efficiency.

Abstract: An apparatus and method for processing fast feedback payload data to generate symbols for transmission through a fast feedback channel in a wireless network are presented. The technique first encodes payload data using a tail biting convolutional code. The encoded bits are then de-multiplexed to five different data subblocks in a sequential fashion. Subblock interleaving is then used to interleave the data of the subblocks according to a predetermine scheme. A bit selector then selects interleaved subblock bit for output. The selected bits may then be modulated by a modulator using quadrature phase shift keying (QPSK). The resulting symbols may then be mapped to a predetermined fast feedback subcarriers within a feedback channel.

Abstract: A convolutional encoder (50) comprises an expurgation unit (22) and a first component convolutional encoder section (24). A convolutional turbo encoder (20) comprises an expurgation unit (22); a first component convolutional encoder section (24); a second component convolutional encoder section (26); and an interleaver (28). For both the convolutional encoder (50) and the expurgating convolutional turbo encoder (20) the expurgation unit (22) inserts predetermined values at selected bit positions of an input bit sequence and thereby provide an expurgated input bit sequence. A lower rate convolutional code is obtained from a higher rate code via expurgation.

Abstract: A decoder includes at least one programming input for a plurality of programmable reduced-state trellis parameters. A programmable device is connected to the at least one programming input and implements a reduced-state maximum likelihood decoder that is operable for processing a continuous phase modulated (CPM) signal and returning up to N bits that were transmitted based on a maximum likelihood and current winning super-state and corresponding survivor full-state. The programmable device calculates the path metrics for every super-state and determines a best path based on the reduced-state trellis parameters.

Abstract: A low-density parity-check (LDPC) decoder includes a plurality of bit node processing elements, and a plurality of check node processing elements. The LDPC decoder also includes a plurality of message passing memory blocks. A first routing matrix couples the plurality of bit node processing elements to the plurality of message passing memory blocks. A second routing matrix couples the plurality of check node processing elements to the plurality of message passing memory blocks. The first routing matrix and the second routing matrix enable each bit node to exchange LDPC decoding messages with an appropriate check node via a corresponding one of the message passing memory blocks.

Abstract: Techniques are described herein that can be used to decode signals received over multiple channels. The received signals may be processed using noise reducing logic. Signal-to-noise ratio information per channel for signals received over each of the multiple channels may be considered to determine reliability information concerning the slicer input for each channel. Low density parity check codes or other forward error correction (FEC) codes may be used to decode the processed signals from all the multiple channels based on the reliability information.

Abstract: An error correction device includes a decoding unit, an error buffer, an error classifying unit and an error correction unit. The decoding unit reads data from a main memory and performs error detection on the data to generate error values and error addresses. Then, the error buffer temporarily stores the error values and the error addresses. The error classifying unit classifies the error addresses stored in the error buffer into a plurality of subclasses, where error values and error addresses which correspond to the same row of the main memory are classified into the same subclass. Finally, the error correction unit performs an error correction on the data stored in the main memory according to the plurality of subclasses. The error correction device therefore can reduce the amount of the change-row operations of the main memory so that the memory efficiency is increased.

Abstract: A trellis encoding device includes a trellis encoder block that includes a plurality of memories, and outputs a bit value determined by a state of the memories; a Reed-Solomon re-encoder that receives the bit value output from the trellis encoder block, and generates a parity corresponding to the bit value; and an adder that receives the parity generated by the Reed-Solomon re-encoder and a transmission stream including a parity, and corrects the parity of the transmission stream by adding the parity generated by the Reed-Solomon re-encoder to the transmission stream, thereby generating a parity-corrected transmission stream.

Abstract: In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.

Abstract: Methods and systems for modifying DOCSIS-based transmission paths for communication in higher frequency and/or wireless environments, such as wireless terrestrial communication systems and satellite communication systems. An inner turbo-code is combined with a DOCSIS based Reed-Solomon (“RS”) forward error correction (“FEC”) coding scheme, to produce a concatenated turbo-RS code (other FEC codes can be utilized). In phase and quadrature phase (“I-Q”) processing is utilized to enable relatively low cost up-converter implementations. The I-Q processing is preferably performed at baseband, essentially pre-compensating for analog variations in the transmit path. Power amplifier on/off control capable of controlling on/off RF power control of remote transmitters is modulated on a transmit cable to reduce the need for a separate cable.

Abstract: A system and method for interleaving data in a wireless transmitter are disclosed, where bits from the input data stream are sent to downstream processing without being stored in memory. According to a first example embodiment, a first radio frame of data from an input code block is sent downstream, and the remaining radio frames from the code block are stored in the memory buffer. The first interleaving pattern can be applied, for example, as data is written to or read from the buffer. The stored radio frames are then read out as needed by the downstream processing. According to a second example embodiment, further savings in memory can be achieved by discarding bits that are not currently needed for processing then recalculating them at a later time. A first radio frame of data from an input code block is sent downstream without being stored in the memory buffer.

Abstract: A system for transmitting a digital broadcasting signal includes a Reed-Solomon encoder that encodes a dual transport stream including a normal stream and a turbo stream to obtain an encoded dual transport stream; an interleaver that interleaves the encoded dual transport stream to obtain an interleaved dual transport stream; and a turbo processor that detects the turbo stream from the interleaved dual transport stream to obtain a detected turbo stream, encodes the detected turbo stream to obtain an encoded turbo stream, stuffs the encoded turbo stream back into the interleaved dual transport stream to obtain a reconstructed dual transport stream, and compensates the reconstructed dual transport stream for a parity error due to the encoded turbo stream to obtain a parity-compensated dual transport stream.

Abstract: A device includes a supernode generator module, a supernode splitting module, and a control module. The supernode generator module generates S supernodes each comprising d symbol nodes, where S and d are integers greater than 1. The supernode splitting module splits each of the S supernodes into d derived symbols, wherein a total number of symbol edges of the d derived symbols is equal to a predetermined number of symbol edges of each of the S supernodes. The control module generates a quasi-cyclic irregular low density parity check (LDPC) code based on S*d derived symbols, wherein S equals the S supernodes and d equals the d derived symbols.

Abstract: A turbo stream processing device and method. A turbo stream processing device includes a turbo stream detector to receive a dual transmission stream in which a turbo stream and a normal stream are multiplexed, and to detect the turbo stream; an outer encoder to encode the turbo stream; an outer encoder to interleave the turbo stream which is encoded at the outer encoder; and a turbo stream stuffer to reconstruct the dual transmission stream by stuffing the interleaved turbo stream into the dual transmission stream. Accordingly, the reception performance can be enhanced by more robustly processing the turbo stream in the dual transmission stream.

Abstract: To provide an LDPC decoder, to which SPA is applied, and a method wherein decoding characteristics are improved by reducing the ratio of a message from a check node within messages sent to the same check node. In a decoding device that decodes a received LDPC code by repeating the passing of messages between a plurality of check nodes and a plurality of bit nodes corresponding to a check matrix in each iteration, the order of message computation at a cluster in an iteration out of at least two iterations that have a before-and-after relationship in time and the order of message computation at a cluster in another iteration are varied.

Abstract: A decoding process for decoding a received block of N systematic binary data samples or N systematic duobinary data samples using a maximum a posteriori probability (MAP) decoding algorithm. The decoding process calculates a set of four log-likelihood values using the corresponding forward state metric, reverse state metric, and branch metric values for each of N/2 pairs of systematic binary data or each of N/2 pairs of duobinary data in the received block. The decoding process also calculates, for each set of four log-likelihood values a delta value corresponding to the difference between the largest and the second largest of the four log-likelihood values in each set. The decoding process repeats for at least a second iteration. The decoding process is stopped based on a plurality of delta values calculated during two consecutive iterations.

Abstract: A convolution interleaver for processing a codeword derived from an input block of symbols using a redundancy-adding coding, and having more symbols than the input block, wherein the codeword has a sequence of interleaving units, wherein each interleaving unit has at least two symbols, includes an interleaver. The interleaver changes the sequence of interleaving units to obtain an interleaved codeword having a changed sequence of interleaving units. In particular, the order of the symbols within an interleaving unit is not changed by the interleaver. The order of the interleaving units in the codeword among each other or with respect to a previous or subsequent codeword is changed, however.

Abstract: Described embodiments provide for rate matching with an encoded sequence of data bits. The encoded sequence of data bits is divided into two or more sub-blocks, with each sub-block having at least one column of bits, each including a set of valid bits. A set of dummy bits is generated and appended to each column of each sub-block. A starting point index for the set of valid bits within each sub-block is generated and the number of bits supported by the physical layer is determined. Only the valid bits of each sub-block are interleaved, based on each starting point index, until either i) there are no valid bits remaining, or ii) the number of interleaved bits reaches the number of bits supported by the physical layer. All dummy bits and any valid bits exceeding the number of bits supported by the physical layer are omitted.

Abstract: An encoding apparatus for use in a radio transmitter has a unit for turbo-SPC encoding a plurality of information bits which bits constitute a transmit signal, and deriving at least one set of redundant bits from one set of the information bits; and a redundancy-adjusting unit for decreasing or increasing the redundant bits according to a channel-encoding rate designated by a control signal, and adjusting the ratio of the number of the information bits to the number of the redundant bits. At least some of the redundant bits decreased or increased by the redundancy-adjusting unit are derived from an identical set of the information bits.

Abstract: The second rate de-matching unit carries out a second rate de-matching step in parallel to each of two data defining the received data Rx for removing bits having been repeated in a second rate matching step having been carried out in a base station, or de-removing bits having been punctured in the second rate matching step having been carried out in a base station. The adders carry out a combining step in parallel in which data stored in the IR buffer is added to associated data among the two data. The first rate de-matching/turbo-decoding unit carries out a first rate de-matching step in which bits having been punctured in a first rate matching step having been carried out in a base station are repeated to data having been output from the input buffers, and simultaneously, repeatedly carries out a turbo-decoding step to the data.

Abstract: The present invention relates to an inter-sequence permutation (ISP) encoder. The ISP encoder comprises: a receiving means to receive an information bit sequence input; a first outputting means for outputting a first code bit output; a second outputting means for outputting a second code bit sequence output; a bit-adding means coupled to the receiving means, the bit-adding means processing the received information bit sequence input prior to any subsequent processing in the ISP encoder; a first convolutional code encoder coupled between the bit-adding means and the first outputting means; a second convolutional code encoder; and an inter-sequence permutation interleaver coupled between the bit-adding means and the second convolutional code encoder. The second convolutional code encoder is coupled between the inter-sequence permutational interleaver and the second outputting means.

Abstract: Methods and associated structures for improved erasure correction and detection in digital communication channels utilizing modified Reed-Solomon decoding of encoded digital data. Methods and associated apparatus in accordance with features and aspects hereof perform Galois Field element generation in descending order for Reed-Solomon erasure detection and correction. Real time computation of Galois Field elements in descending order as required for erasure detection and correction features and aspects hereof eliminates the need for costly, complex, large, high speed lookup tables as previously practiced in the art for storing Galois Field element values pre-computed in the same ascending order of reception of the encoded code words. Features and aspects hereof may thus be applied in digital read channel applications including, for example, digital telecommunications receive/read channels and digital data storage read channels.

Abstract: A method for reducing the computational complexity of a Viterbi decoder, which is suitable for all code rates of a convolutional code applied by the Viterbi decoder. The method dramatically reduces the branch metric computation to thus reduce the complexity of implementing the Viterbi decoder, without affecting the capability of error correction. Upon the best mode, the Viterbi decoder can reduce the required branch metric computation to ¼k of the original computation.

Abstract: Techniques and devices for encoding and decoding a signal channel in a downlink signal in wireless communication systems, including the frame control header (FCH) data in IEEE 802.16 systems with reduced transmission power consumption, improved error correction capability, and reduced decoding complexity.

Abstract: Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bit according to a code characterized by a parity check matrix (H matrix) to generate a sequence of encoded bits, wherein the H matrix is capable of being expressed as H=[Hp|Hd]=[S|J*P*T], S being a dual-diagonal matrix, J being a single parity check matrix, P being an interleaver permutation matrix, and T being a repeat block matrix, wherein the H matrix is a column permuted version of an original H matrix, wherein clashes associated with an interleaver corresponding to the P matrix are reduced by adopting the H matrix instead of the original H matrix, and outputting the sequence of encoded bits.

Abstract: A method and device for performing forward error (FEC) correction avoidance based upon predicted block code reliability in a communications device is provided. An avoidance unit comprising a metric computation unit and a decision unit generates a reliability metric based upon a received code block. The reliability metric is compared to a reliability threshold, and the forward error correction decoder in the communications device is disabled if the metric is below or equal to the threshold.

Abstract: Method and a receiver in a communication system for receiving a transport block. The transport block comprises code blocks, each of the code blocks includes an error detection code and an error correction code. Reliability metrics are determined using an input generated during processing of the code blocks after the transport block is received. Each of the reliability metrics corresponds to each of the code blocks. A code block reorderer reorders the code blocks in an order based on the reliability metrics and a selection criterion. A decoder decodes each of the code blocks using the error correction code in the order. A verifier verifies each of the decoded code blocks using the error detection code.

Abstract: An object of the invention is to provide a wireless communication apparatus which can correct error flexibly without wasting consumed resources while maintaining the improvement of reliability resulted from error correction.

Abstract: The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.

Abstract: An apparatus and method for transmitting a signal using a bit grouping method in a wireless communication system is disclosed. Interleaved subblocks are maintained, and output bit sequences are modulated in due order after bit grouping and bit selection. The bit grouping method is advantageous in that bit reliability is uniformly distributed.

Abstract: A method and apparatus for decoding data is provided herein to show how to turbo decode LDPC codes that contain a partial dual diagonal parity-check portion, and how to avoid memory access contentions in such a turbo decoder. During operation, a decoder will receive a signal vector corresponding to information bits and parity bits and separate the received signal vector into two groups, a first group comprising signals corresponding to the information bits and one or more parity bits, a second group comprising a remainder of the parity bits. The first group of received signals is passed to a first decoder and the second group of received signals is passed to a second decoder. The decoders are separated by an interleaver and a deinterleaver. Iterative decoding takes place by passing messages between the decoders, through the interleaver and the deinterleaver, and producing an estimate of the information bits from the output of the first decoder.

Abstract: Example embodiments include methods of interference cancellation at NodeB receivers of baseband antenna signals including physical channels. The methods include canceling interference from a received baseband antenna signal by removing a reconstructed baseband signal from the processed received baseband antenna signal. The processed reconstructed baseband signal includes users whose physical data channel signals were successfully decoded. Methods also include removing interference from a received baseband signal to form an interference cancelled baseband signal that will be processed by the receiver. The interference cancelled baseband signal is the received baseband antenna signal minus users' signal interference contributions whose demodulated physical data channel signals have a determined user symbol energy value that exceeds a threshold. Methods further include removing interference from a user's signal to be error corrected.

Abstract: Systems and methods are provided for selecting transmission parameters used in the transmission of a communication signal in a wireless communications device. In one embodiment, a computer-implemented method for determining a convolutional code constraint length and/or a modulation type is provided. The method includes obtaining a channel condition for a channel associated with transmission of the communication signal. Based at least in part on the channel condition, the method includes selecting a convolutional code constraint length and/or a modulation type for transmitting the communications signal. In some embodiments, the method also includes selecting a data rate for transmitting the communications signal.

Abstract: The present invention discloses a method for LDPC code erasure decoding, including: generating a first code word through setting a value as a value in Galois field having two elements GF(2) at each of erasure locations in a code word; generating a second code word through setting the value as an inverse value of the value in GF(2) at each of the erasure locations in the code word; conducting a MLD error correcting operation for the first code word and the second code word to get a first result of hard decoding and a second result of hard decoding respectively; determining a result of erasure decoding according to the first result of hard decoding and the second result of hard decoding. Thus the present invention allows LDPC code erasure decoding aimed at the BEC, and increases the error correcting capability for BED signal transmitted data.