Abstract: Methods and apparatus are provided for reduced complexity Soft-Output Viterbi detection. A Soft-Output Viterbi algorithm processes a signal by determining branch metrics using a branch metrics unit; determining survivor paths for sequence detection using a first add-compare select unit; and determining survivor paths for generating one or more bit reliability values using a second add-compare select unit, wherein the first and second add-compare select units process the branch metrics determined by the branch metrics unit. The first and second add-compare select units can optionally process branch metrics having a different number of bits.

Abstract: Sliding block traceback decoding of block codes. Block by block basis decoding is performed in which a single block, and its corresponding overlap portion, are processed during a given time. The traceback saves a record of decision (e.g., among possible trellis branches between various trellis stages) and constructs only the surviving paths through each individual block. Since only one block (by also employing its corresponding overlap portion) is decoded per time, the traceback through the coded block signal is short. One block of the coded block signal is decoded at a time, and certain resulting information (e.g., bit estimates and/or states) of a first decoded block can be leveraged when decoding a second/adjacent block.

Abstract: Detecting, avoiding and/or correcting problematic puncturing patterns in parity bit streams used when implementing punctured Turbo codes is achieved without having to avoid desirable code rates. This enables identification/avoidance of regions of relatively poor Turbo code performance. Forward error correction comprising Turbo coding and puncturing achieves a smooth functional relationship between any measure of performance and the effective coding rate resulting from combining the lower rate code generated by the Turbo encoder with puncturing of the parity bits. In one embodiment, methods to correct/avoid degradations due to Turbo coding are implemented by puncturing interactions when two or more stages of rate matching are employed.

Abstract: A system and method for channel equalization using a Viterbi algorithm. Information from an output of a matched filter and channel parameters from a channel estimation circuit are correlated and passed on to a reconfigurable data path. The reconfigurable data path includes a reconfigurable branch metric calculation block. The reconfigurable data path also includes a reconfigurable add-compare-select and path metric calculation block. The reconfigurable data path is controlled using a programmable finite state machine. The programmable finite state machine executes a plurality of context-related instructions associated with the Viterbi algorithm. The system and method for channel equalization supports multiple standards using Viterbi algorithms.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: A method and system for decoding signals includes a transmitter configured for transmitting signals encoded with a mapping, with different and separable configurations in a real part and an imaginary part of the signal. The signals may be encoded according to a Gray or QAM mapping, and may be transmitted on a selective MIMO channel and/or multiplexed with an OFDM technique. The corresponding receiver is configured for decoding the real part and the imaginary part of the signals separately, and may include a filter for subjecting the encoded signals to a Wiener filtering and a MMSE detector for minimizing the mean-square error between the encoded signals and the result of the Wiener filtering. The receiver may also include a soft decoder for performing a soft estimation of the signals and cancelling, using the results of the soft estimation, an interference produced on the signals.

Abstract: The inventive concept enables backward-compatible extension of existing interleaver-based transmission systems to the effect that in addition to an existing logical transport channel, which is interleaved using a standardized interleaver profile, further logical transport channels may be transmitted via the same physical transmission channel. In this context, the first transport channel obviously is reduced in terms of data rate, so that the additional transport channels may actually obtain a transmission capacity that is needed accordingly. Interleaver profiles of the further logical transport channels are derived, to this end, from the interleaver profile of the first transport channel.

Abstract: Data to be more robustly transmitted within 8VSB broadcast DTV signals are turbo coded using parallelly concatenated convolutional coding (PCCC) and incorporated within the segments of data fields, the bytes of which are convolutionally interleaved before trellis coding and 8VSB symbol mapping. Packing the PCCC into payload fields of MPEG-2-compatible null data packets and Reed-Solomon coding the packets to generate the segments of data fields, the bytes of which are convolutionally interleaved, conditions legacy DTV receivers to disregard PCCC components not useful to them. Transversal packing turbo-coded Reed-Solomon codewords into the payload fields of MPEG-2-compatible null data packets increases the capability of those turbo-coded Reed-Solomon codewords to overcome burst errors. Repeated transmissions of the transversally packed turbo-coded Reed-Solomon codewords in whole or in part allows them to overcome protracted deep fades encountered during mobile reception of 8VSB DTV signals.

Abstract: Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size. A novel means is presented by which any desired turbo code block size can be employed when only requiring, in only some instances, a very small number of dummy bits. This approach also is directly adaptable to parallel turbo decoding, in which any desired degree of parallelism can be employed. Alternatively, as few as one turbo decoder can be employed in a fully non-parallel implementation as well. Also, this approach allows for storage of a reduced number of parameters to accommodate a wide variety of interleaves.

Abstract: A margin decoding communications system includes a circuit receiving a message encoded by an iterative code and processing the message into scores. A normalization process module receives the scores and iteratively approximates log-map normalization factors of the scores to generate approximation normalization factors. An element receives the message and the approximation normalization factors and decodes the received message based on the approximation normalization factors.

Abstract: A method of embedding the edit distance metric into the Hamming distance metric with low distortion. In other words, two input character strings are mapped to two corresponding output bit strings such that the Hamming distance between the output strings is approximately proportional to the edit distance between the two corresponding input strings.

Abstract: Disclosed is an apparatus having a detector for an iterative LDPC-coded MIMO-OFDM system, where the detector is configured to use a structured irregular LDPC code in conjunction with a belief propagation algorithm. Also disclosed is an apparatus having a detector for a structured irregular LDPC-coded MIMO-OFDM system, where the detector is configured to use an iterative Recursive Least Squares-based data detection and channel estimation technique. Corresponding methods and computer program products are also disclosed.

Abstract: An apparatus and method for transmitting and receiving a signal in a communication system are provided. The signal transmission apparatus generates a parity check matrix for an LDPC code in accordance with a code rate to be used and generates a codeword vector by encoding an information vector using the parity check matrix. When the code rate is a first code rate, the signal transmission apparatus generates a first parity check matrix as the parity check matrix for the LDPC code. When the code rate is the second code rate, the signal transmission apparatus generates a second parity check matrix supporting a second code rate lower than the first code rate by adding columns of a degree of 1 and columns of a degree of 2 to the first parity check matrix and generates the second parity check matrix as the parity check matrix for the LDPC code.

Abstract: A system includes a supernode generator module configured to generate supernodes. Each of the supernodes includes a plurality of symbol nodes. A supernode splitting module is configured to split each of the supernodes into derived symbols. The total number of edges of the derived symbols in each of the supernodes is equal to a predetermined number of edges of each of the supernodes.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: Provided are an apparatus and method for receiving a signal in a communication system, in which a signal is received and decoded by setting an offset indicating a start position of a node operation for each block column of a parity check matrix of a Low Density Parity Check (LDPC) code and scheduling an order of performing the node operation on a Partial Parallel Scheduling (PPS) group basis. Here, the parity check matrix includes p×L rows and q×L columns, the p×L rows are grouped into p block rows, the q×L columns are grouped into q block columns, and each PPS group includes one column from each of the q block columns.

Abstract: In a communication system, a transmitter receives an input bit, and in response thereto, generates at least an n-bit codeword, each bit of which is generated by a respective one of n generators of which m are exactly the same, m being greater than n/2. A receiver comprises: m detectors, each adapted to receive the bit generated by a respective one of the m generators, and provide a respective one of m partial detection signals if a strength of the received bit exceeds a predetermined minimum threshold; and a majority logic element adapted to receive each of the m partial detection signals, and provide an output bit indicative of the input bit only if more than m/2 of the received m partial detection signals exceeds the minimum threshold.

Abstract: A method is for decoding a succession of blocks of data encoded with an LDPC code. The method includes storing the blocks temporarily and successively in an input memory before decoding the blocks successively in an iterative manner, the input memory having a memory size for storage of at least two blocks, and defining a current indication representative of a threshold number of iterations for decoding a current block. The method includes decoding the current block until a decoding criterion is satisfied or so long as a number of iterations performed for decoding the current block has not reached the current indication while at least one of a first subsequent block and a part of a second subsequent block are stored in the input memory, and updating the current indication for decoding the first subsequent block as a function of the number of iterations performed for decoding the current block.

Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in QPSK/8PSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: Various example embodiments are disclosed relating to efficient techniques for error detection and authentication in wireless networks. For example, according to an example embodiment, an apparatus adapted for wireless communication in a wireless network may include a processor. The processor may be configured to transmit a message including a field to provide both authentication and error detection for the message. The field may include an authenticated checksum sequence.

Abstract: The present invention relates to a method for optimizing the FEC scheme comprising the steps of (a) receiving a batch of data packets designated for transmission; (b) choosing a number of divisors having no common denominators in accordance with the said batch of data packets; (c) organizing into blocks said batch of data packets a number of times in accordance with the number of divisors using said divisors; and (d) creating a FEC packet for each of said blocks.

Abstract: An almost regular permutation (ARP) interleaver and method generate interleaved indices in a sequential fashion based on a process in which each interleaved index is a function of an adjacent index. Based on the data block size (N) for a received data block and a constant (C) for the ARP interleaver, a plurality of interleaved indices is generated. For one embodiment in which the interleaved indices are generated in forward sequence, the adjacent interleaved index is the immediately previous index, P(j?1), and each interleaved index (P(j)) is generated based on incrementing the previous interleaved index (P(j?1)) by an incremental value k(i), where j represents a non-interleaved index between 0 and N?1, i represents a modulo-C counter index that corresponds to j, k(i) represents the i-th value of a set of incremental values associated with N and C.

Abstract: Disclosed is a transmission device which transmits a systematic code obtained by adding parity bits to information bits. When the code rate of the systematic code is a value in a specific range determined by the decoding characteristic in a case where dummy bits are not inserted, a dummy bit insertion portion inserts dummy bits into the information bits and shifts the decoding characteristic, so that the code rate assumes a value outside a specific range determined by the decoding characteristic after shifting. An encoding portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the encoding to generate a systematic code, and a rate matching portion, performs rate matching such that the size of the systematic code is equal to a size determined by the physical channel transmission rate, and transmits the systematic code.

Abstract: An apparatus and method for improving turbo code performance in a communication system are provided. In the apparatus, a bit inserter inserts a predetermined number of bits into a transmission information bit stream, if the effective coding rate of a transmission packet is a predetermined coding rate. A turbo encoder turbo-encodes a bit stream received from the bit inserter and outputting code symbols. A rate matcher matches the code symbols to a predetermined size.

Abstract: A Serially Concatenated Convolutional Code (SCCC) decoding system includes an outer decoder module (208), permutation module (104), and data store (114). The outer decoder module is configured to generate a first sequence of soft-decision bits x[n] for n=0, 1, 2, . . . , N?1. The permutation module is configured to permute the first sequence of soft-decision bits x[n] to generate a second sequence of soft-decision bits y[n]. The first sequence of soft-decision bits x[n] is generated by the outer decoder module in accordance with a mapping v[n]. The second sequence of soft-decision bits y[n] is generated for communication to an inner decoder module (204). The data store contains a mapping v[n]. The mapping v[n] satisfies a mathematical equation v[k+m·(N/M)] modulo (N/M)=v[k] modulo (N/M) for m=0, . . . , M?1 and k=0, . . . , (N/M?1). (NM) is an integer.

Abstract: There is provided a parity check encoder (100) comprising a data memory (PPDM) configured for storing input data, a calculation/parity result data store (CPRDS), and a selector/serializer (SS). The CPRDS (104,106) is coupled to the PPDM (102) and is configured to calculate parity bits in parallel using input data and information contained in a parity check matrix H. The SS (108) is coupled to the PPDM and CPRDS. The SS is configured to generate an encoded output sequence using the input data and parity bits. The matrix H is formed of a plurality of sub-matrices. Each sub-matrix of the sub-matrices is an all zero (0) matrix, an identity matrix, or a circular right shifted version of the identity matrix. A portion B of the matrix H includes a plurality of rows having two (2) ones (1), except for a first row which includes a single one (1).

Abstract: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. A second data processor inserts a linking block on a boundary portion between unit blocks in the record data. The unit blocks are adjacent to each other. The linking block includes a second identification information and the second identification information is different from each of the first identification information. A controller controls to record the unit block and the linking block on the information recording medium.

Abstract: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.

Abstract: A method and a circuit for decoding a coded signal including a first decoding system capable of receiving the coded signal and of providing a first signal comprising portions considered correct and a second decoding system capable of providing a second signal from the coded signal and from portions considered correct of the first signal.

Abstract: A decoding apparatus and method are described. The decoder includes N successive decoder groups numbered 1 to N arranged in series. Each decoder group includes primary decoding means for decoding the first sequence of codewords in combination with the source sequence of symbols to produce a sequence of primary decoded symbols; intermediate interleaving means for interleaving the sequence of primary decoded symbols using intra-block permutations on the source sequence of symbols and inter-block permutations on each intra-block permuted block across the predetermined number of the intra-block permuted blocks to produce a sequence of intermediate symbols; secondary decoding means for decoding the second sequence of codewords in combination with the sequence of intermediate symbols and a sequence of interleaved source symbols to produce a sequence of secondary decoded symbols; and de-interleaving means for de-interleaving the sequence of secondary decoded symbols to produce a sequence of estimated symbols.

Abstract: Methods and systems for modifying DOCSIS-based transmission paths for communication in higher frequency and/or wireless environments, such as wireless terrestrial communication systems and satellite communication systems. An inner turbo-code is combined with a DOCSIS based Reed-Solomon (“RS”) forward error correction (“FEC”) coding scheme, to produce a concatenated turbo-RS code (other FEC codes can be utilized). In phase and quadrature phase (“I-Q”) processing is utilized to enable relatively low cost up-converter implementations. The I-Q processing is preferably performed at baseband, essentially pre-compensating for analog variations in the transmit path. Power amplifier on/off control capable of controlling on/off RF power control of remote transmitters is modulated on a transmit cable to reduce the need for a separate cable.

Abstract: Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Abstract: An apparatus and a method for receiving a signal in a communication system using a Low Density Parity Check (LDPC) code. The apparatus and the method includes decoding a received signal according to a hybrid decoding scheme, wherein the hybrid decoding scheme is generated by combining two of a first decoding scheme, a second decoding scheme, and a third decoding scheme.

Abstract: An apparatus for random parity check and correction with BCH code is provided, including a Bose-Chaudhuri-Hocquenghem (BCH) parity check code encoder, a channel, a BCH parity check code decoder, and a static random access memory (SRAM). The BCH parity check code encoder uses the BCH encoding to encode the parity check code in writing to flash memory. The channel is connected to the BCH parity check code encoder to compute the parity check code and the message polynomial into receiving data. The BCH parity check code decoder is connected to the channel for inputting the receiving data and using BCH decoding to compute the eigen value and error address. The SRAM is connected to the BCH parity check code decoder so as to read error address from static RAM, correct the data and restores the corrected data to the SRAM. Therefore, this achieves the object of random parity check and correction with BCH code.

Abstract: A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder.

Abstract: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable.

Abstract: A digital broadcasting transmission system processes dual transport stream (TS) including multi turbo streams. The digital broadcasting transmission system includes a turbo processor to detect a turbo stream from a dual transport stream (TS) which includes a multiplexed normal stream and a turbo stream, encoding the detected turbo stream and stuffing the encoded turbo stream into the dual TS; and a transmitter to trellis-encode the processed dual TS, and to output the resultant stream, wherein the turbo processor encodes the turbo stream using a plurality of turbo processors. Accordingly, a plurality of turbo streams may be processed in parallel.

Abstract: A method for encoding data is disclosed. The method can include receiving a first bit segment (K?1 bits) from a bit stream, storing the first bit segment, initializing an encoder with the first bit segment, start encoding and transmitting from the Kth bit to the end of the appended data stream, and appending the first bit segment (K?1 bits) to the end of the data stream. The disclose arrangements can be similar to tail-biting methods different in that the initial bits are utilized to initialize the encoded as opposed to the tail or last bit as provided by tailbiting methods.

Abstract: Methods and apparatus for coding a digital data string to represent a sequence of acoustic frequencies to be transmitted as an acoustic signal by a genuine acoustic authentication device; related to providing for improving the rate of successfully detecting a valid data string contained in the acoustic signal transmitted by the device. Each of a plurality of groups of bits of the data string are coded to represent a respective frequency value set of one or more acoustic frequencies to be transmitted acoustically to represent the respective group of bits. The number of acoustic frequencies in a frequency value set is less than the number of bits in the respective group of bits that the frequency value set represents. For each of the plurality of groups of bits of the data string, the respective frequency value set is selected according to a predetermined frequency assignation pattern that provides for probabilistic transition coding used for error correction of the acoustic signal.

Abstract: A control channel encoder, e.g., in a UMB system, uses a channel structure that can efficiently transmit more information bits, yet achieve sufficient detection and false alarm performance. The control channel encoder uses tail-biting convolutional coding and Cyclical Redundancy Check (CRC).

Abstract: A receiver for the geosynchronous (GEO) satellite reverse link, which uses the tail-biting convolutional code for error control, and methods to solve the problem of channel estimation is described. The channel estimate is initialized at each state using the pilot channel. Branch metric computation is used for circular decoding of the tail-biting convolutional code. The technique is effective when partial tail-biting is implemented.

Abstract: A method of transmitting a spread spectrum signal in a single communication session between a transmitter and a receiver, stores a series of N unique waveform designs and a hopping sequence in a transmitter memory. A signal is transmitted to a receiver according to the hopping sequence using the plurality of N unique waveform designs. Preferably, each waveform design is characterized by a unique composite spreading code that is formed by at least some of a plurality of constituent code segments. Alternatively or additionally, the waveform designs may differ by any one or more of code length, symbol or chip timing or phase, frame or burst structure, chip offset, modulation, error control coding, encryption scheme, or scrambling code. A transmitter and receiver are also disclosed, as is the concept of appending chips between symbols to expand the universe of unique spreading codes without incurring an increase in processing gain.

Abstract: Disclosed is a method and communication device for suppressing interference. The method comprises performing, with a turbo decoder (314), at least one turbo decoding attempt (1106) on a received signal (1104). The turbo decoding attempt generates at least one whole word code bit therefrom (1108). The whole word code bit (1108) corresponds to a group of bits comprising a transmitted symbol. The method determines if the whole word code bit (1108) has a confidence level exceeding a given threshold (1110). If the whole word code bit (1108) does have a confidence level exceeding the given threshold, the whole code word bit is selected for use in data symbol recovery (1114).

Abstract: An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical expression is used to perform an evaluation of the characteristic of an error floor area without using any computer experiments. In a polynomial multiplying block 1, (n?1)-th-order polynomial multiplying units (12-1 to 12-(m?1)) further divide an information bit string, which has been blocked for an error correction encoding, into (m?1) blocks having a length n and a single block having a length (n?r) (where m and n represent integers equal to or greater than two and where r represents an integer between 1 and n inclusive); receive blocks, which have the length n, of divided information bit strings; and output a series having the same length.

Abstract: A data transmitter and receiver for improving a data rate, and more particularly, to an apparatus and method of transmitting and receiving an orthogonal frequency division multiplexing (OFDM) symbol in which a pilot signal is added to a data signal is provided.

Abstract: Variable modulation with LDPC (Low Density Parity Check) coding provides for generation of LDPC coded symbols having different respective code rates and/or modulations. In addition, appropriate LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, and/or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis.

Abstract: In one embodiment, a (hard-drive) read channel has a phase detector used in a timing recovery loop. The phase detector utilizes the sign bit and confidence value from a received log-likelihood ratio (LLR) signal to generate a mean value. The mean value is convolved with a partial response target to generate an estimated timing error signal. When implemented in a hard-drive read channel, the phase detector allows for timing recovery with lower loss-of-lock rates.

Abstract: The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.

Abstract: A 2-dimensional interleaving method is disclosed. The method comprises dividing a frame of input information bits into a plurality of groups and sequentially storing the divided groups in a memory; permuting the information bits of the groups according to a given rule and shifting an information bit existing at the last position of the last group to a position preceding the last position; and selecting the groups according to a predetermined order, and selecting one of the information bits in the selected group.