Abstract: A method, system, apparatus, and computer program product for decoding control information, wherein a total number of allocation blocks defining control channels to be allocated to users for at least one of uplink and downlink directions is determined. Then, a format which determines resource allocation within allocation blocks is selected, allocation blocks are decoded using the selected format, and an error checking is performed for the decoded allocation blocks. This selecting, coding and error checking is repeated for different available formats until no error is revealed in said error checking. Thereby, a blind estimation of a format chosen for the control channel information can be achieved, so that additional amount of control signalling can be reduced.

Abstract: The systematic and parity bits of a symbol are tightly coupled to each other based on the way in which the symbol is encoded. The relationship between the systematic and parity bits can be exploited to improve the accuracy of soft bit estimation for both the systematic bits and parity bits. In one embodiment, a received symbol is processed by demodulating the received symbol to determine an initial soft estimate of each systematic bit and corresponding one or more parity bits in the sequence. The systematic bit sequence is iteratively decoded to revise the soft estimate of the systematic bit. The initial soft estimate of the one or more parity bits associated with each systematic bit is revised based on the revised soft estimate of each systematic bit. The received symbol can be decoded or regenerated based on the revised soft estimate of each systematic bit and corresponding one or more parity bits.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived from a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.

Abstract: Aspects of a method and system for feedback of decoded data characteristics to decoder in stored data access and decoding operations to assist in additional decoding operations are presented. Aspects of the system may include a decoder that enables decoding of a portion of encoded data. A processor may enable generation of at least one hypothesis based on the decoded portion of encoded data and/or redundancy information associated with at least the decoded portion of the encoded data. The decoder may enable generation of one or more subsequent portions of decoded data based on the generated at least one hypothesis.

Abstract: The disclosure relates to optical fiber transmission systems, and in particular, pertains to the transceiver cards in an optical fiber transport system. In particular the disclosure teaches an improved transceiver card architecture that allows high density, flexibility and interchangeability of functionality.

Abstract: A pruned bit-reversal interleaver supports different packet sizes and variable code rates and provides good spreading and puncturing properties. To interleave data, a packet of input data of a first size is received. The packet is extended to a second size that is a power of two, e.g., by appending padding or properly generating write addresses. The extended packet is interleaved in accordance with a bit-reversal interleaver of the second size, which reorders the bits in the extended packet based on their indices. A packet of interleaved data is formed by pruning the output of the bit-reversal interleaver, e.g., by removing the padding or properly generating read addresses. The pruned bit-reversal interleaver may be used in combination with various types of FEC codes such as a Turbo code, a convolutional code, or a low density parity check (LDPC) code.

Abstract: A tree decoding method for decoding a linear block code is provided. According to the tree decoding method, an estimated path metric of node v is f(v)=g(v)+h(v), where g(v) represents a sum of bit metrics of all bits on a path from the root node to the node v, and h(v) represents a lowest bound of estimated accumulated bit metrics from the node v to the goal node. The present invention creatively improves the approach for calculating h(v). According to the present invention, some parity bits are only related to a part of the information bits, according to which the edge metric h(v) of the parity bits can be preliminarily incorporated into the path metric of the part of the information bits. As such, some nodes having inferior path metric could be eliminated in advance, thus minimizing the searching range and simplifying the decoding complexity.

Abstract: An apparatus and method for decoding a channel code is disclosed. The method for decoding a channel code includes the steps of receiving a low density parity check (LDPC) encoded signal from a transmitting party, generating a parity check matrix by adjusting the order of rows or columns of the parity check matrix, the parity check matrix including a plurality of groups consisting of a plurality of columns, at least one of the groups including at least one row of which every element is zero (0), and iteratively decoding the received signal for each group by using the generated parity check matrix.

Abstract: Block modulus coding (BMC) systems implement block coding on non-binary modulus m symbols, where m is greater than 2. BMC systems can be used for, among other things, forward error correction (FEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data is represented by non-binary symbols that may be corrupted by burst errors. The block coding is preferably performed using a distributed arrangement of block encoders or decoders. A distributed block modulus encoder (DBME) encodes sequential source data symbols of modulus m with a plurality of sequential block encoders to produce interleaved parity codewords. The codewords utilize modulus m symbols where the medium can reliably resolve m symbol states. The interleaved parity codewords enable decoding of error-corrected source data symbols of modulus m with a distributed block modulus decoder (DBMD).

Abstract: A data communications system having a plurality of processing devices connected to a serial via a serial bus interface. The processing device provides a communication control line which connects each processing device in order and performs the transfer of transmission right of the serial bus, a transmission right management unit which is connected to the communication control line, performs the transfer of the transmission right and manages the state of the transmission right within its own processing device, a data transmission unit which starts data transmission when the transmission right is valid and holds the data transmission when the transmission right is invalid, and a state initialization unit which sets the initial state of the transmission right so that the transmission right of only one processing device is made to be valid at the initialization.

Abstract: A data processing system for processing digital data with a low density parity check (LDPC) matrix includes: a storage device for storing a plurality of indices representing a plurality of shifting numbers, where the LDPC matrix comprises an array of elements, and at least one element of the LDPC matrix represents a cyclic permutation matrix that is produced by cyclically shifting columns of an identity matrix to the right according to one of the shifting numbers; and a processing circuit, coupled to the storage device, for retrieving at least one index to recover at least one element of the LDPC matrix according to the index and performing data processing according to the LDPC matrix.

Abstract: Encoding and/or decoding of messages. On the encoding end, a composite encoder encodes message from an internal format that is used by internal system components into an external format. However, the composite encoder may encode the outgoing messages into different external formats on a per-message basis. For incoming message, a composite decoder decodes incoming messages from any one of a plurality of external formats into the internal format also on a per-message basis. A per-message report mechanism permits internal system components and the encoding/decoding components to communicate information regarding the encoding or decoding on a per message basis. This permits a higher level of collaboration and complexity in the encoding and decoding process.

Abstract: An approach is provided for encoding information bits to output a coded signal using turbo code encoding with a low code rate.

Abstract: A storage system comprises a linear block encoder. A write circuit writes an output of the linear block encoder to a storage medium. A read circuit reads data from the storage medium. A channel decoder decodes the data. A soft linear block code decoder that decodes the data decoded by the channel decoder. The channel decoder decodes the data read in a first iteration. In a subsequent iteration the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block code decoder. A threshold check circuit selects an output of the soft linear block code decoder if a number of parity check violations has a first relationship with respect to a threshold, or an output of the channel decoder if the number of parity check violations has a second relationship with respect to the threshold.

Abstract: A method and apparatus for decoding a frame control header message in a wireless communication transmission are disclosed. The method comprises assuming at least some of the bits comprising the frame control header message are constant across multiple frames or are known a priori and generating metrics at least from the bits of the frame control header message that are assumed to be constant or are known a priori. The method further comprises decoding the metrics, for example, with a Viterbi decoder or using chase combining, to yield the decode frame control header message.

Abstract: In one embodiment, the present patent application comprises a method and apparatus to generate low rate protographs from high rate protographs, comprising copying a base graph; permuting end points of edges of a same type in copies of the base graph to produce a permuted graph; and pruning systematic input nodes in the permuted graph and the edges connected to them. In another embodiment, the present patent application comprises a method and apparatus to generate high-rate codes from low-rate codes, comprising puncturing a subset of codeword bits, wherein the step of puncturing a subset of codeword bits comprises regular-irregular puncturing the subset of codeword bits, random puncturing variable nodes, or progressive node puncturing variable nodes to obtain a desired code from a preceding code.

Abstract: A unified decoder is capable of decoding data encoded with convolutional codes, Turbo codes, and LDPC codes. In at least one embodiment, a unified decoder is implemented within a multi-standard wireless device.

Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

Abstract: A network component comprising a processor configured to implement a method that comprises applying a forward error correction (FEC) algorithm to a plurality of data blocks to generate a plurality of redundancy data, encapsulating an integer number of the data blocks and the redundancy data in an FEC codeword, and transmitting the FEC codeword, wherein the codeword is about evenly aligned with a transmission clock time quanta to have a transmission rate. A method comprising selecting an FEC algorithm that generates a plurality of redundancy data from a plurality of data blocks, selecting an EEC codeword that encapsulates an integer number of the data blocks, and selecting a synchronization pattern to add to the FEC codeword such that an integer number of the FEC codewords are evenly aligned with an integer number of transmission clock time quanta.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data receiving system is disclosed that includes a data signal provided from a medium that may include a defective portion. An absolute value circuit receives the data signal and provides an output corresponding to an absolute value of the data signal. The output corresponding to the absolute value of the data signal is input to a filter that filters it and provides a filtered output. In some cases, the filter is a digital filter operable to integrate the absolute value of the data signal. A comparator receives the output from the filter and compares it with a threshold value. The result of the comparison indicates a defect status of the medium.

Abstract: A system comprising a plurality of channel detectors (CDs) receiving quantized and equalized ISI channel information indicative of an LDPC codeword. The channel information is split for input to the CDs, such that each CD receives channel information indicative of a portion of the LDPC codeword. Each CD outputs at least first soft information for bits of the codeword portion of that CD. The first soft information for the codeword is received by an LDPC decoder, which uses the soft information to produce a user bit sequence and second soft information about the user bit sequence. The system can cause the second soft information to be input to the plurality of CDs, such that iterative processing can occur for the codeword. Other aspects include a system providing clocking of one or more CDs at a frequency selected to balance codeword throughput of the CDs with codeword throughput of an LDPC decoder clocked by a second clock, and methods according to each system.

Abstract: Methods and apparatus for encoding data in a communication network. In an aspect, a method is provided for coding data. The method includes generating one or more permutations of the data, determining weights associated with each permutation, calculating one or more code packets from each permutation based on the associated weights, and multiplexing the data and the one or more code packets into a code packet stream. In an aspect, an apparatus is provided for coding data. The apparatus includes permutation logic configured to generate one or more permutations of the data, and weight logic configured to determine weights associated with each permutation. The apparatus also includes processing logic configured to calculate one or more code packets from each permutation based on the associated weights, and a multiplexer configured to multiplex the data and the one or more code packets into a code packet stream.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: An adaptive sliding block Viterbi decoder (ASBVD) includes forward and backward Viterbi processors, a state estimator and a control unit. The processors generate metrics of states and of transitions between the states associated with an encoder, based on encoded input information symbols received via a communications channel. Each processor includes a plurality of buffers for storing information symbols so that a number of the encoded input information symbols can be concurrently decoded. The state estimator estimates a current state of a code trellis based on the generated metrics, and the processors decode the stored information symbols based on the estimated current state. The control unit adapts the number of encoded input information symbols to be concurrently decoded based on a condition of the communications channel, and selectively controls the number of buffers that are enabled in accordance with the number of encoded input information symbols to be concurrently decoded.

Abstract: A system may be used to predict when a decoding process will fail to correct an error burst within a transmission. A decoder may receive an input bit stream and process it to produce an output bit stream, which may be convolutionally encoded. K-bits of the convolutionally encoded output bit stream may be compared with a corresponding k-bits of a delayed version of the input bit stream, with the k-bits starting at a first bit and ending at first bit+k. For each bit of the k-bits in the convolutionally encoded output bit stream and in the corresponding k-bits of the delayed version of the input bit stream, a number of conflicting bits and whether the number of conflicting bits exceeds a threshold number of conflicting bits may be determined. The output bit stream may be sent to a block decoding component for decoding with the bits marked for erasure.

Abstract: A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code.

Abstract: The subject matter disclosed herein provides an outer coding framework that, in some implementations, provides frequency diversity to outer codewords that are mapped to modulation symbols. In one aspect, there is provided a method. The method may include inserting a received packet into a frame. Moreover, an outer code may be used to encode the frame. Furthermore, the values read from a column of the frame may be inserted into a link-layer packet. In addition, the column may be shuffled by moving the values of the column based on an offset. The link-layer packet may also be provided to enable an inner code to encode the link-layer packet before transmission. Related systems, apparatus, methods, and/or articles are also described.

Abstract: A turbo decoding apparatus comprises: a backward-probability calculation unit that executes backward-probability calculation from time N to time 0 with respect to coded data having an information length N (N is a natural number) which is encoded with turbo-encoding; a storage unit to store backward-probability calculation results extracted from a plurality of continuous backward-probability calculation results regarding a predetermined section of at intervals of n-time; a forward-probability calculation unit that executes forward-probability calculation from time 0 to time N with respect to the coded data; and a decoded result calculation unit that calculates a decoded result of the coded data through joint-probability calculation using forward-probability calculation results by the forward-probability calculation unit and the backward-probability calculation results stored in the storage unit and backward-probability calculation results obtained through recalculation by the backward-probability calculation u

Abstract: A method constructs a code, wherein the code is a large-girth quasi-cyclic low-density parity-check code. A base matrix is selected for the code. A cost matrix corresponding to the base matrix is determined. A single element in the base is changed repeatedly maximize a reduction in cost. A parity check matrix is constructing for the code from the base matrix when the cost is zero, and an information block is encoded as a code word using the parity check matrix in an encoder.

Abstract: Where two or more multi-valued digital data symbols are modulated so that they overlap after passing through a channel, forming a combined signal, a receiver receives the combined signal and forms detection statistics to attempt to recover the symbols. Where forming detection statistics does not completely separate the symbols, each statistic comprises a different mix of the symbols. A receiver determines the symbols which, when mixed in the same way, reproduce or explain the statistics most closely. For example, the receiver hypothesizes all but one of the symbols and subtracts the effect of the hypothesized symbols from the mixed statistics. The remainders are combined and quantized to the nearest value of the remaining symbol. For each hypothesis, the remaining symbol is determined. A metric is then computed for each symbol hypothesis including the so-determined remaining symbol, and the symbol set producing the best metric is chosen as the decoded symbols.

Abstract: A method to receive a signal transmitted over a transmission link comprising coded channels, the method comprising: —equalization operations (110-116) to compensate for signal distortion introduced by the transmission link in a signal burst, and—block decoding operations (120-126) to perform channel decoding operation from the equalized signal bursts. If one of the block decoding operations has not been executed before a predetermined time limit, the method comprises at least one step (146) of discarding one of the next burst equalization operations.

Abstract: Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.

Abstract: A device including a minimal trellis decoder is disclosed. The device can receive an encoded codeword, which the minimal trellis decoder efficiently decodes. In a specific implementation, the device can include a Bluetooth receiver that, in operation, receives an encoded codeword from a Bluetooth transmitter, which is decoded by the minimal trellis decoder.

Abstract: Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Abstract: By controlling to select encoding appropriately considering characteristics of equalization and decoding of a receiving apparatus employing a turbo equalization technology, it is possible to attain a high transmission characteristic. Information bits of two systems including a sequence which is input to a first RSC encoding unit 22 and a sequence which is input through an interleaving unit 21 to a second RSC encoding unit 23 are set for input information bits, and each of which is subjected to RSC encoding. Each encoded parity bit is input to a puncturing unit 24. Since a systematic bit obtained by the first RSC encoding unit 22 is the information bit itself, a systematic bit obtained by the second RSC encoding unit 23 is not transmitted. In the puncturing unit 24, while puncturing is applied according to a predetermined coding rate, selection of either an RSC code or a turbo code is carried out by a puncturing control unit 25.

Abstract: The invention provides methods and systems for terminating an iterative decoding process of a Forward Error Correction block (FEC). The iterative decoding process of the FEC block is terminated upon determining that the FEC block cannot be decoded successfully. A method comprises calculating a metric based on one or more Log Likelihood Ratios (LLRs) corresponding to a first number of iterations of the iterative decoding process of the FEC block. The method further comprises, formulating one or more stopping criteria for the iterative decoding process based on a variation pattern of the metric over a second predetermined number of iterations of the iterative decoding process. The second predetermined number of iterations is a subset of the first number of iterations. Moreover, the method comprises terminating the iterative decoding process of the FEC block based on the one or more stopping criteria.

Abstract: A method of transmitting data that includes controlling generation of bit sequences to adjust an occupation rate occupied with predetermined bits included in a first data block, which is obtained by encoding first data in a first encoding process, to be equal or closer to an occupation rate occupied with predetermined bits included in a second data block, which is obtained by encoding second data in a second encoding process, in regard to first bit positions of the bit sequences generated using bits included in the first and second data blocks; and performing multi-level modulation for transmission based on the generated bit sequences.

Abstract: Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.

Abstract: There is provided with a decoding apparatus for decoding a low-density parity check code defined by a parity check matrix, includes: a first operation unit configured to carry out a row operation for each row of the parity check matrix; a calculation unit configured to calculate a reliability coefficient with respect to establishment of a parity check equation defined by said each row, respectively; a second operation unit configured to carry out a column operation for said each row; and a controller configured to iteratively execute one set which includes respective processing by the first operation unit, the calculation unit and the second operation unit and omit the processing by the first operation unit and the calculation unit for a row for which the reliability coefficient has satisfied a threshold.

Abstract: Systems and methods are provided for encoding a stream of datawords based on a tensor product code to provide a stream of codewords, and detecting and decoding a stream of received data based on a tensor product code to provide a decoded stream of data. In one aspect, the tensor product code is based on two codes including an inner code and an outer parity hiding code, where the outer parity hiding code is an iterative code. In certain embodiments, the outer parity hiding code is a Turbo code or a low density parity check (LDPC) code.

Abstract: This invention relates to a method and a circuit for estimating the bit error rate in a data transmission system. Symbols are detected (u) by a maximum likelihood detector (1), which provides path metrics of the decoded path and the best competitor at predetermined symbol positions. Absolute path metric differences (2) are calculated between the decoded path and the best competitor at said predetermined symbol positions. Events (5) are counted when an absolute path metric difference (2) is equal to one of a set of difference values. The bit error rate is estimated based on the number of counted (4) events (5). The invention further comprises a method and a circuit in which a function is applied onto said absolute path metric difference. The function maps quantized logarithms of probabilities to probabilities.

Abstract: In a frame sync method, a receiver searches for the presence of an N-symbol long unique word pattern. For each possible frame sync detected, the receiver proceeds to demodulation and FEC processing. After each iteration of the FEC decoder, the detected unique word pattern is compared to the expected one and the frame sync is detected if the number of unique word errors has decreased.

Abstract: A digital broadcasting system for transmitting/receiving a digital broadcasting signal and a data processing method are disclosed. First program table information and second program table information, which has an identifier different from an identifier of the first program information, are multiplexed and transmitted. The first program table information describes main service data through fixed reception channel, while the second program information described mobile service data through mobile reception channel. Thus, a broadcast receiving system can receive and output the mobile service data by parsing the second program table information.

Abstract: A transmitting apparatus, that includes a means for generating bit sequences to adjust an occupation rate occupied with predetermined bits included in a first data block, which is obtained by encoding first data in a first encoding process, to be equal or closer to an occupation rate occupied with predetermined bits included in a second data block, which is obtained by encoding second data in a second encoding process, in regard to first bit positions of the bit sequences generated using bits included in the first and second data blocks and a modulator for performing multi-level modulation for transmission based on the generated bit sequences.

Abstract: A digital television (DTV) transmitter and a method of processing data in the DTV transmitter/receiver are disclosed. In the DTV transmitter, a pre-processor pre-processes the enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded data. A packet formatter generates one or more groups of enhanced data packets, each enhanced data packet including the pre-processed enhanced data and known data, wherein the data formatter adds burst time information into each group of enhanced data packets. And, a packet multiplexer generates at least one burst of enhanced data by multiplexing the one or more groups of enhanced data packets with at least one main data packet including the main data, each burst of enhanced data including at least one group of enhanced data packets.

Abstract: In a decoding apparatus in a portable Internet terminal, a channel encoded symbol received from a transmitter is decoded by one of a chase-combining scheme and a code-combining scheme selected based on an ID value of the subpacket indicating a start position of the symbol. In this case, the chase-combining scheme is partly used for the encoded symbol of the information bit. With such a mode, decoding can be performed at a low code rate.

Abstract: Tail-biting turbo coding to accommodate any information and/or interleaver block size. The beginning and ending state of a turbo encoder can be made the same using a very small number of dummy bits. In some instances, any dummy bits that are added to an information block before undergoing interleaving are removed after interleaving and before transmission of a turbo coded signal via a communication channel thereby increasing throughput (e.g., those dummy bits are not actually transmitted via the communication channel). In other instances, dummy bits are added to both the information block that is encoded using a first constituent encoder as well as to an interleaved information block that is encoded using a second constituent encoder.

Abstract: System for managing a life cycle of a virtual resource. One or more virtual resources are defined. The one or more defined virtual resources are created. The created virtual resources are instantiated. Then, a topology of a virtual resource is constructed using a plurality of virtual resources that are in at least one of a defined, a created, or an instantiated state.

Abstract: A 2-dimensional interleaving method is disclosed. The method comprises dividing a frame of input information bits into a plurality of groups and sequentially storing the divided groups in a memory; permuting the information bits of the groups according to a given rule and shifting an information bit existing at the last position of the last group to a position preceding the last position; and selecting the groups according to a predetermined order, and selecting one of the information bits in the selected group.

Abstract: Disclosed is a A system and method for joint source-channel encoding, symbol decoding and error correction, preferably utilizing an arithmetic encoder with operational error detection space; and a combination sequential, and arithmetic, encoded symbol decoder structure.