Abstract: The present invention provides a decoding method and device for Reed-Solomon (RS) codes. The method includes the following steps: A: filling data to be decoded in a byte interleaver by column in turn; B: performing cyclic shift to data in a check region of the byte interleaver by row and/or by column, so as to make the data of each row in the check region become check data in sequence of data of corresponding row in an information region of the byte interleaver; C: performing RS decoding by row method, and writing information data of each row obtained after decoding into the corresponding row in the information region of the byte interleaver in turn; and D: reading business data of the decoded information data from the information region of the byte interleaver by column. The method and device of the present invention can achieve the best interleaving effect.

Abstract: An error correction code of (N+M) words is configured by adding an ECC parity of M word (M is a natural number) to N words extracted at an interval of A words with respect to data of (A*N) words (A and N are natural numbers) inputted via an interface 1. A data distributor 3 distributes (N+M) words to the respective (N+M) physical blocks to record by A words. In a case where a writing error has occurred, data recorded in a cell sharing page of the page and in a page of another physical block configuring the error correction code is read. A disappearing correction is carried out to the data of the cell sharing page by using the data, and thus the data of the cell sharing page is recovered and written. In this manner, in the multi-level nonvolatile memory, an error in writing of a certain page can be prevented from propagating to a written page sharing a cell.

Abstract: A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The memory stores data in the form of multi-byte data words with error correction coding (ECC). In a page mode read/write operation, data states stored in memory cells of the selected row are sensed by sense amplifiers arranged in first and second banks, which are associated with first and second groups of columns. The first bank of sense amplifiers, associated with the first group of columns and containing the ECC value, are coupled to to the internal bus, followed by coupling the second bank of sense amplifiers associated with the second group of columns to the internal bus. The internal bus is then placed in tri-state, following which the internal data bus is driven with data to be written into the second group of columns in that same row, that data latched into the second bank of sense amplifiers.

Abstract: A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.

Abstract: An interface processes memory redundancy data on an application specific integrated circuit (ASIC) with self-repairing random access memory (RAM) devices. The interface includes a state machine, a counter, and an array of registers. The state machine is coupled to a redundancy chain. The redundancy chain includes coupled redundant elements of respective memory elements on the ASIC. In a shift-in mode, the interface shifts data from each of the elements in the redundancy chain and compresses the data in the array of registers. The interface communicates with a test access port coupled to one or more eFuse devices to store and retrieve the compressed data. In a shift-out mode, the interface decompresses the data stored in the array of registers and shifts the decompressed data to each unit in the redundancy chain. The interface functions absent knowledge of the number, bit size and type of self-repairing RAM devices in the redundancy chain.

Abstract: A dispersed storage system includes a plurality of storage units that each include a partial rebuild grid module. The partial rebuild grid module includes partial rebuilding functionality to reconstruct one of a plurality of encoded data slices wherein the plurality of encoded data slices are generated from a data segment based on an error encoding dispersal function. In the partial rebuilding process, a data slice is rebuilt by combining in any order slice partials generated from at least a threshold number T of the plurality of data slices.

Abstract: A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.

Abstract: A flash storage device tracks performs wear-leveling by tracking data errors that occur when dynamic data is read from a storage block of the flash storage device and moving the dynamic data to an available storage block of the flash storage device. Additionally, the flash storage device identifies a storage block containing static data and moves the static data to the storage block previously containing the dynamic data.

Abstract: A computing device boot-up method begins by a processing module detecting a boot-up of the computing device. The method continues with the processing module addressing a distributed basic input/output system (BIOS) memory to retrieve a plurality of error coded BIOS data slices. The method continues with the processing module reconstructing BIOS data from the plurality of error coded BIOS data slices using an error coding dispersal function. The method continues with the computing device booting up in accordance with the BIOS data.

Abstract: Degrees of similarity between pages from the viewpoint of metadata creation and verification can be estimated based on degrees of similarity between pages in terms of structure, style (appearance), and accessibility error, and, based on the estimation, representative pages appropriate for efficiently adding metadata can be recommended, or target pages appropriate for efficiently verifying the metadata can be recommended.

Abstract: An n-way parity protection technique enables recovery of up to n storage device (e.g., disk) failures in a parity group of a storage array encoded to protect against n-way disk failures. The storage array is created by first configuring the array with m data disks, where m=p?1 and p is a prime number and a row parity disk. n?1 diagonal parity disks are then added to the array. Each diagonal parity set (i.e., diagonal) is associated with a slope that defines the data and row parity blocks of the array that are included in the diagonal. All diagonals having a common slope within a parity group are organized as a diagonal parity class. For each diagonal parity class, a diagonal parity storage disk is provided to store the diagonal parity.

Abstract: One embodiment provides a system that protects translated guest program code in a virtual machine that supports self-modifying program code. While executing a guest program in the virtual machine, the system uses a guest shadow page table associated with the guest program and the virtual machine to map a virtual memory page for the guest program to a physical memory page on the host computing device. The system then uses a dynamic compiler to translate guest program code in the virtual memory page into translated guest program code (e.g., native program instructions for the computing device). During compilation, the dynamic compiler stores in a compiler shadow page table and the guest shadow page table information that tracks whether the guest program code in the virtual memory page has been translated. The compiler subsequently uses the information stored in the guest shadow page table to detect attempts to modify the contents of the virtual memory page.

Abstract: A sensor transmitter device for transmitting the payload data of a sensor to a bus control device is described, the sensor transmitter device being connectable to a data bus of a vehicle, which is configured for simultaneous transmission of bus data packets between a plurality of sensor transmitter devices and a bus control device. The bus data packets should include at least one signaling field and one payload data field having a plurality of payload data blocks. The sensor transmitter device includes a sensor interface for receiving payload data which represent a physical variable and a memory which is configured for storing position information which identifies at least one payload data block from the payload data field, which is reserved exclusively for the transmission of payload data from the sensor transmitter device to the bus control device.

Abstract: An error correction code includes a separate error code portion for each of two or more separate burst erasure durations (or burst error durations). For each burst erasure duration, the code can be employed to recover from the burst erasure with a different delay time. Each error code portion has a particular parameter for burst duration (B) and delay (T), meaning that the code can be used to recover from a burst erasure of duration B with delay T. Each error code portion is based on separating the source symbols into sub-symbols and diagonally interleaving the sub-symbols based on the (B,T) parameters for the error code portion. Accordingly, different burst erasures are recovered from with different delays.

Abstract: A memory system includes a nonvolatile memory, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that performs communication with a host according to an aspect of the preset invention, wherein the control circuit includes a reading unit that outputs a read enable signal to the nonvolatile memory to read data; a delay unit that delays a signal obtained by returning the read enable signal and outputs the signal as a clock, and a latch unit that latches and outputs the data read from the nonvolatile memory by using the clock output from the delay unit.

Abstract: A method and apparatus to read information from an information storage medium using a read channel, where that read channel includes a data cache. The invention generates an analog waveform comprising the information, and provides that analog waveform to a read channel, and generates a digital signal from that analog waveform using one or more first operating parameters. The method error corrects that digital signal at an actual error correction rate, and determines if the actual error correction rate is greater than an error correction rate threshold. If the actual error correction rate exceeds the error correction rate threshold, then the method captures the digital signal, stores that captured data in a data cache, reads that digital signal from the cache, generates one or more second operating parameters, and provides those one or more second operating parameters to the read channel.

Abstract: Cluster parsing for signaling within multi-user wireless communication systems. Cluster assignment allows for complete flexibility across a variety of operational parameters in accordance with communications provided from a transmitting wireless communication device to a number of receiving wireless communication devices. For example, an access point (AP) may communicate to a number of wireless stations (STAs) in accordance with multi-user multiple input multiple output (MU-MIMO), orthogonal frequency division multiple access (OFDMA), and/or MU-MIMO/OFDMA. The selectivity may involve employing different antenna for communicating with each of the respective, receiving wireless communication devices. Also, the formation of a cluster employed in such communications may involve using as few as one channel within one band, different channels within a single band, different channels within different bands, or other combinations.

Abstract: A flash-memory system is organized into a plurality of blocks and a plurality of pages in each block, each page having 2N data locations and K spare locations. At least one page in the memory has 2M user data sectors and each sector has 2N-M+L locations therein. Because L is at least 1 but less than 2N-M, user data is stored in the spare memory locations. By storing user data in spare locations that were previously off-limits to user data, enterprise-sized sectors can be efficiently stored in flash memories with little wasted memory, thereby making flash-memory systems compatible with existing hard-drive storage systems in enterprise system applications.

Abstract: A memory system includes a nonvolatile memory configured to store data, a first buffer configured to temporarily store data from the nonvolatile memory, a correction circuit configured to correct an error of data from the first buffer, a second buffer configured to temporarily store data from the correction circuit, a bus configured to receive data from the second buffer, a command sequence unit configured to issue a command for data transfer between modules, the modules including the first buffer, the correction circuit and the second buffer, and a command decode unit configured to decode the command and to generate a control signal for controlling the data transfer.

Abstract: A controller and a control method for a controller can simplify application development and can improve the performance of device control processes. When a request is received from an application 1 and the received process request is an initialization request, whether or not the received request is the first initialization request received after the application 1 started running is determined. If the received initialization request is the first initialization request, the request is passed to the device driver 3 and initialization settings information describing the configuration of the device driver 3 after the initialization process ends is stored. If an error has occurred in the device driver 3 when the device driver 3 status is detected, an error handling process is executed according to the device driver 3 state. When the device driver 3 has recovered, a request for setting the device driver 3 state to the state based on the initialization settings information is asserted.

Abstract: A method of operating a nonvolatile memory device includes performing a program operation on memory cells included in a selected page, checking whether a verification operation for the programmed memory cells is passed or failed by performing the verification operation, counting a number of error bits for the selected page, if the verification operation is failed, performing an error checking and correction (ECC) algorithm using an error correction circuit, if the counted number of error bits is less than or equal to a number of correctable bits, and storing the counted number of error bits in a specific one of a plurality of memory blocks.

Abstract: Disclosed are a flash memory device and flash memory programming method that equalizes a wear-level. The flash memory device includes a memory cell array, an inversion determining unit to generate a programming page through inverting or not inverting a data page based on a number of ‘1’s and ‘0’s in the data page, a programming unit to store the generated programming page in the memory cell array; and a data verifying unit to read the programming page stored in the memory cell array, to restore the data page from the programming page according to whether an error exists in the read programming page, and to output the restored data page, and thereby can equalize a wear-level of a memory cell.

Abstract: A user device includes a browser module, a DSN interface to a local or external DSN memory and a DS processing module coupled to the DSN interface for storing and retrieving the data object from the DSN memory, wherein the data object is divided into a plurality of data segments and wherein each of the plurality of data segments is stored in the DSN memory as a plurality of encoded data slices that are generated based on an error encoding dispersal function. The browser module is operable to interpret a user input as a request to display a data object, determine the data object is stored in the DSN memory, request the DS processing module to retrieve the data object from the DSN memory and request an application program to open the data object for display.

Abstract: A method of securely transferring data. The source data stored in a source memory (NV_MEM) is compared with the transferred data (COPY_ELT_X_V_MEM) that has been copied from the source memory (NV_MEM) into a “destination” memory (V_MEM). The method consists in reading from the source memory (NV_MEM) an integrity value (PI_ELT_X) associated with an element (ELEMENT_X_NV_MEM) such as file containing the source data, in calculating the integrity of a reconstituted element made up of the transferred data (COPY_ELT_X_V_MEM) associated, where appropriate, with the data of the source element (ELEMENT_X_NV_MEM) other than the data that was transferred, and in deciding that the transferred data (COPY_ELT_X_V_MEM) is identical to the source data when the integrity calculation gives a value identical to the integrity value of the source element (PI_ELT_X). The method applies to transferring data between components of a smart card.

Abstract: A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element.

Abstract: Provided is a signal processing device including a signal receiving unit for receiving a multilevel signal having a signal waveform that is obtained by synchronously adding an encoded signal generated based on a specific coding rule and a clock which has an amplitude larger than the encoded signal and for which the transmission speed is half that of the encoded signal, an amplitude level detection unit for detecting an amplitude level of the multilevel signal received by the signal receiving unit, a violation detection unit for detecting a bit position at which rule violation of the specific coding rule occurred, based on a change pattern of the amplitude level detected by the amplitude level detection unit, and an error correction unit for correcting a detection value of the amplitude level corresponding to the bit position detected by the violation detection unit so that the rule violation is resolved.

Abstract: Systems and methods implementing a protocol that provides reliable transport over a point-to-point link characterized by deep and sustained fades. Such a communications link may be a free space optical channel or may be a radio frequency point-to-point channel. Data frames are processed through a circular data buffer that operates in a round robin fashion at a transmission node. The coding and forward error correction processes allow for continued operation in spite of possible signal fades due to atmospheric turbulence or other causes. At a receive node, incoming data is also saved in a circular buffer. A re-acknowledgment list is maintained at the receive node for tracking recently received and decoded data. This allows for a new acknowledgment to be sent in the event that a previously sent acknowledgment failed to reach the transmission node.

Abstract: Disclosed herein is a method and apparatus for providing traffic information of public transportation means, such as a bus, and utilizing the provided information. A method of encoding public traffic information according to the present invention creates an identifier of bus information system, an ID of bus route, and information on all of bus stops pertaining to the bus route. The created information is organized to status information that is in turn incorporated into a transfer message. A sequence of transfer messages, each being constructed as described above, is wirelessly transmitted.

Abstract: Various techniques are disclosed for improved reliability of wireless communications using packet combination-based error correction. For example, a method includes receiving a first message transmitted wirelessly, where the first message contains a first copy of a data packet and has at least one error. The method also includes receiving a second message transmitted wirelessly, where the second message contains a second copy of the data packet and has at least one error. The method further includes identifying a set of bit positions based on where the first and second copies of the data packet differ and modifying the set of bit positions to produce a modified set of bit positions. In addition, the method includes modifying one or more bit values in the modified set of bit positions to produce at least one modified copy of the data packet and determining if the at least one modified copy of the data packet is error-free.

Abstract: A data storage device may include an interface that is arranged and configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller may be arranged and configured to receive a read metadata command for a specified one of the memory devices from the host using the interface, read metadata from the specified memory device and communicate the metadata to the host using the interface.

Abstract: A digital broadcast transmitting/receiving system and a method for processing data are disclosed. The method for processing data may enhance the receiving performance of the receiving system by performing additional coding and multiplexing processes on the traffic information data and transmitting the processed data. Thus, robustness is provided to the traffic information data, thereby enabling the data to respond strongly against the channel environment which is always under constant and vast change.

Abstract: A method to provide an alert notification and a reconcile action to a client computing system, the alert notification being responsive to an error condition in a target computing system, and the reconcile action being responsive to the alert notification, wherein the method supplies a client computing system and a target computing system, wherein the target computing system is in communication with the client computing system. The method further forms an alert notification responsive to an error condition detected in the target computing system, and generates a reconcile action responsive to the alert notification. The method provides the alert notification and the reconcile action to the client computing system. The client computing system returns a selected reconcile action, which is implemented by the target computing system, wherein that implementing step is performed without logging into said target computing system.

Abstract: A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.

Abstract: The present techniques provide systems and methods for decoding an optical data signal returned from an optical disc to retrieve source information. The decoding method is based on a 16 state trellis diagram, and may decode an optical data signal encoded through a modulation code where the input-to-output relationship is not convolutional, such as the 17 Parity Preserve/Prohibit (17pp) modulation code. A trellis diagram may enable non-convolutional trellis-modulated data to be more efficiently decoded. Further, the 16 state trellis diagram of the present techniques provides a unique path for each input-to-output bit pair, such that no information about input bits may be lost on parallel paths in a trellis diagram.

Abstract: An information processing device includes: a receiving operation for receiving, from a transmission device, content and first verification data corresponding to divided content obtained by dividing the content; a detecting operation for detecting an error of the divided content based on second verification data to be calculated based on the divided content and the first verification data received in the receiving operation; and an obtaining operation for obtaining other divided content corresponding to the divided content having the error detected in the detecting operation from another information processing device different from the transmission device, when the error of the divided content is detected in the detecting operation.

Abstract: An error detector/corrector includes an ECC cache unit configured to store an error bit address which represents an error location by associating the error bit address with an error page address and a coefficient ? of an error location polynomial; a comparison unit configured to check for a match by comparing new values with stored values, where the new values are an error page address detected by a syndrome calculation unit and a coefficient ? of the error location polynomial calculated by a polynomial calculation unit while the stored values are an error page address and a coefficient ? of the error location polynomial stored in the ECC cache unit; and a first error localization unit configured to identify a location of the error bit address stored in the ECC cache unit as the error location when the comparison unit determines that the compared values match.

Abstract: Methods, systems and computer program products for copy protecting content data to be stored on storage media are disclosed. At least one location in the content data is selected for insertion of a predetermined data sequence, which, upon re-trieval from the storage media by a data retrieval apparatus, is capable of rendering the data retrieval apparatus incapable of correctly retrieving the content data from the storage media. The predetermined data sequence is inserted at the at least one selected location in the content data and the content data and predetermined data sequence are processed such that the data retrieval apparatus is capable of correctly retrieving the content data from original storage media the content data is stored on and is incapable of correctly retrieving the content data from a copy of the original storage media.

Abstract: An image processing apparatus which, when an error occurs during communication with a host computer, gives a higher priority to reconnection to the host computer connected at the time of occurrence of the error than to connection to another host computer. A CPU of the apparatus accepts processing requests from the host computers. When accepting a processing request from a host computer, the CPU causes the apparatus to connect to the host computer. If occurrence of an error is detected during communication with the host computer, the CPU controls the connection such that reconnection to the host computer connected at the time of occurrence of the error is given priority over connection to another host computer.

Abstract: A generation unit in a data protection circuit acquires input data from one position on a path that outputs the input data as output data, and generates a second error detecting code. A check unit acquires the input data from another position on the path that is closer to an output side than the acquiring position in the generation unit, and checks the input data using a first error detecting code. Further, a connection unit connects the acquiring position in the generation unit and the acquiring position in the check unit so that the input data is acquired by the check unit subsequent to acquirement by the generation unit.

Abstract: Arbitrarily high data transmission rates may be achieved by the use of N-dimensional, LDPC-coded modulation. N orthonormal basis functions are employed using coherent reception, resulting in a proportional increase in transmission rate with only a modest increase in bit-error ratio.

Abstract: A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.

Abstract: In a wireless network (100) with HSDPA-enabled user equipment devices (130), the base transceiver station (120) transmits to each HSDPA-enabled UE information regarding allocation of HSDPA codes and associated modulation techniques for other HSDPA-enabled UEs. Using this additional control information, each UE configures decision feedback filter of its equalizer to reduce inter-user interference. The additional control information may be transmitted in a packet (300) that includes a CRC portion (310) with the packet's CRC masked by a common ID, which is known to the HSDPA-enabled UEs. To reduce the number of bits needed to transmit the additional control information, the HSDPA codes used with a particular modulation technique are allocated consecutively. For each modulation technique, only the beginning code and the total number of codes need be known to the UEs. The number of codes used with each modulation technique may be allowed to change once in several TTIs.

Abstract: Systems and methods of deferred error recovery in a digital home communications terminal are disclosed. One such method comprises: receiving packets at a delivery rate; filling a decoder buffer from frames in the received packets while bypassing an error recovery buffer; after the level of the decoder buffer reaches an underrun threshold, decoding from the frames in the decoder buffer; and after beginning to decode, filling the error recovery buffer from the received packets and filling the decoder buffer from frames output from the error recovery buffer.

Abstract: A method for generating a virtual volume (VV) in a storage system architecture. The architecture comprises a host and one or more disk array subsystems. Each subsystem comprises a storage controller. One or more of the subsystems comprises a physical storage device (PSD) array. The method comprises the following steps: mapping the PSD array into a plurality of media extents (MEs), each of the MEs comprises a plurality of sections; providing a virtual pool (VP) to implement a section cross-referencing function, wherein a section index (SI) of each of the sections contained in the VP is defined by the VP to cross-reference VP sections to physical ME locations; providing a conversion method or procedure or function for mapping VP capacity into to a VV; and presenting the VV to the host. A storage subsystem and a storage system architecture performing the method are also provided.

Abstract: Runtime checks on a program may be used to determine whether a pointer points to a legitimate target before the pointer is dereferenced. Legitimate addresses, such as address-taken local variables (ATLVs), global variables, heap locations, functions, etc., are tracked, so that the legitimate targets of pointers are known. The program may be transformed so that, prior to dereferencing a pointer, the pointer is checked to ensure that it points to a legitimate address. If the pointer points to a legitimate address, then the dereferencing may proceed. Otherwise, an error routine may be invoked. One example way to keep track of legitimate addresses is to group address-taken variables together within a specific range or ranges of memory addresses, and to check that a pointer has a value within that range prior to dereferencing the pointer. However, addresses may be tracked in other ways.

Abstract: To update firmware on a consumer device intelligently, two or more application images are stored as firmware on the consumer device. If the primary application image is corrupt, the back-up application image is executed on the consumer device. The back-up application image can be updated based on the primary application image. User configuration files can be preserved during the update of an application image, or they can be overwritten. This firmware updating scheme can be advantageously implemented in a personal media broadcasting system.

Abstract: An apparatus and method for multimedia file streaming are provided. In a method for multimedia file streaming in a receiving portable terminal, the method includes determining meta data included in a received packet, generating new meta data having a circular-type media data offset on the basis of the meta data, storing media data included in the packet received in a circular manner according to the media data offset included in the new meta data, and loading the media data stored according to the media data offset included in the new meta data.

Abstract: A data protection method is provided. The method includes receiving data; generating compressed data based on the data; determining a degree of compressibility based on the compressed data; determining an amount of free space based on the degree of compressibility; and setting one or more error bits based on the amount of free space.

Abstract: The present disclosure provides a data storage system including a data memory device and controller having interface error detection and handling logic. In one example, a solid-state data memory device is provided and includes a semiconductor package. A memory array is provided in the semiconductor package and an interface is provided that is communicatively couplable to a device bus for receiving data to be stored to the memory array. An error detection component is provided in the semiconductor package and is associated with the interface of the solid-state data memory device. The error detection component is configured to detect errors occurring on data received at the interface prior to the data being stored to the memory array.

Abstract: The present invention provides a method for restoring a client operating system-based system, a virtual machine manager and a virtual machine manager system using the same. The method comprises steps of: receiving a restoration instruction for the client operating system and suspending running the client operating system after receiving the restoration instruction, the restoration instruction including a preset restoration point; determining a first memory snapshot and a first incremental file corresponding to the restoration point, the first memory snapshot being a memory snapshot for the client operating system, which is created when setting the restoration point, and the first incremental file being an incremental file, which is mapped as the first hard disk when setting the restoration point; re-mapping the first incremental file as the first hard disk; and performing a snapshot recovery based on the first memory snapshot. With the present invention, system restoration may be performed rapidly.