Abstract: Disclosed is a fullerene derivative having a formula of F-Cy, wherein F is an open-cage fullerene, and Cy is a chalcogenyl group. The fullerene derivative can be applied to hydrogen storage material and an optoelectronic device such as an organic light emitting diode (OLED), a solar cell, or an organic thin film transistor (TFT).

Abstract: A gate driving circuit includes a plurality of stages outputting gate signals to a plurality of gate lines. Each of the stages includes a circuit transistor, a capacitor part, a first connecting electrode and a second connecting electrode. The circuit transistor outputs the gate signal to an output electrode in response to a control signal inputted to a control electrode. The capacitor part is disposed adjacent to the circuit transistor, and includes a first electrode, a second electrode disposed over the first electrode, a third electrode disposed over the second electrode and a fourth electrode disposed over the third electrode. The first connecting electrode electrically connects the control electrode to the first and third electrodes. The second connecting electrode electrically connects the output electrode to the second and fourth electrodes.

Abstract: Provided are an electronic device and methods of fabricating the same, the electronic device include a device-substrate, a stacked structure, and an electrode. The stacked structure includes a graphene thin film between a first insulator and a second insulator. The electrode is disposed over the stacked structure.

Abstract: In an inverted staggered thin film transistor, a microcrystalline silicon film and a pair of silicon carbide films are provided between a gate insulating film and wirings serving as a source wiring and a drain wiring. The microcrystalline silicon film is formed on the gate insulating film side and the pair of silicon carbide films are formed on the wiring side. In such a manner, a semiconductor device having favorable electric characteristics can be manufactured with high productivity.

Abstract: In a display substrate and a method of manufacturing the display substrate, the display substrate includes a data line, a channel pattern, an insulating pattern and a pixel electrode. The data line extends in a direction on a base substrate. The channel pattern is disposed in a separate region between an input electrode connected to the data line and an output electrode spaced apart from the input electrode. The channel pattern makes contact with the input electrode and the output electrode on the input and output electrodes. The insulating pattern is spaced apart from the channel pattern on the base substrate and includes a contact hole exposing the output electrode. The pixel electrode is formed on the insulating pattern to make contact with the output electrode through the contact hole. Thus, a damage of the oxide semiconductor layer may be minimized and a manufacturing process may be simplified.

Abstract: A transistor includes: a control electrode; an active layer facing the control electrode; a first electrode and a second electrode electrically connected to the active layer; and an insulating layer provided between the control electrode and the active layer, the insulating layer containing diallyl isophthalate resin.

Abstract: A break on a video signal line is prevented during patterning on the video signal line. A video signal line, a drain electrode, and a source electrode are simultaneously formed in the same layer. The video signal line includes three layers: a base layer, an AlSi layer, and a cap layer. Conventionally, an alloy having a high etching rate is formed at the boundary between the AlSi layer and the cap layer, causing breakage during patterning on the video signal line. According to the present invention, in the formation of the video signal line, the AlSi layer is formed by sputtering, a TFT is exposed to the atmosphere to form an Al oxide layer on the surface of the AlSi layer, and then the cap layer is formed by sputtering. Thus, the formation of an alloy having a high etching rate on a part of the AlSi layer is prevented, precluding the occurrence of a break on the video signal line.

Abstract: A thin-film transistor includes: an organic semiconductor layer; and a source electrode and a drain electrode spaced apart from each other and disposed to respectively overlap the organic semiconductor layer. The organic semiconductor layer INCLUDES: a lower organic semiconductor layer; and an upper organic semiconductor layer formed on the lower organic semiconductor layer and having solubility and conductivity higher than the lower organic semiconductor layer. The lower organic semiconductor layer extends from an area overlapping the source electrode to an area overlapping the drain electrode, while the upper organic semiconductor layer is disposed in each of the area overlapping the source electrode and the area overlapping the drain electrode so that the respective upper organic semiconductor layers are spaced apart from each other.

Abstract: A method is provided for fabricating a thin film transistor. A plurality of layers is deposited on a substrate. The plurality of layers includes a conductive gate contact layer, a gate insulator layer, an undoped channel layer, an etch-stop layer, and a conductive contact layer. The etch-stop layer is positioned between the conductive contact layer and the undoped channel layer. A portion of the conductive contact layer is selectively removed while removal of a portion of the undoped channel layer is prevented by the etch-stop layer during the selective removal. A portion of the etch-stop layer is selectively removed and an exposed portion of the etch-stop layer is converted from a conductor to an insulator by oxidizing the exposed portion of the etch-stop layer in air. A portion of remaining layers of the plurality of layers is selectively removed to form the thin film transistor.

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract: A semiconductor device in which release of oxygen from side surfaces of an oxide semiconductor film including c-axis aligned crystal parts can be prevented is provided. The semiconductor device includes a first oxide semiconductor film, a second oxide semiconductor film including c-axis aligned crystal parts, and an oxide film including c-axis aligned crystal parts. In the semiconductor device, the first oxide semiconductor film, the second oxide semiconductor film, and the oxide film are each formed using a IGZO film, where the second oxide semiconductor film has a higher indium content than the first oxide semiconductor film, the first oxide semiconductor film has a higher indium content than the oxide film, the oxide film has a higher gallium content than the first oxide semiconductor film, and the first oxide semiconductor film has a higher gallium content than the second oxide semiconductor film.

Abstract: A semiconductor device includes TFTs designed in accordance with characteristics of circuits. In a first structure of the invention, the TFT is formed by using a crystalline silicon film made of a unique crystal structure body. The crystal structure body has a structure in which rod-like or flattened rod-like crystals grow in a direction parallel to each other. In a second structure of the invention, growth distances of lateral growth regions are made different from each other in accordance with channel lengths, of the TFTs. By this, characteristics of TFTs formed in one lateral growth region can be made as uniform as possible.

Abstract: Organic polymeric multi-metallic alkoxide or aryloxide composites are used as dielectric materials in various devices with improved properties such as improved mobility. These composites comprise an organic polymer comprising metal coordination sites, and multi-metallic alkoxide or aryloxide molecules that are coordinated with the organic polymer, the multi-metallic alkoxide or aryloxide molecules being represented by: (M)n(OR)x wherein at least one M is a metal selected from Group 2 of the Periodic Table and at least one other M is a metal selected from any of Groups 3 to 12 and Rows 4 and 5 of the Periodic Table, n is an integer of at least 2, R represents the same or different alkyl or aryl groups, and x is an integer of at least 2.

Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

Abstract: The organic memory device is a double-gate transistor that successively comprises a first gate electrode, a first gate dielectric, an organic semi-conductor material, a second gate dielectric and a second gate electrode. Source and drain electrodes are arranged in the organic semiconductor material and define an inter-electrode surface. A trapping area is arranged between the organic semiconductor material and one of the gate electrodes and is in electric contact with one of the gate electrodes or the organic semi-conductor material. The trapping area is at least facing the inter-electrode surface.

Abstract: A pixel structure including a first scan line, a second scan line, a data line and a power line substantially perpendicular to the first scan line and the second scan line, a reference signal line and an emission signal line substantially parallel with the first scan line and the second scan line, a common thin film transistor (C-TFT), a first pixel unit, and a second pixel unit is provided. The common thin film transistor has a common gate electrode, a common source electrode and a common drain electrode. The common gate electrode is electrically connected to the first scan line, the common drain electrode is electrically connected to the reference signal line. The first and the second pixel units respectively have a first TFT, a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a capacitor, and an emission device.

Abstract: A flat panel display including a semiconductor circuit, and a method of manufacturing the semiconductor circuit are disclosed. In one embodiment, the semiconductor circuit includes i) a substrate, ii) a semiconductor layer and a first capacitor electrode formed on the substrate, the first capacitor electrode being doped to be conductive, iii) an insulating layer covering the semiconductor layer and the first capacitor electrode, iv) a gate electrode disposed on the insulating layer and corresponding to a portion of the semiconductor layer, and v) a second capacitor electrode disposed on the insulating layer and corresponding to the first capacitor electrode, wherein the gate electrode is thicker than the second capacitor electrode.

Abstract: In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a drain electrode is formed in contact with the oxide semiconductor film, and then, heat treatment is performed. Through the heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, whereby the oxide semiconductor film is highly purified. By providing the metal oxide film, generation of a parasitic channel on the back channel side of the oxide semiconductor film in the transistor can be prevented.

Abstract: A display device and a fabrication method thereof are provided. The display device includes a first metal layer disposed on a display area and a peripheral area. An insulating layer covers the first metal layer. A patterned semiconductor layer is disposed on the insulating layer at the display area. A second metal layer is disposed on the patterned semiconductor layer and the insulating layer at the peripheral area. A transparent conductive layer directly covers the second metal layer. A protective layer completely covers the second metal layer, the patterned semiconductor layer and the transparent conductive layer. The protective layer includes a first portion, a second portion and a through hole, wherein the first portion has a height which is higher than a height of the second portion.

Abstract: A display panel (50a) includes a TFT substrate (20a) in which a plurality of TFTs (5a) are provided, a counter substrate (30a) provided to face the TFT substrate (20a), and a display medium layer (40) provided between the TFT substrate (20a) and the counter substrate (30a), a plurality of pixels being provided so that each of the plurality of pixels is associated with a corresponding one of the TFTs (5a), wherein an oxide semiconductor layer (13) is provided in each of the TFTs (5a) as a channel, and an ultraviolet light absorbing layer (22) having a light transmitting property is provided in each of the pixels (P) so as to overlap the oxide semiconductor layer (13).

Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.

Abstract: Objects are to provide a semiconductor device for high power application in which a novel semiconductor material having high productivity is used and to provide a semiconductor device having a novel structure in which a novel semiconductor material is used. The present invention is a vertical transistor and a vertical diode each of which has a stacked body of an oxide semiconductor in which a first oxide semiconductor film having crystallinity and a second oxide semiconductor film having crystallinity are stacked. An impurity serving as an electron donor (donor) which is contained in the stacked body of an oxide semiconductor is removed in a step of crystal growth; therefore, the stacked body of an oxide semiconductor is highly purified and is an intrinsic semiconductor or a substantially intrinsic semiconductor whose carrier density is low. The stacked body of an oxide semiconductor has a wider band gap than a silicon semiconductor.

Abstract: The time taken to write a signal to a pixel is shortened in a display device. Further, a signal is written at high speed even when high voltage is applied. The display device includes a pixel including a transistor and a liquid crystal element electrically connected to a source or a drain of the transistor. The transistor includes an intrinsic or substantially intrinsic oxide semiconductor as a semiconductor material and has an off-state current of 1×10?17 A/?m or less. The pixel does not include a capacitor. Since it is not necessary to provide a capacitor, the time taken to write a signal can be shortened.

Abstract: A thin-film transistor having a protection layer for a planarization layer. The protection layer prevents reduction of the planarization layer during an ashing process, thereby preventing the formation of a steeply tapered via hole through the planarization layer. In this manner, the via hole may be coated with a conductive element that may serve as a conductive path between a common electrode and the drain of the transistor.

Abstract: A display apparatus includes a first substrate including pixels, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. Each of the pixels includes a thin film transistor disposed on a first insulating substrate, a first protective layer that covers the thin film transistor and includes a SiOC layer, a first electrode disposed on the first protective layer, a second protective layer that covers the first electrode, and a second electrode disposed on the second protective layer.

Abstract: A stem wiring (13a) having a broad line width is formed above branch wirings (13b) having a narrow line width. In a region where the stem wiring (13a) is connected to the branch wiring (13b), the stem wiring (13a) overlaps with the branch wiring (13b) via a gate insulating film when seen in a plan view, a contact hole is provided in the gate insulating film so as to uncover the branch wiring (13b), and the stem wiring (13a) is electrically connected to the branch wiring (13b) via a connecting conductor formed in the contact hole. Consequently, a TFT array substrate can be achieved, in which a disconnection failure or an abnormal line width is reduced without enlarging the dimension of a driving circuit region.

Abstract: A method of connecting to a first metal layer in a semiconductor flow process. Disclosed embodiments connect to the first metal layer by etching a first portion of a viahole through an etch stop layer and a gate insulation layer to reach a first metal layer, depositing a second metal layer such that the second metal layer contacts the first metal layer within the viahole, and etching a second portion of the viahole through a first passivation layer and an organic layer to reach the second metal layer.

Abstract: An active device array substrate includes a flexible substrate, a gate electrode, a dielectric layer, a channel layer, a source electrode, a drain electrode, and a pixel electrode. The flexible substrate has at least one transistor region and at least one transparent region adjacent to each other. The gate electrode is disposed on the transistor region of the flexible substrate. The dielectric layer covers the flexible substrate and the gate electrode. A portion of the dielectric layer disposed on the gate electrode has a first thickness. Another portion of the dielectric layer disposed on the transparent region of the flexible substrate has a second thickness. The second thickness is less than the first thickness. The channel layer is disposed above the gate electrode. The source electrode and the drain electrode are disposed on opposite sides of the channel layer and are electrically connected to the channel layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract: Nano-sized materials and/or polysilicon are formed using heat generated from a micro-heater, the micro-heater may include a substrate, a heating element unit formed on the substrate, and a support structure formed between the substrate and the heating element unit. Two or more of the heating element units may be connected in series.

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Abstract: A field effect transistor device includes a bulk semiconductor substrate, a fin arranged on the bulk semiconductor substrate, the fin including a source region, a drain region, and a channel region, a first shallow trench isolation (STI) region arranged on a portion of the bulk semiconductor substrate adjacent to the fin, a first recessed region partially defined by the first STI region and the channel region of the fin, and a gate stack arranged over the channel region of the fin, wherein a portion of the gate stack is partially disposed in the first recessed region.

Abstract: A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A semiconductor layer has a third pattern. A source/drain includes a second electrically conductive layer stack.

Abstract: A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A third inorganic thin film dielectric layer has a third pattern. A semiconductor layer is in contact with and has the same pattern as the third inorganic thin film dielectric material layer. A source/drain includes a second electrically conductive layer stack.

Abstract: A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer has a second pattern. A semiconductor layer is in contact with and has the same pattern as the second inorganic thin film dielectric material layer. A source/drain includes a second electrically conductive layer stack.

Abstract: An n-channel transistor or a p-channel transistor provided with a second gate electrode for controlling a threshold voltage in addition to a normal gate electrode is used for a complementary logic circuit. In addition, an insulated gate field-effect transistor with an extremely low off-state current is used as a switching element to control the potential of the second gate electrode. A channel formation region of the transistor which functions as a switching element includes a semiconductor material whose band gap is wider than that of a silicon semiconductor and whose intrinsic carrier density is lower than that of silicon.

Abstract: A display apparatus includes a first substrate including a plurality of pixels, a first electrode arranged on the first substrate, a second substrate facing the first substrate, and a second electrode arranged on the second substrate and spaced apart from the first electrode, the second electrode to form an electric field in cooperation with the first electrode. At least one of the first and second electrodes includes a transparent conductive nanomaterial having a transmittance of no less than 73% to no more than 100% and a sheet resistance of 0 ohms to 100 ohms.

Abstract: A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ?r/d is greater than or equal to 0.08 (nm?1) and less than or equal to 7.9 (nm?1) when the relative permittivity of a material used for the gate insulating layer is ?r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 ?m.

Abstract: An organic light-emitting display device is manufactured via a simple process and has an improved aperture ratio. The organic light-emitting display device comprising: a substrate; an auxiliary electrode formed on the substrate; a thin film transistor (TFT) formed on the auxiliary electrode, the TFT comprising an active layer, a gate electrode, a source electrode and a drain electrode; an organic electroluminescent (EL) device electrically connected to the TFT and formed by sequentially stacking a pixel electrode formed on the same layer by using the same material as portions of the source and drain electrodes, an intermediate layer comprising an organic light emission layer (EML), and an opposite electrode disposed to face the pixel electrode; and a contact electrode formed on the same layer by a predetermined distance by using the same material as the source and drain electrodes, and electrically connecting the auxiliary electrode and the opposite electrode.

Abstract: An object is to provide a semiconductor device using an oxide semiconductor having stable electric characteristics and high reliability. A transistor including the oxide semiconductor film in which a top surface portion of the oxide semiconductor film is provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film and functioning as a channel protective film is provided. In addition, the oxide semiconductor film used for an active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by heat treatment in which impurities such as hydrogen, moisture, a hydroxyl group, or a hydride are removed from the oxide semiconductor and oxygen which is a major constituent of the oxide semiconductor and is reduced concurrently with a step of removing impurities is supplied.

Abstract: In a TFT that adopts an oxide semiconductor as an active layer and has a resistance layer interposed between the active layer and one of a source and drain electrode, while Vth close to 0 V and a small off current are sustained, an on-current is increased. In a thin-film transistor including a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a drain electrode, the semiconductor layer that links the source electrode and drain electrode is made of a metal oxide. The semiconductor layer includes three regions of first, second, and third regions. The first region is connected with the source electrode, the third region is connected with the drain electrode, and the second region is connected between the first region and third region. The resistivities of the three regions have the relationship of the first region>the second region>the third region.

Abstract: A touch panel display and method for manufacturing the same are disclosed. The touch panel display includes a first substrate, a second substrate, a touch-sensing member, and a liquid crystal layer. The first substrate has a first surface and a second surface thereon. The second substrate has an element array and is disposed on the second surface of the first substrate. The touch-sensing member locates on the first surface of the first substrate. Furthermore, the touch-sensing member includes a conductive layer, a patterned electrode layer, and a protective layer. The patterned electrode layer is correspondingly located on the periphery of the first substrate. The protective layer covers the conductive layer, and the patterned electrode layer. The conductive layer locates between the protective layer and the first substrate. In addition, the liquid crystal layer is disposed between the first and the second substrate.

Abstract: There is provided a thin-film transistor forming substrate in which at least one of a source electrode, a drain electrode, and a gate electrode, which are constituent elements of a thin film transistor, or a first electrode is included on a face of a substrate main body that is located on any one side in a thickness direction. An embedded wiring that is connected to one of the source electrode, the drain electrode, the gate electrode, and the first electrode is buried inside the substrate main body.

Abstract: Disclosed is a thin film transistor wherein an ON current is increased and a leak current is reduced. The channel layer 60 of the TFT 10 is formed of a crystalline silicon, and the lower surface of one end of the channel layer 60 is electrically connected to the surface of an n+ silicon layer 40a, and the lower surface of the other end is electrically connected to the surface of an n+ silicon layer 40b. Furthermore, the side surface of said end of the channel layer 60 is electrically connected to a source electrode 50a, and the side surface of the other end is electrically connected to a drain electrode 50b. Thus, a barrier that makes electrons, which act as carriers, not easily transferred is formed on the boundary between the source electrode 50a and the channel layer 60. As a result, the ON current that flows when the TFT 10 is in the ON state can be increased, and the leak current that flows when the TFT is in the OFF state can be reduced.

Abstract: An organic light-emitting display device comprises: a lower substrate; an upper substrate facing the lower substrate; and a spacer formed in a sealed space between the lower substrate and the upper substrate and dividing the space into two or more sections; wherein air holes are formed in the spacer and allow air to flow between the sections of the space.

Abstract: A display device includes a first substrate and a second substrate facing each other, a thin film transistor on the first substrate, a color filter and a black matrix on the first substrate, a column spacer on the first substrate and electrically connected to the thin film transistor, a pixel electrode on one surface of the second substrate, a common electrode on the pixel electrode on the one surface of the second substrate, and a transparent electrode on the other surface of the second substrate. The column spacer is electrically connected to the pixel electrode.

Abstract: The present invention provides a manufacturing method for array substrate, including: forming a first conductive layer, a first isolator layer, a second conductive layer and a second isolator layer on a substrate from bottom up, the first conductive layer for forming electrically connected scan line and control terminal of switch transistor, performing dry etch on the second isolator layer to form via hole, and forming a third conductive layer on the second isolator layer for forming data line. The present invention also provides an arrays substrate and a liquid crystal display device. As such, the present invention can reduce the possibility of electrostatic explosion during array substrate manufacturing process and improve the yield rate of array substrate.

Abstract: A semiconductor display device is formed including an interlayer insulating. Specifically, a TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.

Abstract: Pixel control structure for use in a backplane for an electronic display, including a transistor that has a gate, a source, a drain, and an organic semiconductor element. The pixel control structure is formed by a first patterned conductive layer portion, a second patterned conductive layer portion, a dielectric layer portion, and an organic patterned semiconductive layer portion. The dielectric layer portion comprises an overlap region defined by overlap of the second conductive layer portion over the first conductive layer portion. The overlap region defines an overlap boundary, defined by an edge portion of the first patterned conductive layer portion and an edge portion of the second patterned conductive layer portion. The patterned semiconductive layer portion extends over the overlap region and away from the overlap region so as to extend from both first and second edge portions.

Abstract: This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and configured to receive first, second, and third control signals, respectively. Dielectric layers insulate the gates from the semiconducting layer and from one another. In a first mode, the first, second, and third gates are configured such that charge is stored in a potential well in a region of the semiconducting layer adjacent the second gate. In a second mode, the first, second and third gate electrodes are configured such that the stored charge is transferred through the region of the semiconducting layer adjacent the third gate electrode and through the source to a load.