With Decomposition Of A Precursor (except Impurity Or Dopant Precursor) Composed Of Diverse Atoms (e.g., Cvd) Patents (Class 117/88)
  • Patent number: 8808452
    Abstract: A method for using a silicon film formation apparatus includes performing a pre-coating process to cover a reaction tube with a silicon coating film, an etching process to etch natural oxide films on product target objects, a silicon film formation process to form a silicon product film on the product target objects, and a cleaning process to etch silicon films on the reaction tube, in this order. The pre-coating process includes supplying a silicon source gas into the reaction tube from a first supply port having a lowermost opening at a first position below the process field, while exhausting gas upward from inside the reaction tube. The etching process includes supplying an etching gas into the reaction tube from a second supply port having a lowermost opening between the process field and the first position, while exhausting gas upward from inside the reaction tube by the exhaust system.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: August 19, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Naotaka Noro, Takahiro Miyahara
  • Patent number: 8795431
    Abstract: A gallium nitride layer is produced using a seed crystal substrate by flux method. The seed crystal substrate 8A includes a supporting body 1, a plurality of seed crystal layers 4A each comprising gallium nitride single crystal and separated from one another, a low temperature buffer layer 2 provided between the seed crystal layers 4A and the supporting body and made of a nitride of a group III metal element, and an exposed layer 3 exposed to spaces between the adjacent seed crystal layers 4A and made of aluminum nitride single crystal or aluminum gallium nitride single crystal. The gallium nitride layer is grown on the seed crystal layers by flux method.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: August 5, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Katsuhiro Imai, Makota Iwai, Takanao Shimodaira, Masahiro Sakai, Shuhei Higashihara, Takayuki Hirao
  • Patent number: 8790462
    Abstract: A nanoengineered structure comprising an array of more than about 1000 nanowhiskers on a substrate in a predetermined spatial configuration, for use for example as a photonic band gap array, wherein each nanowhisker is sited within a distance from a predetermined site not greater than about 20% of its distance from its nearest neighbour. To produce the array, an array of masses of a catalytic material are positioned on the surface, heat is applied and materials in gaseous form are introduced such as to create a catalytic seed particle from each mass, and to grow, from the catalytic seed particle, epitaxially, a nanowhisker of a predetermined material, and wherein each mass upon melting, retains approximately the same interface with the substrate surface such that forces causing the mass to migrate across said surface are less than a holding force across a wetted interface on the substrate surface.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: July 29, 2014
    Assignee: Qunano AB
    Inventors: Lars Ivar Samuelson, Bjorn Jonas Ohlsson, Thomas M. I. Martensson
  • Patent number: 8790463
    Abstract: Disclosed is a hot wall type substrate processing apparatus, including a processing chamber which is to accommodate at least one product substrate therein; a heating member which is disposed outside of the processing chamber and which is to heat the product substrate; a processing gas supply system connected to the processing chamber; and an exhaust system, wherein with a member from which a Si film is exposed being disposed such as to be opposed to a surface on which selective growth is to be effected of the product substrate, an epitaxial film including Si is allowed to selectively grow on a Si surface of the product substrate.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: July 29, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Atsushi Moriya, Yasuhiro Inokuchi, Yasuo Kunii
  • Publication number: 20140196660
    Abstract: A nitride semiconductor crystal producing method, includes growing a nitride semiconductor crystal over a seed crystal substrate, while applying an etching action to an outer end of the seed crystal substrate during the growing of the nitride semiconductor crystal.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 17, 2014
    Applicant: Hitachi Metals, Ltd.
    Inventors: Hajime FUJIKURA, Taichiroo KONNO, Yuichi OSHIMA
  • Patent number: 8778078
    Abstract: A process for producing a doped III-N bulk crystal, wherein III denotes at least one element of the main group III of the periodic system, selected from Al, Ga and In, wherein the doped crystalline III-N layer or the doped III-N bulk crystal is deposited on a substrate or template in a reactor, and wherein the feeding of at least one dopant into the reactor is carried out in admixture with at least one group III material. In this manner, III-N bulk crystals and III-N single crystal substrates separated therefrom can be obtained with a very homogeneous distribution of dopants in the growth direction as well as in the growth plane perpendicular thereto, a very homogeneous distribution of charge carriers and/or of the specific electric resistivity in the growth direction as well as in the growth plane perpendicular thereto, and a very good crystal quality.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: July 15, 2014
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Ferdinand Scholz, Peter Brückner, Frank Habel, Gunnar Leibiger
  • Patent number: 8771416
    Abstract: A substrate processing apparatus comprises: a reaction chamber to process a substrate; a heating target object disposed in the reaction chamber to surround at least a region where the substrate is disposed, the heating target object having a cylindrical shape with a closed end; an insulator disposed between the reaction chamber and the heating target object to surround the heating target object, the insulator having a cylindrical shape with a closed end facing the closed end of the heating target object; an induction heating unit disposed outside the reaction chamber to surround at least the region where the substrate is disposed; a first gas supply system to supply at least a source gas into the reaction chamber; and a controller to control the first gas supply system so that the first gas supply system supplies at least the source gas into the reaction chamber for processing the substrate.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 8, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Shuhei Saido, Takatomo Yamaguchi, Kenji Shirako
  • Publication number: 20140174342
    Abstract: The present invention generally related to adding Indium precursors to deposition processes for thin films. Indium precursors are added in order to increase the growth rate per cycle of the deposition process. A plurality of deposition processes are disclosed herein which comprising a plurality of deposition cycles and providing an In-precursor pulse before at least one reactant pulse in at least one deposition cycle. The In-precursor can be added for increasing the average growth rate per cycle by at least 50% and in many examples above 500% compared to the growth rate of a similar deposition process without providing an In-precursor. Examples disclosed herein include the deposition of thin films comprising pnictides or chalcogenides, made by atomic layer deposition.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: ASM IP HOLDING B.V.
    Inventor: Viljami Pore
  • Patent number: 8747553
    Abstract: A method of growing a p-type thin film of ?-Ga2O3 includes preparing a substrate including a ?-Ga2O3 single crystal, and growing a p-type thin film of ?-Ga2O3 on the substrate. The p-type thin film is grown in a manner that Ga in the thin film is replaced by a p-type dopant selected from H, Li, Na, K, Rb, Cs, Fr, Be, Mg, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Tl, and Pb.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: June 10, 2014
    Assignee: Waseda University
    Inventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
  • Publication number: 20140150713
    Abstract: A method of manufacturing synthetic CVD diamond material, the method comprising: providing a microwave plasma reactor comprising: a plasma chamber; one or more substrates disposed in the plasma chamber providing a growth surface area over which the synthetic CVD diamond material is to be deposited in use; a microwave coupling configuration for feeding microwaves from a microwave generator into the plasma chamber; and a gas flow system for feeding process gases into the plasma chamber and removing them therefrom, injecting process gases into the plasma chamber; feeding microwaves from the microwave generator into the plasma chamber through the microwave coupling configuration to form a plasma above the growth surface area; and growing synthetic CVD diamond material over the growth surface area, wherein the process gases comprise at least one dopant in gaseous form, selected from a one or more of boron, silicon, sulphur, phosphorous, lithium and beryllium at a concentration equal to or greater than 0.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 5, 2014
    Applicant: ELEMENT SIX LIMITED
    Inventor: Helen Wilman
  • Publication number: 20140137793
    Abstract: A method of fabricating a wafer according to the embodiment comprises the steps of growing an wafer on a surface of the wafer in a growth temperature; and cooling the wafer after the wafer has been grown, wherein a stepwise cooling is performed when cooling the wafer.
    Type: Application
    Filed: June 22, 2012
    Publication date: May 22, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Seok Min Kang, Moo Seong Kim
  • Publication number: 20140138679
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Patent number: 8728236
    Abstract: Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: May 20, 2014
    Assignee: Cree, Inc.
    Inventors: Xueping Xu, Robert P. Vaudo
  • Patent number: 8728237
    Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8728622
    Abstract: Provided is a base substrate with which a Group-III nitride crystal having a large area and a large thickness can be grown while inhibiting crack generation. A single-crystal substrate for use in growing a Group-III nitride crystal thereon, which satisfies the following expression (1), wherein Z1 (?m) is an amount of warpage of physical shape in a growth surface of the single-crystal substrate and Z2 (?m) is an amount of warpage calculated from a radius of curvature of crystallographic-plane shape in a growth surface of the single-crystal substrate: ?40<Z2/Z1<?1: Expression (1).
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: May 20, 2014
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Kenji Fujito, Yasuhiro Uchiyama
  • Publication number: 20140117382
    Abstract: Disclosed is an epitaxial wafer including a substrate, and an epitaxial structure disposed on the substrate, wherein the epitaxial structure includes a first epitaxial layer, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed between the first epitaxial layer and the second epitaxial layer, the third epitaxial layer having a first doping concentration around a first boundary adjacent to the first epitaxial layer and a second doping concentration different from the first doping concentration around a second boundary adjacent to the second epitaxial layer.
    Type: Application
    Filed: October 31, 2013
    Publication date: May 1, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventor: Seok Min Kang
  • Patent number: 8709156
    Abstract: Epitaxially coated silicon wafers are produced by placing a wafer polished on its front side on a susceptor in an epitaxy reactor, first pretreating under a hydrogen atmosphere and in a second and a third step with addition of an etching medium to the hydrogen atmosphere, and subsequently providing an epitaxial layer, wherein during the first and second steps the hydrogen flow rate is 20-100 slm, during the second and third steps the flow rate of the etching medium is 0.5-1.5 slm, during the second step the average temperature in the reactor chamber is 950-1050° C., and the power of heating elements above and below the susceptor is regulated such that there is a temperature difference of 5-30° C. between a radially symmetrical region encompassing the central axis of and a part lying outside this region; and during the third step the hydrogen flow rate is reduced to 0.5-10 slm. In a second method, during the third pretreatment step the flow rate of the etching medium is increased to 1.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: April 29, 2014
    Assignee: Siltronic AG
    Inventor: Joerg Haberecht
  • Patent number: 8702865
    Abstract: Affords AlxGa1-xN crystal growth methods, as well as AlxGa1-xN crystal substrates, wherein bulk, low-dislocation-density crystals are obtained. The AlxGa1-xN crystal (0<x?1) growth method is a method of growing, by a vapor-phase technique, an AlxGa1-xN crystal (10), characterized by forming, in the growing of the crystal, at least one pit (10p) having a plurality of facets (12) on the major growth plane (11) of the AlxGa1-xN crystal (10), and growing the AlxGa1-xN crystal (10) with the at least one pit (10p) being present, to reduce dislocations in the AlxGa1-xN crystal (10).
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: April 22, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Michimasa Miyanaga, Naho Mizuhara, Hideaki Nakahata
  • Patent number: 8691011
    Abstract: The present invention relates to epitaxial growth of nanowires on a substrate. In particular the invention relates to growth of nanowires on an Si-substrate without using Au as a catalyst. In the method according to the invention an oxide template is provided on a passivated surface of the substrate. The oxide template defines a plurality of nucleation onset positions for subsequent nanowire growth. According to one embodiment a thin organic film is used to form the oxide template.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: April 8, 2014
    Assignee: QuNano AB
    Inventors: Lars Samuelson, Thomas Mårtensson, Werner Seifert, Anders Mikkelsen, Bernhard Mandl
  • Patent number: 8685549
    Abstract: A nanocomposite article that includes a single-crystal or single-crystal-like substrate and heteroepitaxial, phase-separated layer supported by a surface of the substrate and a method of making the same are described. The heteroepitaxial layer can include a continuous, non-magnetic, crystalline, matrix phase, and an ordered, magnetic magnetic phase disposed within the matrix phase. The ordered magnetic phase can include a plurality of self-assembled crystalline nanostructures of a magnetic material. The phase-separated layer and the single crystal substrate can be separated by a buffer layer. An electronic storage device that includes a read-write head and a nanocomposite article with a data storage density of 0.75 Tb/in2 is also described.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 1, 2014
    Assignee: UT-Battelle, LLC
    Inventors: Amit Goyal, Junsoo Shin
  • Publication number: 20140065368
    Abstract: This disclosure relates to methods that include depositing a first component and a second component to form a film including a plurality of nanostructures, and coating the nanostructures with a hydrophobic layer to render the film superhydrophobic. The first component and the second component can be immiscible and phase-separated during the depositing step. The first component and the second component can be independently selected from the group consisting of a metal oxide, a metal nitride, a metal oxynitride, a metal, and combinations thereof. The films can have a thickness greater than or equal to 5 nm; an average surface roughness (Ra) of from 90 to 120 nm, as measured on a 5 ?m×5 ?m area; a surface area of at least 20 m2/g; a contact angle with a drop of water of at least 120 degrees; and can maintain the contact angle when exposed to harsh conditions.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Applicant: UT-BATTELLE, LLC
    Inventors: Tolga AYTUG, Mariappan Parans PARANTHAMAN, John T. SIMPSON, Daniela Florentina BOGORIN
  • Patent number: 8663389
    Abstract: A method and apparatus for depositing III-V material is provided. The apparatus includes a reactor partially enclosed by a selectively permeable membrane 12. A means is provided for generating source vapors, such as a vapor-phase halide of a group III element (IUPAC group 13) within the reactor volume 10, and an additional means is also provided for introducing a vapor-phase hydride of a group V element (IUPAC group 15) into the volume 10. The reaction of the group III halide and the group V hydride on a temperature-controlled substrate 18 within the reactor volume 10 produces crystalline III-V material and hydrogen gas. The hydrogen is preferentially removed from the reactor through the selectively permeable membrane 12, thus avoiding pressure buildup and reaction imbalance. Other gases within the reactor are unable to pass through the selectively permeable membrane.
    Type: Grant
    Filed: May 21, 2011
    Date of Patent: March 4, 2014
    Inventor: Andrew Peter Clarke
  • Patent number: 8658118
    Abstract: An object of the present invention is to provide more inexpensive high purity crystalline silicon which can satisfy not only a quality required to a raw material of silicon for a solar cell but also a part of a quality required to silicon for an up-to-date semiconductor and a production process for the same and provide high purity silicon tetrachloride used for production of high purity crystalline silicon and a production process for the same. The high purity crystalline silicon of the present invention has a boron content of 0.015 ppmw or less and a zinc content of 50 to 1000 ppbw. The production process for high purity crystalline silicon according to the present invention is characterized by that a silicon tetrachloride gas and a zinc gas are supplied to a vertical reactor to react them at 800 to 1200° C.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: February 25, 2014
    Assignees: JNC Corporation, JX Nippon Mining & Metals Corporation, Toho Titanium Co., ltd.
    Inventors: Satoshi Hayashida, Wataru Kato
  • Publication number: 20140050652
    Abstract: The present invention provides graphene nuclei including monolayer single-crystalline graphene nuclei and a method of growing from them two-dimensional graphene dendrites, with aspect ratio of the main branches increasing with growth time, on catalytic metal surface using thermal chemical vapor deposition. By controlling the supply rates of the carbon etching gas and the carbon deposition species, it results in graphene branches being merged to form a two-dimensional monolayer single-crystalline graphene plate and further allows multiple graphene plates to merge and form a large-area continuous monolayer graphene plate.
    Type: Application
    Filed: January 30, 2013
    Publication date: February 20, 2014
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventor: Yon Hua TZENG
  • Patent number: 8652255
    Abstract: A method of: flowing a silicon source gas, a carbon source gas, and a carrier gas into a growth chamber under growth conditions to epitaxial grow silicon carbide on a wafer in the growth chamber; stopping or reducing the flow of the silicon source gas to interrupt the silicon carbide growth and maintaining the flow of the carrier gas while maintaining an elevated temperature in the growth chamber for a period of time; and resuming the flow of the silicon source gas to reinitiate silicon carbide growth. The wafer remains in the growth chamber throughout the method.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 18, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Robert E Stahlbush, Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, David Kurt Gaskill, Charles R. Eddy, Jr.
  • Patent number: 8652256
    Abstract: A manufacturing apparatus of polycrystalline silicon products polycrystalline silicon by depositing on a surface of a silicon seed rod by supplying raw-material gas to the heated silicon seed rod provided vertically in a reactor, includes: an electrode which holds the silicon seed rod and is made of carbon; an electrode holder which holds the electrode, and cooled by coolant medium flowing therein, wherein the electrode includes: a seed rod holding member which holds the silicon seed rod; a heat cap which is provided between the seed rod holding member and the electrode holder; and a cap protector having a ring-like plate shape, which covers an upper surface of the heat cap, and in which a through hole penetrating the lower-end portion of the seed rod holding member is formed.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: February 18, 2014
    Assignee: Mitsubishi Materials Corporation
    Inventors: Toshihide Endoh, Masayuki Tebakari, Toshiyuki Ishii, Masaaki Sakaguchi
  • Patent number: 8636845
    Abstract: Methods and compositions for depositing a metal containing film on a substrate are disclosed. A reactor and at least one substrate disposed in the reactor are provided. A metal containing precursor is provided and introduced into the reactor, which is maintained at a temperature of at least 100° C. A metal is deposited on to the substrate through a deposition process to form a thin film on the substrate.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: January 28, 2014
    Assignee: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Julien Gatineau, Kazutaka Yanagita, Shingo Okubo
  • Patent number: 8636843
    Abstract: Heterogeneous nanowires having a core-shell structure consisting of single-crystal apatite as the core and graphitic layers as the shell and a synthesis method thereof are provided. More specifically, provided is a method capable of producing large amounts of heterogeneous nanowires, composed of graphitic shells and apatite cores, in a reproducible manner, by preparing a substrate including an element corresponding to X of X6(YO4)3Z which is a chemical formula for apatite, adding to the substrate a gaseous source containing an element corresponding to Y of the chemical formula, adding thereto a gaseous carbon source, and allowing these reactants to react under optimized synthesis conditions using chemical vapor deposition (CVD), and to a method capable of freely controlling the structure and size of the heterogeneous nanowires and also to heterogeneous nanowires synthesized thereby.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: January 28, 2014
    Assignee: Korea Institute of Energy Research
    Inventors: Nam Jo Jeong, Jung Hoon Lee
  • Patent number: 8636844
    Abstract: A method of forming a template on a silicon substrate includes epitaxially growing a template of single crystal ternary rare earth oxide on a silicon substrate and epitaxially growing a single crystal semiconductor active layer on the template. The active layer has either a cubic or a hexagonal crystal structure. During the epitaxial growth of the template, a partial pressure of oxygen is selected and a ratio of metals included in the ternary rare earth oxide is selected to match crystal spacing and structure of the template at a lower interface to the substrate and to match crystal spacing and structure of the template at an upper interface to crystal spacing and structure of the semiconductor active layer. A high oxygen partial pressure during growth of the template produces a stabilized cubic crystal structure and a low oxygen partial pressure produces a predominant peak with a hexagonal crystal structure.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 28, 2014
    Assignee: Translucent, Inc.
    Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
  • Publication number: 20140020619
    Abstract: Disclosed are methods for growing Sn-containing semiconductor materials. In some embodiments, an example method includes providing a substrate in a chemical vapor deposition (CVD) reactor, and providing a semiconductor material precursor, a Sn precursor, and a carrier gas in the CVD reactor. The method further includes epitaxially growing a Sn-containing semiconductor material on the substrate, where the Sn precursor comprises tin tetrachloride (SnCl4). The semiconductor material precursor may be, for example, digermane, trigermane, higher-order germanium precursors, or a combination thereof. Alternatively, the semiconductor material precursor may be a silicon precursor.
    Type: Application
    Filed: March 29, 2012
    Publication date: January 23, 2014
    Inventors: Benjamin Vincent, Federica Gencarelli, Roger Loo, Matty Caymax
  • Patent number: 8632853
    Abstract: Methods for deposition of elemental metal films on surfaces using metal coordination complexes comprising nitrogen-containing ligands are provided. Also provided are nitrogen-containing ligands useful in the methods of the invention and metal coordination complexes comprising these ligands.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: January 21, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey W. Anthis, David Thompson
  • Publication number: 20140014029
    Abstract: A method of preventing microcavity formation in the bonding layer of a composite structure resulting from creep and thermal expansion due to high temperature exposure of the composite structure The method includes the steps of providing the thin film with a thickness of 5 micrometers or less; providing the bonding layer of oxide with a thickness that is equal to or greater than the thickness of the thin film with the bonding layer formed by low pressure chemical vapor deposition. The thin film or support substrate have a mean thermal expansion coefficient of 7×10?6 K?1 or more. The thin film, bonding layer and support substrate combine to reduce stress in and plastic deformation of the bonding layer during exposure to during exposure to high temperatures of more than approximately 900° C. to thus prevent microcavities from appearing in the bonding layer.
    Type: Application
    Filed: September 19, 2013
    Publication date: January 16, 2014
    Applicant: SOITEC
    Inventors: Bruce FAURE, Alexandra MARCOVECCHIO
  • Patent number: 8623139
    Abstract: An apparatus for producing polycrystalline silicon which heats a silicon seed rod in a reactor to which a raw material gas is supplied, and deposits polycrystalline silicon on the surface of the silicon seed rod, includes an electrode extending in a vertical direction to hold the silicon seed rod, an electrode holder having a cooling flow passage circulating a cooling medium formed therein, and inserted into a through-hole formed in a bottom plate of the reactor to hold the electrode, and an annular insulating material arranged between an inner peripheral surface of the through-hole and an outer peripheral surface of the electrode holder to electrically insulate the bottom plate and the electrode holder from each other.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: January 7, 2014
    Assignee: Mitsubishi Materials Corporation
    Inventors: Toshihide Endoh, Masayuki Tebakari, Toshiyuki Ishii, Masaaki Sakaguchi
  • Publication number: 20130333611
    Abstract: A lattice matching layer for use in a multilayer substrate structure comprises a lattice matching layer. The lattice matching layer includes a first chemical element and a second chemical element. Each of the first and second chemical elements has a hexagonal close-packed structure at room temperature that transforms to a body-centered cubic structure at an ?-? phase transition temperature higher than the room temperature. The hexagonal close-packed structure of the first chemical element has a first lattice parameter. The hexagonal close-packed structure of the second chemical element has a second lattice parameter. The second chemical element is miscible with the first chemical element to form an alloy with a hexagonal close-packed structure at the room temperature. A lattice constant of the alloy is approximately equal to a lattice constant of a member of group III-V compound semiconductors.
    Type: Application
    Filed: March 11, 2013
    Publication date: December 19, 2013
    Applicant: Tivra Corporation
    Inventors: Indranil De, Francisco Machuca
  • Patent number: 8608849
    Abstract: A method for making zinc oxide nano-structure, the method includes the following steps. Firstly, providing a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, providing a growing substrate and forming a metal layer thereon. Thirdly, depositing a catalyst layer on the metal layer. Fourthly, placing the growing substrate into the reacting room together with a quantity of zinc source material. Fifthly, introducing a oxygen-containing gas into the reacting room. Lastly, heating the reacting room to a temperature range of 500˜1100° C.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: December 17, 2013
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
  • Publication number: 20130319319
    Abstract: The present invention provides a susceptor for supporting a semiconductor substrate at the time of performing vapor-phase epitaxy of an epitaxial layer, wherein a pocket in which the semiconductor substrate is to be placed is formed on an upper surface of the susceptor, the pocket has a two-stage structure having an upper-stage-pocket portion for supporting an outer peripheral edge portion of the semiconductor substrate and a lower-stage-pocket portion that is formed on a central side of the pocket below the upper-stage-pocket portion, through holes that penetrate to a back surface of the susceptor and are opened at the time of performing the vapor-phase epitaxy are formed in the lower-stage-pocket portion, and a groove is provided on the back surface of the susceptor at a position corresponding to that of the upper-stage-pocket portion.
    Type: Application
    Filed: February 13, 2012
    Publication date: December 5, 2013
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Masato Ohnishi
  • Patent number: 8591652
    Abstract: The invention relates to a free-standing semiconductor substrate as well as a process and a mask layer for the manufacture of a free-standing semiconductor substrate, wherein the material for forming the mask layer consists at least partially of tungsten silicide nitride or tungsten silicide and wherein the semiconductor substrate self-separates from the starting substrate without further process steps.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: November 26, 2013
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Christian Hennig, Markus Weyers, Eberhard Richter, Guenther Traenkle
  • Patent number: 8585820
    Abstract: Methods for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, or for wafers. The equipment and methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. The method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber to form the semiconductor material; removing exhaust gases including unreacted Group III precursor, unreacted Group V component and reaction byproducts; and heating the exhaust gases to a temperature sufficient to reduce condensation thereof and enhance manufacture of the semiconductor material. Advantageously, the exhaust gases are heated to sufficiently avoid condensation to facilitate sustained high volume manufacture of the semiconductor material.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: November 19, 2013
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Patent number: 8585822
    Abstract: The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 19, 2013
    Assignee: Sixpoint Materials, Inc.
    Inventors: Tadao Hashimoto, Masanori Ikari, Edward Letts
  • Patent number: 8580034
    Abstract: A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si layer on the strained Ge-containing layer, maintaining the substrate at a temperature less than 700° C., and generating a soft plasma in the vacuum processing tool. The Si layer is exposed to the soft plasma to form a Si-containing dielectric layer while minimizing oxidation and strain relaxation in the underlying strained Ge-containing layer. A semiconductor device containing a substrate, a strained Ge-containing layer on the substrate, and an Si-containing dielectric layer formed on the strained Ge-containing layer is provided. The semiconductor device can further contain a gate electrode layer on the Si-containing dielectric layer or a high-k layer on the Si-containing dielectric layer and a gate electrode layer on the high-k layer.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: November 12, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Gert Leusink
  • Patent number: 8580035
    Abstract: Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities—e.g., a dislocation density below 104 cm?2 and an inclusion density below 104 cm?3 and/or a MV density below 104 cm?3.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 12, 2013
    Assignee: Crystal IS, Inc.
    Inventors: Robert Bondokov, Kenneth E. Morgan, Glen A. Slack, Leo J. Schowalter
  • Patent number: 8574364
    Abstract: The invention relates to a GaN-crystal free-standing substrate obtained from a GaN crystal grown by HVPE with a (0001) plane serving as a crystal growth plane and at least one plane of a {10-11} plane and a {11-22} plane serving as a crystal growth plane that constitutes a facet crystal region, except for the side surface of the crystal, wherein the (0001)-plane-growth crystal region has a carbon concentration of 5×1016 atoms/cm3 or less, a silicon concentration of 5×1017 atoms/cm3 or more and 2×1018 atoms/cm3 or less, and an oxygen concentration of 1×1017 atoms/cm3 or less; and the facet crystal region has a carbon concentration of 3×1016 atoms/cm3 or less, a silicon concentration of 5×1017 atoms/cm3 or less, and an oxygen concentration of 5×1017 atoms/cm3 or more and 5×1018 atoms/cm3 or less.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: November 5, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinsuke Fujiwara, Koji Uematsu, Hitoshi Kasai, Takuji Okahisa
  • Patent number: 8568530
    Abstract: Precursors suitable for chemical vapor deposition, especially ALD, of hafnium oxide or zirconium oxide, have the general formula: (R1Cp)2MR2 wherein Cp represents a cyclopentadienyl ligand, R1 is H or a substituting alkyl group, alkoxy group or amido group of the Cp ligand, R2 is an alkyl group, an alkoxy group or an amido group and M is hafnium or zirconium.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: October 29, 2013
    Assignee: Sigma-Aldrich Co. LLC
    Inventors: Peter Nicholas Heys, Paul Williams, Fuquan Song
  • Publication number: 20130269599
    Abstract: Apparatus and method for continuous pressure control in a process chamber. An apparatus includes a process chamber configured to receive a wafer; at least one pump coupled to the process chamber for maintaining pressure in the process chamber; an inlet for receiving reactive gasses into the process chamber; and a pressure control valve positioned between the at least one pump and configured to seal the process chamber to control the pressure in the process chamber. A method includes disposing at least one semiconductor wafer into a process chamber that is coupled to a pump for maintaining a sub-atmospheric pressure within the process chamber; introducing reactive process gasses into the process chamber; using a pressure control valve, at least partially sealing the process chamber; and increasing the pressure within the process chamber while exposing the semiconductor wafer to the process gasses to form epitaxial material. Additional embodiments are disclosed.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 17, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Feng Lin, Tsung-Hsun Yu
  • Patent number: 8557043
    Abstract: The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: October 15, 2013
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Masanori Ikari, Edward Letts
  • Patent number: 8551246
    Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: October 8, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
  • Patent number: 8545626
    Abstract: A method for efficiently producing a plate-like nitride semiconductor crystal having the desired principal plane in a simple method is provided. A raw material gas is fed to a seed crystal in which a ratio (L/W) of length L in a longitudinal direction and maximum width W, of a plane of projection obtained by projecting a crystal growth face on the seed crystal in a growth direction is from 2 to 400, and the maximum width W is 5 mm or less, thereby growing a plate-like semiconductor crystal on the seed crystal.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: October 1, 2013
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Kenji Fujito, Shuichi Kubo, Yoko Mashige
  • Publication number: 20130239615
    Abstract: The present application discloses the details of a microwave plasma chemical vapor deposition process that uses Nitrogen and Diborane simultaneously in combination along with the Methane and Hydrogen gases to grow white color diamonds. The invention embodies using nitrogen to avoid inclusions and impurities in the CVD diamond samples and Diborane for the color enhancement during the growth of diamond. It is also found that heating of the so grown diamonds to 2000 C results in significant color enhancement due to the compensation of Nitrogen and Boron centers in the samples. The origin of the various colors in diamond is explained on the basis of the band diagram of CVD diamond.
    Type: Application
    Filed: October 11, 2010
    Publication date: September 19, 2013
    Inventor: Devi Shanker Misra
  • Publication number: 20130233240
    Abstract: The present application relates to methods for depositing a smooth, germanium rich epitaxial film by introducing silylgermane as a source gas into a reactor at low temperatures. The epitaxial film can be strained and serve as an active layer, or relaxed and serve as a buffer layer. In addition to the silylgermane gas, a diluent is provided to modulate the percentage of germanium in a deposited germanium-containing film by varying the ratio of the silylgermane gas and the diluent. The ratios can be controlled by way of dilution levels in silylgermane storage containers and/or separate flow, and are selected to result in germanium concentration greater than 55 atomic % in deposited epitaxial silicon germanium films. The diluent can include a reducing gas such as hydrogen gas or an inert gas such as nitrogen gas. Reaction chambers are configured to introduce silylgermane and the diluent to deposit the silicon germanium epitaxial films.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Applicant: ASM AMERICA, INC.
    Inventors: Nyles W. Cody, Shawn G. Thomas
  • Patent number: 8529698
    Abstract: Methods, devices, and compositions of matter related to high efficiency InGaN-based photovoltaic devices. The disclosed synthesis of semiconductor heterostructures may be exploited to produce higher efficiency, longer lasting, photovoltaic cells.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: September 10, 2013
    Assignee: Arizona Board Of Regents For And On Behalf Of Arizona State University
    Inventors: Fernando A. Ponce, Rafael Garcia