With Decomposition Of A Precursor (except Impurity Or Dopant Precursor) Composed Of Diverse Atoms (e.g., Cvd) Patents (Class 117/88)
  • Publication number: 20120325138
    Abstract: A film-forming apparatus and method comprising a film-forming chamber for supplying a reaction gas into, a cylindrical shaped liner provided between an inner wall of the film-forming chamber and a space for performing a film-forming process, a main-heater for heating a substrate placed inside the liner, from the bottom side, a sub-heater cluster provided between the liner and the inner wall, for heating the substrate from the top side, wherein the main-heater and the sub-heater cluster are resistive heaters, wherein the sub-heater cluster has a first sub-heater provided at the closest position to the substrate, and a second sub-heater provided above the first sub-heater, wherein the first sub-heater heats the substrate in combination with the main-heater, the second sub-heater heats the liner at a lower output than the first sub-heater, wherein each temperature of the main-heater, the first sub-heater, and the second sub-heater is individually controlled.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 27, 2012
    Applicants: NuFlare Techology, Inc., Toyota Jidosha Kabushiki Kaisha, Denso Corporation, Central Res. Institute of Electric Power Industry
    Inventors: Kunihiko SUZUKI, Hideki Ito, Naohisa Ikeya, Hidekazu Tsuchida, Isaho Kamata, Masahiko Ito, Masami Naito, Hiroaki Fujibayashi, Ayumu Adachi, Koichi Nishikawa
  • Patent number: 8334016
    Abstract: Metal silicates or phosphates are deposited on a heated substrate by the reaction of vapors of alkoxysilanols or alkylphosphates along with reactive metal amides, alkyls or alkoxides. For example, vapors of tris(tert-butoxy)silanol react with vapors of tetrakis(ethylmethylamido)hafnium to deposit hafnium silicate on surfaces heated to 300° C. The product film has a very uniform stoichiometry throughout the reactor. Similarly, vapors of diisopropylphosphate react with vapors of lithium bis(ethyldimethylsilyl)amide to deposit lithium phosphate films on substrates heated to 250° C. Supplying the vapors in alternating pulses produces these same compositions with a very uniform distribution of thickness and excellent step coverage.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: December 18, 2012
    Assignee: President and Fellows of Harvard College
    Inventors: Roy G. Gordon, Jill S. Becker, Dennis Hausmann, Seigi Suh
  • Patent number: 8328937
    Abstract: A seed crystal axis used in a solution growth of single crystal production system is provided to prevent formation of polycrystals and grow a single crystal with a high growth rate. The seed crystal axis includes a seed crystal bonded to a seed crystal support member between which is interposed a laminated carbon sheet having a high thermal conductivity in a direction perpendicular to a solution surface of a solvent. The laminated carbon sheet includes a plurality of carbon thin films laminated with an adhesive or a plurality of pieces with differing lamination directions arranged in a lattice. Alternatively, a wound carbon sheet including a carbon strip wound concentrically from the center or a wound carbon sheet including a plurality of carbon strips with differing thicknesses which are wound and laminated from the center may be provided.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: December 11, 2012
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidemitsu Sakamoto, Yasuyuki Fujiwara
  • Patent number: 8328935
    Abstract: The present invention is a method of manufacturing polycrystalline silicon rods, wherein silicon is deposited onto a silicon core wire by a chemical vapor deposition (CVD) method such that a silicon member, which is cut out from a single-crystalline silicon ingot at an off-angle range of 5 to 40 degrees relative to a crystal habit line of the ingot, is used as the silicon core wire. The single-crystalline silicon ingot is preferably grown by a Czochralski (CZ) method or floating zone (FZ) method, such that the ingot preferably has an interstitial oxygen concentration of 7 ppma to 20 ppma. Silicon rods produced by this method are less likely to suffer a breakage caused by cleavage during the growth process of polycrystalline silicon during CVD, and exhibit improved FZ method success rates. The polycrystalline silicon rods produced by this method also have low impurity contamination and high single-crystallization efficiency.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: December 11, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Michihiro Mizuno, Shinichi Kurotani, Shigeyoshi Netsu, Kyoji Oguro
  • Patent number: 8328936
    Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 11, 2012
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Patent number: 8329253
    Abstract: A method for forming a transparent conductive film by atomic layer deposition includes providing more than one kind of oxide precursor which is individually introduced into atomic layer deposition equipment through different sources, wherein the oxide precursors are consecutively introduced into the atomic layer deposition equipment at the same time, so that the oxide precursors are simultaneously present in the atomic layer deposition equipment, to form a uniform mixture of oxide precursors in a single adsorbate layer for settling onto a substrate in the atomic layer deposition equipment. Then, an oxidant is provided to react with the oxide precursors to form a single multi-oxide atomic layer. The above mentioned steps are repeated to form a plurality of multi-oxide atomic layers.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: December 11, 2012
    Assignee: National Taiwan University
    Inventors: Feng-Yu Tsai, Chun-Ting Chou
  • Patent number: 8323402
    Abstract: Methods of growing and manufacturing aluminum nitride crystal, and aluminum nitride crystal produced by the methods. Preventing sublimation of the starting substrate allows aluminum nitride crystal of excellent crystallinity to be grown at improved growth rates. The aluminum nitride crystal growth method includes the following steps. Initially, a laminar baseplate is prepared, furnished with a starting substrate having a major surface and a back side, a first layer formed on the back side, and a second layer formed on the first layer. Aluminum nitride crystal is then grown onto the major surface of the starting substrate by vapor deposition. The first layer is made of a substance that at the temperatures at which the aluminum nitride crystal is grown is less liable to sublimate than the starting substrate. The second layer is made of a substance whose thermal conductivity is higher than that of the first layer.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: December 4, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keisuke Tanizaki, Naho Mizuhara, Michimasa Miyanaga, Hideaki Nakahata, Yoshiyuki Yamamoto
  • Patent number: 8323407
    Abstract: The invention relates to a method and system for epitaxial deposition of a Group III-V semiconductor material that includes gallium. The method includes reacting an amount of a gaseous Group III precursor having one or more gaseous gallium precursors as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber; and supplying sufficient energy to the gaseous gallium precursor(s) prior to their reacting so that substantially all such precursors are in their monomer forms. The system includes sources of the reactants, a reaction chamber wherein the reactants combine to deposit Group III-V semiconductor material, and one or more heating structures for heating the gaseous Group III precursors prior to reacting to a temperature to decompose substantially all dimers, trimers or other molecular variations of such precursors into their component monomers.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: December 4, 2012
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Publication number: 20120291698
    Abstract: Methods are disclosed for growing group III-nitride semiconductor compounds with advanced buffer layer technique. In an embodiment, a method includes providing a suitable substrate in a processing chamber of a hydride vapor phase epitaxy processing system. The method includes forming an AlN buffer layer by flowing an ammonia gas into a growth zone of the processing chamber, flowing an aluminum halide containing precursor to the growth zone and at the same time flowing additional hydrogen halide or halogen gas into the growth zone of the processing chamber. The additional hydrogen halide or halogen gas that is flowed into the growth zone during buffer layer deposition suppresses homogeneous AlN particle formation. The hydrogen halide or halogen gas may continue flowing for a time period while the flow of the aluminum halide containing precursor is turned off.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 22, 2012
    Inventors: Yuriy Melnik, Lu Chen, Hidehiro Kojiri
  • Publication number: 20120291696
    Abstract: A method and apparatus for depositing III-V material is provided. The apparatus includes a reactor partially enclosed by a selectively permeable membrane 12. A means is provided for generating source vapors, such as a vapor-phase halide of a group III element (IUPAC group 13) within the reactor volume 10, and an additional means is also provided for introducing a vapor-phase hydride of a group V element (IUPAC group 15) into the volume 10. The reaction of the group III halide and the group V hydride on a temperature-controlled substrate 18 within the reactor volume 10 produces crystalline III-V material and hydrogen gas. The hydrogen is preferentially removed from the reactor through the selectively permeable membrane 12, thus avoiding pressure buildup and reaction imbalance. Other gases within the reactor are unable to pass through the selectively permeable membrane.
    Type: Application
    Filed: May 21, 2011
    Publication date: November 22, 2012
    Inventor: Andrew Peter Clarke
  • Publication number: 20120282443
    Abstract: Provided is a base substrate with which a Group-III nitride crystal having a large area and a large thickness can be grown while inhibiting crack generation. A single-crystal substrate for use in growing a Group-III nitride crystal thereon, which satisfies the following expression (1), wherein Z1 (?m) is an amount of warpage of physical shape in a growth surface of the single-crystal substrate and Z2 (?m) is an amount of warpage calculated from a radius of curvature of crystallographic-plane shape in a growth surface of the single-crystal substrate: ?40<Z2/Z1<?1: Expression (1).
    Type: Application
    Filed: July 13, 2012
    Publication date: November 8, 2012
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Kenji FUJITO, Yasuhiro Uchiyama
  • Patent number: 8303924
    Abstract: A bulk AlN single crystal is grown on a monocrystalline AlN seed crystal having a central longitudinal mid-axis and disposed in a crystal growth region of a growing crucible. The bulk AlN single crystal grows in a growth direction oriented parallel to the longitudinal mid-axis by deposition on the AlN seed crystal. The crucible has a lateral crucible inner wall extending in the growth direction, a free space being provided between the AlN seed crystal and the growing bulk AlN single crystal on the one hand, and the lateral crucible inner wall on the other hand. Bulk AlN single crystals and monocrystalline AlN substrates produced therefrom are therefore obtained with only few dislocations, which furthermore are substantially distributed homogeneously. The growing crucible, inside which the crystal growth region is located, is an inner growing crucible which is arranged in an outer growing crucible.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: November 6, 2012
    Assignee: SiCrystal AG
    Inventors: Ralph-Uwe Barz, Thomas Straubinger
  • Publication number: 20120272892
    Abstract: A VPE reactor is improved by providing temperature control to within 0.5° C., and greater process gas uniformity via novel reactor shaping, unique wafer motion structures, improvements in thermal control systems, improvements in gas flow structures, improved methods for application of gas and temperature, and improved control systems for detecting and reducing process variation.
    Type: Application
    Filed: April 6, 2012
    Publication date: November 1, 2012
    Applicant: Veeco Instruments Inc.
    Inventors: Ajit Paranjpe, Alexander Gurary, William Quinn
  • Patent number: 8293011
    Abstract: A method for growing a Group III nitride semiconductor crystal is provided with the following steps: First, a chamber including a heat-shielding portion for shielding heat radiation from a material 13 therein is prepared. Then, material 13 is arranged on one side of heat-shielding portion in chamber. Then, by heating material to be sublimated, a material gas is deposited on the other side of heat-shielding portion in chamber so that a Group III nitride semiconductor crystal is grown.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 23, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Michimasa Miyanaga, Naho Mizuhara, Keisuke Tanizaki, Issei Satoh, Hisao Takeuchi, Hideaki Nakahata
  • Patent number: 8293592
    Abstract: A semiconductor device manufacturing method including: (a) loading into a chamber a substrate having at least an exposed silicon surface and an exposed surface of silicon oxide film or silicon nitride film on a substrate surface; (b) simultaneously supplying at least a first process gas containing silicon and a second process gas for etching into the chamber when the substrate inside the chamber is heated to a predetermined temperature; and (c) supplying into the chamber a third process gas having an etchability higher than the second process gas etchability. Steps (b) and (c) are performed at least once to selectively grow an epitaxial film on the exposed silicon surface of the substrate surface. A temperature of the substrate is maintained at the predetermined temperature from (b) to (c), and the temperature of the substrate is temporarily elevated above the predetermined temperature and then returned to the predetermined temperature in (c).
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: October 23, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Junichi Tanabe
  • Patent number: 8293012
    Abstract: Affords AlxGa1-xN crystal growth methods, as well as AlxGa1-xN crystal substrates, wherein bulk, low-dislocation-density crystals are obtained. The AlxGa1-xN crystal (0<x?1) growth method is a method of growing, by a vapor-phase technique, an AlxGa1-xN crystal (10), characterized by forming, in the growing of the crystal, at least one pit (10p) having a plurality of facets (12) on the major growth plane (11) of the AlxGa1-xN crystal (10), and growing the AlxGa1-xN crystal (10) with the at least one pit (10p) being present, to reduce dislocations in the AlxGa1-xN crystal (10).
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: October 23, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Michimasa Miyanaga, Naho Mizuhara, Hideaki Nakahata
  • Publication number: 20120255486
    Abstract: Disclosed herein is an apparatus for cleaning an inner surface of a film growth reaction chamber, including a supporting unit, a cleaning unit, an electric motor and a power supply apparatus. The cleaning unit includes a surface facing the inner surface of the reaction chamber, and the surface is provided with a plurality of scraping structures. The electric motor is provided on the supporting unit and includes a driving shaft. One end of the driving shaft is connected to the cleaning unit so as to drive the cleaning unit to move. The power supply apparatus is connected to the electric motor. The cleaning apparatus of the present application provides a method for cleaning the inner surface of the reaction chamber, which is highly automatic, effective and timesaving, and may ensure the quality and consistency of cleaning process.
    Type: Application
    Filed: April 5, 2012
    Publication date: October 11, 2012
    Applicant: Advanced Micro-Fabrication Equipment Inc., Shanghai
    Inventors: Yinxin Jiang, Yijun Sun, Zhiyou Du
  • Patent number: 8282733
    Abstract: The manufacturing method of a semiconductor apparatus has a step for carrying in the substrate into the processing chamber; a step for heating the processing chamber and the substrate to the predetermined temperature; and a gas supply and exhaust step for supplying and exhausting desired gas into and from the processing chamber, wherein the gas supply and exhaust step repeats by the predetermined times a first supply step for supplying silicon-type gas and hydrogen gas into the processing chamber; a first exhaust step for exhausting at least said silicon-type gas from the processing chamber; a second supply step for supplying chlorine gas and hydrogen gas into the processing chamber; and a second exhaust step for exhausting at least the chlorine gas from the processing chamber.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: October 9, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Katsuhiko Yamamoto
  • Publication number: 20120248463
    Abstract: A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the chamber; and epitaxially growing a layer of SiC on a surface of the SiC substrate. The SiC substrate is heated to the first temperature at a rate of at least 30° C./minute. The surface of the SiC substrate is inclined at an angle of from 1° to 3° with respect to a basal plane of the substrate material.
    Type: Application
    Filed: June 15, 2012
    Publication date: October 4, 2012
    Applicant: SS SC IP, LLC
    Inventor: Jie ZHANG
  • Publication number: 20120247386
    Abstract: A method and apparatus for forming heterojunction stressor layers is described. A germanium precursor and a metal precursor are provided to a chamber, and an epitaxial layer of germanium-metal alloy formed on the substrate. The metal precursor is typically a metal halide, which may be provided by subliming a solid metal halide or by contacting a pure metal with a halogen gas. The precursors may be provided through a showerhead or through a side entry point, and an exhaust system coupled to the chamber may be separately heated to manage condensation of exhaust components.
    Type: Application
    Filed: July 28, 2011
    Publication date: October 4, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Errol Antonio C. Sanchez, David K. Carlson
  • Publication number: 20120251428
    Abstract: Disclosed is a crystal growing apparatus, which is useful when growing a nitride semiconductor crystal by means of hydride vapor phase deposition, and which is capable of effectively preventing a reaction tube from breaking, and is capable of growing the high quality nitride semiconductor single crystal. Also disclosed are a method for manufacturing the nitride compound semiconductor crystal using such crystal growing apparatus, and the nitride compound semiconductor crystal. In the horizontal-type crystal growing apparatus for growing the nitride compound semiconductor crystal on a base substrate using the hydride vapor phase deposition, between the reaction tube (11) end portion (upstream flange (11a)) on the side where raw material gas supply tubes (14, 15) are disposed, and a base substrate disposing position (substrate holder (13)), a plurality of partitioning plates (20) that partition the reaction tube in the axis direction are provided.
    Type: Application
    Filed: March 3, 2011
    Publication date: October 4, 2012
    Inventor: Satoru Morioka
  • Publication number: 20120240845
    Abstract: Disclosed is a novel method wherein an aluminum nitride single crystal having good crystallinity is efficiently and easily manufactured. The method for produsing an aluminum nitride single crystal wherein nitrogen gas is circulated in the presence of a raw material gas generation source, which generates an aluminum gas or an aluminum oxide gas, and a carbon body, and then the aluminum nitride single crystal is grown under a heating condition; characterized in that, at least a part of the carbon body does not directly contact with the raw material gas generation source, at least a part of the raw material gas generation source does not directly contact with the carbon body, the raw material gas generation source and the carbon body are positioned to make a space in which a clearance between the raw material gas generation source, which does not contact with the carbon body, and the carbon body, which does not contact with the raw material gas generation source, is 0.
    Type: Application
    Filed: November 29, 2010
    Publication date: September 27, 2012
    Applicants: Tohoku University, Tokuyama Corporation
    Inventors: Hiroyuki Fukuyama, Masanobu Azuma, Kazuya Takada, Takeshi Hattori
  • Publication number: 20120234229
    Abstract: Substrate support assemblies and deposition chambers employing such support assemblies to improve temperature uniformity during film depositions, such as epitaxial growths of group-V material stacks for LEDs. In one embodiment, the support assembly includes a first component having a first thermal resistance and a top surface upon which the substrate is to be disposed at a first location. The support assembly further includes a second component to be disposed over the first component and cover a second location of the susceptor while the substrate is disposed over the first location and having a second thermal resistance to insulate regions of the susceptor adjacent to the substrate by an amount approximating that of the substrate during a deposition process. In embodiments, the second component is removable from the first component and supports the substrate in absence of the first component during transfer of the substrate between multiple deposition systems.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 20, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Tuan Anh NGUYEN, Donald J.K. Olgado, David H. Quach
  • Publication number: 20120235116
    Abstract: One embodiment of a quantum well structure comprises an active region including active layers that comprise quantum wells and barrier layers wherein some or all of the active layers are p type doped. P type doping some or all of the active layers improves the quantum efficiency of III-V compound semiconductor light emitting diodes by locating the position of the P-N junction in the active region of the device thereby enabling the dominant radiative recombination to occur within the active region. In one embodiment, the quantum well structure is fabricated in a cluster tool having a hydride vapor phase epitaxial (HVPE) deposition chamber with a eutectic source alloy. In one embodiment, the indium gallium nitride (InGaN) layer and the magnesium doped gallium nitride (Mg—GaN) or magnesium doped aluminum gallium nitride (Mg—AlGaN) layer are grown in separate chambers by a cluster tool to avoid indium and magnesium cross contamination.
    Type: Application
    Filed: July 30, 2010
    Publication date: September 20, 2012
    Inventors: Jie Su, Olga Kryliouk, Yuriy Melnik, Hidehiro Kojiri, Lu Chen, Tetsuya Ishikawa
  • Patent number: 8268076
    Abstract: SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: September 18, 2012
    Assignee: Siltronic AG
    Inventors: Thomas Schroeder, Peter Storck, Hans Joachim Muessig
  • Patent number: 8263424
    Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: September 11, 2012
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Tadao Hashimoto, Hitoshi Sato, Shuji Nakamura
  • Patent number: 8262796
    Abstract: A thin-film single crystal growing method includes preparing a substrate, irradiating an excitation beam on a metallic target made of a pure metal or an alloy in a predetermined atmosphere, and combining chemical species including any of atoms, molecules, and ions released from the metallic target by irradiation of the excitation beam with atoms contained in the predetermined atmosphere to form a thin film on the substrate.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: September 11, 2012
    Assignee: Waseda University
    Inventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
  • Publication number: 20120225004
    Abstract: In a physical vapor transport growth technique for silicon carbide a silicon carbide powder and a silicon carbide seed crystal are introduced into a physical vapor transport growth system and halosilane gas is introduced separately into the system. The source powder, the halosilane gas, and the seed crystal are heated in a manner that encourages physical vapor transport growth of silicon carbide on the seed crystal, as well as chemical transformations in the gas phase leading to reactions between halogen and chemical elements present in the growth system.
    Type: Application
    Filed: May 15, 2012
    Publication date: September 6, 2012
    Applicant: II-VI INCORPORATED
    Inventors: Ilya Zwieback, Thomas E. Anderson, Avinash K. Gupta
  • Publication number: 20120216743
    Abstract: A downsized substrate may be housed in a substrate accommodation vessel (FOUP) constituting a transfer system corresponding to a large diameter substrate. An attachment includes an upper plate and a lower plate supported by a first support groove that can support an 8-inch wafer, and holding columns installed at the upper plate and the lower plate and including a second support groove that can support a 2-inch wafer (if necessary, via a wafer holder and a holder member). Accordingly, the 2-inch wafer can be housed in a pod corresponding to the 8-inch wafer, and the pod, which is a transfer system, can be standardized to reduce cost of a semiconductor manufacturing apparatus. In addition, a distance from each gas supply nozzle to the wafer can be increased to sufficiently mix reactive gases before arrival at the wafer and improve film-forming precision to the wafer.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 30, 2012
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takeshi Itoh, Akinori Tanaka
  • Publication number: 20120217618
    Abstract: The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 30, 2012
    Applicant: The Arizona Board of Regents, a body corporated acting on behalf of Arizona State University
    Inventors: John Kouvetakis, Cole J. Ritter, III
  • Patent number: 8252112
    Abstract: A method and apparatus for the unusually high rate deposition of thin film materials on a stationary or continuous substrate. The method includes delivery of a pre-selected precursor intermediate to a deposition chamber and formation of a thin film material from the intermediate. The intermediate is formed outside of the deposition chamber and includes a metastable species such as a free radical. The intermediate is pre-selected to include a metastable species conducive to the formation of a thin film material having a low defect concentration. By forming a low defect concentration material, deposition rate is decoupled from material quality and heretofore unprecedented deposition rates are achieved. In one embodiment, the pre-selected precursor intermediate is SiH3.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: August 28, 2012
    Assignee: Ovshinsky Innovation, LLC
    Inventor: Stanford R. Ovshinsky
  • Publication number: 20120210932
    Abstract: An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.
    Type: Application
    Filed: February 23, 2011
    Publication date: August 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: BAHMAN HEKMATSHOAR-TABARI, Ali Khakifirooz, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8236267
    Abstract: The present invention discloses a high-pressure vessel of large size formed with a limited size of e.g. Ni—Cr based precipitation hardenable superalloy. The vessel may have multiple zones. For instance, the high-pressure vessel may be divided into at least three regions with flow-restricting devices and the crystallization region is set higher temperature than other regions. This structure helps to reliably seal both ends of the high-pressure vessel, and at the same time, may help to greatly reduce unfavorable precipitation of group III nitride at the bottom of the vessel. This invention also discloses novel procedures to grow crystals with improved purity, transparency and structural quality. Alkali metal-containing mineralizers are charged with minimum exposure to oxygen and moisture until the high-pressure vessel is filled with ammonia. Several methods to reduce oxygen contamination during the process steps are presented.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: August 7, 2012
    Assignee: Sixpoint Materials, Inc.
    Inventors: Tadao Hashimoto, Edward Letts, Masanori Ikari
  • Patent number: 8236103
    Abstract: A method for producing a Group III nitride semiconductor crystal includes a first step of supplying a Group III raw material and a Group V raw material at a V/III ratio of 0 to 1,000 to form and grow a Group III nitride semiconductor on a heated substrate and a second step of vapor-phase-growing a Group III nitride semiconductor crystal on the substrate using a Group III raw material and a nitrogen raw material.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: August 7, 2012
    Assignee: Showa Denko K.K.
    Inventors: Hisayuki Miki, Tetsuo Sakurai, Mineo Okuyama
  • Patent number: 8231728
    Abstract: An epitaxial growth method forming a semiconductor thin film including a heterojunction of a group III-V compound semiconductor by means of molecular beam epitaxy. The method is configured to include: a first step of irradiating a molecular beam of at least one of group III elements and a molecular beam of a first group V element to form a first compound semiconductor layer; a second step of stopping the irradiation of the molecular beam of the group III element and the molecular beam of the first group V element to halt growth until an amount of the first group V element supplied is reduced to 1/10 or less of a supply of the first group V element in the first step; and a third step of irradiating a molecular beam of at least one of the group III elements and a molecular beam of a second group V element to form a second compound semiconductor layer, which is different from the first compound semiconductor, on the first compound semiconductor layer.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: July 31, 2012
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Misao Takakusaki, Susumu Kanai
  • Patent number: 8226767
    Abstract: “Super-hetero-epitaxial” combinations comprise epitaxial growth of one material on a different material with different crystal structure. Compatible crystal structures may be identified using a “Tri-Unity” system. New bandgap engineering diagrams are provided for each class of combination, based on determination of hybrid lattice constants for the constituent materials in accordance with lattice-matching equations. Using known bandgap figures for previously tested materials, new materials with lattice constants that match desired substrates and have the desired bandgap properties may be formulated by reference to the diagrams and lattice matching equations. In one embodiment, this analysis makes it possible to formulate new super-hetero-epitaxial semiconductor systems, such as systems based on group IV alloys on c-plane LaF3; group IV alloys on c-plane langasite; Group III-V alloys on c-plane langasite; and group II-VI alloys on c-plane sapphire.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: July 24, 2012
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott
  • Publication number: 20120183728
    Abstract: Methods for growing a three-dimensional nanorod network in three-dimensional growth spaces, including highly confined spaces, are provided. The methods are derived from atomic layer deposition (ALD) processes, but use higher temperatures and extended pulsing and/or purging times. Through these methods, networks of nanorods can be grown uniformly along the entire inner surfaces of confined growth spaces.
    Type: Application
    Filed: January 18, 2011
    Publication date: July 19, 2012
    Inventors: Xudong Wang, Jian Shi
  • Patent number: 8221548
    Abstract: A process for producing a diamond thin-film includes forming a diamond crystal thin-film on a substrate and firing the diamond crystal thin-film at a sufficient temperature under high pressure under which a diamond is stable. A diamond single-crystal substrate having a diamond single-crystal thin-film formed thereon is placed in an ultra-high-pressure and high-temperature firing furnace to anneal the diamond single-crystal thin-film under the conditions of 1200° C. and 6 GPa.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: July 17, 2012
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Publication number: 20120177902
    Abstract: Multiferroic articles including highly resistive, strongly ferromagnetic strained thin films of BiFe0.5Mn0.5O3 (“BFMO”) on (001) strontium titanate and Nb-doped strontium titanate substrates were prepared. The films were tetragonal with high epitaxial quality and phase purity. The magnetic moment and coercivity values at room temperature were 90 emu/cc (H=3 kOe) and 274 Oe, respectively. The magnetic transition temperature was strongly enhanced up to approximately 600 K, which is approximately 500 K higher than for pure bulk BiMnO3.
    Type: Application
    Filed: September 1, 2011
    Publication date: July 12, 2012
    Inventors: Judith L. Driscoll, Quanxi Jia
  • Publication number: 20120174859
    Abstract: After removing deposit on a susceptor in an epitaxial growth furnace by a cleaning recipe (step S101), a first epitaxial wafer is produced by growing an epitaxial layer on a first wafer based on a process recipe A (step S102). Subsequently, a step of producing an epitaxial wafer by growing an epitaxial layer on a wafer based on a process recipe B including second control parameters set such that the epitaxial wafer has approximately the same film thickness profile as the first wafer (step S103) is repeated a plurality of times to successively produce a plurality of epitaxial wafers (step S104). The cleaning recipe, the process recipe A, and the process recipe B repeated a plurality of times are carried out repeatedly (step S105).
    Type: Application
    Filed: September 10, 2010
    Publication date: July 12, 2012
    Inventors: Kenji Sakamoto, Masayuki Tsuji
  • Patent number: 8216364
    Abstract: Direct resistive heating is used to grow nanotubes out of carbon and other materials. A growth-initiated array of nanotubes is provided using a CVD or ion implantation process. These processes use indirect heating to heat the catalysts to initiate growth. Once growth is initiated, an electrical source is connected between the substrate and a plate above the nanotubes to source electrical current through and resistively heat the nanotubes and their catalysts. A material source supplies the heated catalysts with carbon or another material to continue growth of the array of nanotubes. Once direct heating has commenced, the source of indirect heating can be removed or at least reduced. Because direct resistive heating is more efficient than indirect heating the total power consumption is reduced significantly.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: July 10, 2012
    Assignee: Raytheon Company
    Inventors: Delmar L. Barker, Mead M. Jordan, William R. Owens
  • Patent number: 8216365
    Abstract: Objects of the invention are to further enhance crystallinity and crystallinity uniformity of a semiconductor crystal produced through the flux method, and to effectively enhance the production yield of the semiconductor crystal. The c-axis of a seed crystal including a GaN single-crystal layer is aligned in a horizontal direction (y-axis direction), one a-axis of the seed crystal is aligned in the vertical direction, and one m-axis is aligned in the x-axis direction. Thus, three contact points at which a supporting tool contacts the seed crystal are present on m-plane. The supporting tool has two supporting members, which extend in the vertical direction. One supporting member has an end part, which is inclined at 30° with respect to the horizontal plane ?. The reasons for supporting a seed crystal at m-plane thereof are that m-plane exhibits a crystal growth rate, which is lower than that of a-plane, and that desired crystal growth on c-plane is not inhibited.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: July 10, 2012
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Seiji Nagai, Shiro Yamazaki, Takayuki Sato, Katsuhiro Imai, Makoto Iwai, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
  • Patent number: 8216366
    Abstract: A cubic silicon carbide single crystal thin film is manufactured by a method. A sacrificial layer is formed on a surface of a substrate. A cubic semiconductor layer is formed on the sacrificial layer, the cubic semiconductor layer having at least a surface of cubic crystal structure. A cubic silicon carbide single crystal layer is formed on the cubic semiconductor layer. The sacrificial layer is etched away to release a multilayer structure of the cubic semiconductor layer and the 3C—SiC layer from the substrate. A cubic silicon carbide single crystal thin film of a multilayer structure includes an AlxGa1-xAs (0.6>x?0) layer and a cubic silicon carbide single crystal layer. A metal layer is formed on a substrate. The multilayer structure is bonded to the metal layer with the AlxGa1-xAs (0.6>x?0) in direct contact with the metal layer.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: July 10, 2012
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Masaaki Sakuta
  • Patent number: 8216367
    Abstract: A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: July 10, 2012
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 8216537
    Abstract: The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: July 10, 2012
    Assignee: Arizona Board of Regents
    Inventors: John Kouvetakis, Cole J. Ritter, III, Changwu Hu, Ignatius S. T. Tsong, Andrew Chizmeshya
  • Publication number: 20120160157
    Abstract: There is provided a method of manufacturing a light emitting diode, the method including: growing a first conductivity type nitride semiconductor layer and an active layer on a substrate in a first reaction chamber; transferring the substrate having the first conductivity type nitride semiconductor layer and the active layer grown thereon to a second reaction chamber; and growing a second conductivity type nitride semiconductor layer on the active layer in the second reaction chamber, wherein an atmosphere including a nitride source gas and a dopant source gas supplying a dopant to be included in the second conductivity type nitride semiconductor layer is created in an interior of the second reaction chamber prior to the transferring of the substrate to the second reaction chamber. This method improves a system's operational capability and productivity. In addition, the crystallinity and doping uniformity of semiconductor layers obtained by this method may be improved.
    Type: Application
    Filed: August 12, 2011
    Publication date: June 28, 2012
    Inventors: Sang Heon HAN, Do Young Rhee, Jin Young Lim, Ki Sung Kim, Young Sun Kim
  • Publication number: 20120153298
    Abstract: A system for crystal growth having rapid heating and cooling. A fluid-cooling jacket having a reflective shield contained therein is disposed around a heating cylinder in which crystal growth takes place. A heating coil is disposed round the cooling jacket. The invention also includes a method of crystal growth and semiconductor devices formed using the inventive methods and systems.
    Type: Application
    Filed: February 12, 2008
    Publication date: June 21, 2012
    Applicant: CARACAL, INC.
    Inventors: Olof Claes Erik KORDINA, Rune BERGE
  • Patent number: 8197598
    Abstract: A method for making iron silicide nano-wires comprises the following steps. Firstly, providing a growing substrate and a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, placing the growing substrate and a quantity of iron powder into the reacting room. Thirdly, introducing a silicon-containing gas into the reacting room. Finally, heating the reacting room to a temperature of 600˜1200° C.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: June 12, 2012
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 8197597
    Abstract: The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods and equipment for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber under conditions sufficient to provide sustained high volume manufacture of the semiconductor material on one or more substrates, with the gaseous Group III precursor continuously provided at a mass flow of 50 g Group III element/hour for at least 48 hours.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: June 12, 2012
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Patent number: 8192713
    Abstract: A method of incorporating a mark of origin, such as a brand mark, or fingerprint in a CVD single crystal diamond material, includes the steps of providing a diamond substrate, providing a source gas, dissociating the source gas thereby allowing homoepitaxial diamond growth, and introducing in a controlled manner a dopant into the source gas in order to produce the mark of origin or fingerprint in the synthetic diamond material. The dopant is selected such that the mark of origin or fingerprint is not readily detectable or does not affect the perceived quality of the diamond material under normal viewing conditions, but which mark of origin or fingerprint is detectable or rendered detectable under specialised conditions, such as when exposed to light or radiation of a specified wavelength, for example. Detection of the mark of origin or fingerprint may be visual detection or detection using specific optical instrumentation, for example.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: June 5, 2012
    Inventors: Daniel James Twitchen, Geoffrey Alan Scarsbrook, Philip Maurice Martineau, Paul Martyn Spear