Abstract: The present invention relates to a semiconductor device with one or more current confinement regions and to a method of manufacturing such a device, particularly buried heterostructure light emitting devices such as semiconductor lasers and light emitting diodes. The device comprises an active layer, a current conduction region, one or more current confinement regions adjacent the current conduction region. The current conduction region and current confinement region are arranged to channel an applied electric current to the active layer. The or each current confinement region includes both a metal-doped current blocking structure and a p-n junction current blocking structure. The p-n current blocking structure is between the current conduction region and the metal-doped current blocking structure.

Abstract: An active feedback network for gain linearization is disclosed. High quality epitaxial layers of monocrystalline materials grown over monocrystalline substrates enables the formation of an active device on a monocrystalline compound semiconductor material and an active feedback device on a monocrystalline substrate. Alternatively, the active device may be formed on the monocrystalline substrate and the active feedback device may be formed on the monocrystalline compound semiconductor material. In either case, the differing characteristics of each semiconductor material is used to advantageously provide wideband operation with additional benefits in stability.

Abstract: A semiconductor structure for implementing optical beam switching includes a monocrystalline silicon substrate and an amorphous oxide material overlying the monocrystalline silicon substrate. A monocrystalline perovskite oxide material overlies the amorphous oxide material and a monocrystalline compound semiconductor material overlies the monocrystalline perovskite oxide material. An optical source component that is operable to transmit radiant energy is formed within the monocrystalline compound semiconductor layer. A diffraction grating including an electrochromic portion is optically coupled to the optical source component.

Abstract: A heterojunction bipolar transistor comprises a collector layer, a base layer, and an emitter layer stacked sequentially. The base layer comprises a first base layer joined to the collector layer in an inward base area directly below the emitter layer and a second base layer joined to the collector layer in an outward base area adjacent to the inward base area. The second base layer is formed of a semiconductor with a wider energy band gap than the collector layer.

Abstract: A practically realizable semiconductor magnetic body having a flat-band structure is disclosed. The semiconductor magnetic body is formed by semiconductor quantum dots arranged on lattice points such that electrons can transfer between neighboring quantum dots and the electron energy band contains a flat-band structure, where each quantum dot is a structure in which electrons are confined inside a region which is surrounded by high energy potential regions, and the flat-band structure is a band structure in which energy dispersion of electrons has hardly any wave number dependency.

Abstract: A smoothing structure containing indium is formed between the substrate and the active region of a III-nitride light emitting device to improve the surface characteristics of the device layers. In some embodiments, the smoothing structure is a single layer, separated from the active region by a spacer layer which typically does not contain indium. The smoothing layer contains a composition of indium lower than the active region, and is typically deposited at a higher temperature than the active region. The spacer layer is typically deposited while reducing the temperature in the reactor from the smoothing layer deposition temperature to the active region deposition temperature. In other embodiments, a graded smoothing region is used to improve the surface characteristics. The smoothing region may have a graded composition, graded dopant concentration, or both.

Abstract: The method produces coherent dislocation-free regions from initially dislocated and/or defect-rich lattice mismatched layer grown on top of the substrate having a different lattice constant, which does not contain any processing steps before of after the lattice-mismatched layer growth. The process preferably uses in situ formation of a cap layer on top of a dislocated layer. The cap layer preferably has a lattice parameter close to that in the underlying substrate, and different from that in the lattice mismatched layer in no strain state. Under these conditions, the cap layer undergoes elastic repulsion from the regions in the vicinity of the dislocations, where the lattice parameter is the most different from that in the substrate. The cap layer is absent in these regions.

Abstract: A semiconductor device comprising a plurality of heterojunction bipolar transistors with their base layer made of GaAsSb or InGaAs, a GaAs substrate, and a buffer layer placed between the base layer and the substrate is fabricated. The substrate and the buffer layer that lie directly under the intrinsic regions of a part or all of the plurality of heterojunction bipolar transistors are removed. Thereby, a semiconductor device using HBTs that can operate with a power supply voltage of 2V or below can be provided at reduced cost as a well-reliable product, and a power amplifier with high power conversion efficiency can be provided.

Abstract: A semiconductor device includes an electrically conductive III-V doped semiconductor substrate of a first conduction type, a photodiode array having photodiode structures disposed on the III-V doped semiconductor substrate, a first III-V doped semiconductor layer of a second conduction type disposed between the photodiode structures and the III-V doped semiconductor substrate, etching trenches disposed on the III-V doped semiconductor substrate, each of the trenches having inner sides, the inner sides having an insulation layer and a metallization layer for electrically connecting the photodiode structures in series, the metallization layer disposed on the insulation layer; and partition lines separating each of the photodiode structures from others of the photodiode structures for producing an individual photodiode structure when the array is cut through the first III-V doped semiconductor layer along the partition lines.

Abstract: Transistor, is disclosed, including a base having a bundle of (n,n) nanotubes, and an emitter and a collector connected to opposite sides of the base each having (n,m, n−m≠3l) nanotubes, whereby substantially reducing a device size and improving an operation speed as the carbon nanotube has a thermal conductivity much better than silicon.

Abstract: A thin-film crystal wafer having a pn junction includes a first crystal layer of p GaAs, a second crystal layer of n InxAlyGa1-x-yP, the first and second crystal layers being lattice-matched layers that form a heterojunction, and a control layer of a thin-film of InxAlyGa1-x-yP differing in composition from the n InxAlyGa1-x-yP of the second crystal layer is formed at the interface of the heterojunction. The control layer enables the energy discontinuity at the interface of the InxAlyGa1-x-yP/GaAs heterojunction to be set within a relatively broad range of values and thus enables the current amplification factor and the offset voltage to be matched to specification values by varying the energy band gap at the heterojunction.

Abstract: In a high frequency semiconductor device, a shield plate which is connected to the ground potential is provided above an MMIC structure including line conductors, with an insulating interlayer provided therebetween. By using the shield plate to shield the MMIC, interference caused by external electromagnetic waves or leakage of electromagnetic waves to the exterior can be reduced in a chip alone.

Abstract: An array of photodiodes in series on a common semi-insulating substrate has a non-conductive buffer layer between the photodiodes and the semi-insulating substrate. The buffer layer reduces current injection leakage between the photodiodes of the array and allows optical energy to be converted to high voltage electrical energy.

Abstract: A superlattice structure for thermoelectric power generation includes m monolayers of a first barrier material alternating with n monolayers of a second quantum well material with a pair of monolayers defining a superlattice period and each of the materials having a relatively smooth interface therebetween. Each of the quantum well layers have a thickness which is less than the thickness of the barrier layer by an amount which causes substantial confinement of conduction carriers to the quantum well layer and the alternating layers provide a superlattice structure having a figure of merit which increases with increasing temperature.

Abstract: An acoustic charge transport device is formed by a process which introduces a process dependent variation in charge carrier density within the device. The acoustic charge transport device includes a transport channel operable to carry charge carriers in response to a surface acoustic wave. In addition, the acoustic charge transport device further includes a backgate for controlling the charge carrier density within the transport channel.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography. In accordance with one embodiment of the invention, there is provided a semiconductor structure including a planarized relaxed Si1−xGex layer on a substrate; and a device heterostructure deposited on said planarized relaxed Si1−xGex layer including at least one strained layer.

Abstract: An organic thin film device in which, as a junction interface shape between an organic thin film and an adjacent layer, a sectional contour shape of a device interface having a Hausdorff dimension, as one fractal dimension, falling within the range 1.5≦D≦2.0 is formed by defining the Hausdorff dimension and its scale length.

Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.

Abstract: A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates.

Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.

Abstract: A heterojunction bipolar transistor (20, 60) is provided with a silicon (Si) base region (34, 74) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36, 72) proximate the base region (34, 74) and a distal gallium phosphide (GaP) emitter layer (40, 66). The GaAs emitter layer (36, 72) is sufficiently thin, preferably less than 200 Å, so as to be coherently strained. In one embodiment, the GaP emitter layer includes a doped region (70) which serves as the emitter and a non-doped region (68) on which the intrinsic portion of the transistor (60) is formed.

Abstract: A semiconductor device comprises an n-conductive type Si substrate, a n-conductive type Si film formed on the n-conductive type Si substrate, a p-conductive type SiGe film formed on the n-conductive type Si film, a p-conductive type Si film formed on the p-conductive type SiGe film, a n-conductive type Si film formed on the p-conductive type Si film, a base electrode formed by removing a part of the n-conductive type Si film or changing the conductive type of a part of the n-conductive type Si film to a p-conductive type, and joining a metal terminal to a part of the p-conductive type Si film exposed by removing the N-type Si film or to the part of the n-conductive type Si film whose conductive type is changed to a p-conductive type, an emitter electrode formed by joining a metal terminal to the n-conductive type Si film, and a collector electrode formed by joining a metal terminal to a back surface of the n-conductive type Si substrate.

Abstract: A light-emitting diode comprising a quantum-wave reflection layer for electrons, a quantum-wave transmission layer for electrons, and an emission layer formed between the quantum-wave reflection layer and th e quantum-wave transmission layer is used as a photocoupler. Compared with a commercial product having a response velocity of 20 MHz, a response velocity of the light-emitting diode of the present invention is improved to be 100 MHz to 200 MHz. The quantum-wave reflection layer for electrons and the quantum-wave transmission layer for electrons are formed to have thicknesses of one fourth and a half of quantum wave of electrons, respectively.

Abstract: A pn junction diode (250) having its metallurgical junction of the oppositely-doped regions (254, 256) coincident with the surface WS of an electrically-doped wafer W and a method of forming such a diode. The method includes preparing (202) the wafer surface prior to placing the wafer into a reaction chamber (14). The preparation of the wafer surface includes UV ozonation (102d) and hydrogen-termination (102e) in a hydrofluoric acid solution. After the wafer surface is prepared, the wafer is inserted into the reaction chamber and heated to a temperature of less than 650° C. Without delay, a pn junction (252) is formed by growing on the wafer surface an epitaxial film layer having a doping opposite the doping of the wafer. The doped film layer is grown (204) by plasma-enhanced chemical vapor deposition while simultaneously introducing dopant atoms into the reaction chamber.

Abstract: A compliant substrate for the formation of semiconductor devices includes a crystalline base layer and a thin-film crystalline layer on and loosely bonded to the base layers. The thin-film layer has a high degree of lattice flexibility. A compliant substrate for formation of semiconductor devices may also include a crystalline base layer, and, on the base layer, a thin film layer having a lattice constant different from the lattice constant of the base layer. A method for formation of a compliant substrate for formation of semiconductor devices includes forming a thin film layer on a first substrate, bonding a first surface of the thin film layer to a surface of a second substrate having a lattice constant different from the lattice constant of the thin film layer either with or without twist bonding, and removing the first substrate to expose a second surface of the thin film layer.

Abstract: The photoconductive switch comprises a first confinement layer, a second confinement layer, a photoconductive layer that includes a doped sub-layer and an undoped sub-layer, a first electrode and a second electrode. The first confinement layer is a layer of a first semiconductor material having a first band-gap energy and a first conductivity type. The second confinement layer is a layer of a second semiconductor material having a second band-gap energy. The photoconductive layer is a layer of a third semiconductor material having a third band-gap energy and a second conductivity type, opposite to the first conductivity type. The photoconductive layer is sandwiched between the first confinement layer and the second confinement layer, and the third band-gap energy is less than the first and second band-gap energies. In the photoconductive layer, the doped sub-layer is in contact with the first confinement layer, and the undoped sub-layer is adjacent the second confinement layer.

Abstract: A structure with an optically active layer embedded in a Si wafer, such that the outermost epitaxial layer exposed to the CMOS processing equipment is always Si or another CMOS-compatible material such as SiO2. Since the optoelectronic layer is completely surrounded by Si, the wafer is fully compatible with standard Si CMOS manufacturing. For wavelengths of light longer than the bandgap of Si (1.1 &mgr;m), Si is completely transparent and therefore optical signals can be transmitted between the embedded optoelectronic layer and an external waveguide using either normal incidence (through the Si substrate or top Si cap layer) or in-plane incidence (edge coupling).

Abstract: An insulator-compound semiconductor interface structure is disclosed including compound semiconductor material with a spacer layer of semiconductor material having a bandgap which is wider than the bandgap of the compound semiconductor material positioned on a surface of the compound semiconductor material and an insulating layer positioned on the spacer layer. Minimum and maximum thicknesses of the spacer layer are determined by the penetration of the carrier wave function into the spacer layer and by the desired device performance. In a specific embodiment, the interface structure is formed in a multi-wafer epitaxial production system including a transfer and load module with a III-V growth chamber attached and an insulator chamber attached.

Abstract: A buffer layer with a composition of AlaGabIncN (a+b+c=1, a, b, c≧0) and a multilayered thin films with a composition of AlxGayInzN (x+y+z=1, x, y, z≧0) are formed in turn on a substrate. The Al component of the Al component-minimum portion of the buffer layer is set to be larger than that of at least the thickest layer of the multilayered thin films. The Al component of the buffer layer is decreased continuously or stepwise from the side of the substrate to the side of the multilayered thin films therein.

Abstract: There are contained the steps of forming a plurality of semiconductor elements on surface sides of a plurality of operational unit areas defined on a semiconductor substrate respectively, then connecting the semiconductor elements only in the operational unit areas by wirings, and then forming recesses from the back side of the semiconductor substrate in the situation that a connection layer for connecting mechanically the semiconductor elements only in the operational unit areas is formed on the surface side of the semiconductor substrate, whereby the semiconductor substrate is separated between the semiconductor elements. Accordingly, there is provided a method of manufacturing a semiconductor device having a plurality of semiconductor elements, that is capable of preventing electrical interference between a plurality of semiconductor elements that are connected mutually via wirings and also suppressing variation a width of a recess that separates respective semiconductor elements.

Abstract: A solid state pickup apparatus is described, which can weaken a dark current. The pickup apparatus includes an optical shield layer with a number of windows corresponding to the light receiving parts, and a negative voltage applying device. Each of the light receiving parts has a solid state pickup device where an P-type diode layer is formed between an N-type diode layer and a gate insulating layer. The negative voltage applying device is formed at the optical shield layer in order to apply a negative voltage to the P-type diode layer.

Abstract: A heterojunction bipolar transistor comprises a collector layer, a base layer, and an emitter layer stacked sequentially. The base layer comprises a first base layer joined to the collector layer in an inward base area directly below the emitter layer and a second base layer joined to the collector layer in an outward base area adjacent to the inward base area. The second base layer is formed of a semiconductor with a wider energy band gap than the collector layer.

Abstract: The invention relates to a semiconductor device with a diode. The semiconductor body (10) comprises a stack of a first semiconductor region provided with a first connection conductor (5) and a second semiconductor region (2) connected to a second connection conductor (6), wherein a rectifying junction is present between the two semiconductor regions (1, 2) having opposite conductivity types. Such a device is—after a rotation through 90 degrees—suitable for surface mounting. However, in particular at high voltage and/or high power levels, the diode may suffer from breakdown or a high leakage current.

Abstract: Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.

Abstract: A semiconductor device with a tunnel diode (23) is particularly suitable for various applications. Such a device comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types and having doping concentrations which are so high that breakdown between them leads to conduction by means of tunnelling. A disadvantage of the known device is that the current-voltage characteristic is not yet steep enough for some applications.

Abstract: A BICMOS integrated circuit is formed with CMOS transistors on an SOI substrate in a silicon layer having a standard thickness of 0.1 &mgr;m to 0.2 &mgr;m and with Bipolar SiGe transistors formed in an epitaxial layer nominally 0.5 &mgr;m thick. The CMOS transistors are formed first with standard processing, then covered with an insulating film. The insulating film is stripped in the bipolar areas and an epitaxial SiGe layer is deposited on the Si substrate. The bipolar transistors are formed using the SiGe epi layer for the base and having an encapsulated structure for device isolation using shallow isolation trenches and the buried oxide.

Abstract: A passivating layer is provided for a III-V semiconductor. The passivating layer is preferably made of Fe and is used with III-V (especially GaAs) devices. At least one full monolayer of the passivating layer is formed, so that one full monolayer of the passivating layer bonds with one full monolayer of the atomic species of the semiconductor.

Abstract: A light-emitting device using a vacuum doughnut to serve as a current blocking layer is disclosed. The light-emitting device comprises: a substrate of a first conductivity type; a buffer layer formed on the substrate; a double heterostructure layer comprising a first cladding layer, an active layer and a second cladding layer, formed on the buffer layer; and a cap layer of a second conductivity type formed on the double heterostructure layer. A vacuum doughnut is formed between the active layer and an electrode formed on the cap layer to block a current flowing from the electrode formed on the cap layer so that the current flows through a region of the double heterostructure layer that is uncovered by the electrode. Furthermore, the vacuum doughnut can also be formed in the second cladding layer instead of forming in the cap layer.

Abstract: A p-type semiconductor composed basically of an Ib-IIIb-VIb.sub.2 group compound semiconductor (especially CuInS.sub.2) which is improved in carrier concentration and has advantages in manufacture and performance. In order to obtain the p-type semiconductor mentioned above, p-type CuInS.sub.2 is formed by adding both P (p-type impurity) and Sn (n-type impurity) to CuInS.sub.2. The carrier concentration of the p-type semiconductor is 5.times.10.sup.17 cm.sup.-3 which is larger than the value (5.times.10.sup.16 cm.sup.-3) obtained when P and In are added or another value (3.times.10.sup.15 cm.sup.-3) obtained when only P is added. A thin film solar cell characterized by a glass substrate (2), an Mo electrode (1), a p-type semiconductor layer (3), an n-type semiconductor layer composed of a CdS layer (4), and an ITO electrode (5) is manufactured by using the CuInS.sub.2 layer containing P and Sn as the p-type semiconductor (3).

Abstract: The invention is to develop a high-speed low power consumption resonant tunneling element--a superlatticed negative-differential-resistance (NDR) functional transistor. The proposed element exhibits amplification and obvious NDR phenomena simultaneously. In this element, the emitter region includes 5-period GaInAs/AlInAs super lattice resonant tunneling and emitter layers. Since the emitter--base interface is of homojunction, the collector--emitter offset voltage (V.sub.CE, offset) may be lowered down significantly. In addition, the produced infinitesimal potential (.DELTA.Ev) at GaInAs/AlInAs interface due to heterojunction in discrete valence bands may be applied as barriers to prohibit holes flow from base towards emitter. By doing so, the base current is remarkably depressed so as to elevate efficiency of emitter injection as well as current gain.

Abstract: A semiconductor thin film comprises an n-type compound semiconductor layer including at least one element from each of groups Ib, IIIb, VIb and II. A solar cell using this semiconductor thin film comprises a substrate and a rear electrode, a p-type compound semiconductor layer, an n-type compound semiconductor layer, an n-type semiconductor layer, a window layer, and a transparent conductive film, formed in this order on the substrate. The n-type compound semiconductor layer including at least one element from each of groups Ib, IIIb, VIb and II has a high carrier density.

Abstract: The present invention provides, in one embodiment, a method of fabricating a heterostructure bipolar transistor. This particular embodiment comprises forming a n-type doped region in a semiconductor substrate to form a collector, epitaxially forming a base on the collector, epitaxially doping the base with indium while forming the base, and forming an emitter on the base. The base is epitaxially formed, and at the same time the base is doped with indium. In other words, the indium is epitaxially incorporated within the base as the base is being formed. In addition to the indium, the base may also be epitaxially doped with boron. Since, indium is incorporated into the base with the same epitaxial process used to form the base, the damage typically associated with conventional implantation processes are not present, and thus, the high annealing temperatures to repair the damage are not required. The base can be doped and formed at the same time; thereby, saving processing time.

Abstract: Silicon-germanium-based compositions comprising silicon, germanium, and carbon (i.e., Si--Ge--C), methods for growing Si--Ge--C epitaxial layer(s) on a substrate, etchants especially suitable for Si--Ge--C etch-stops, and novel methods of use for Si--Ge--C compositions are provided. In particular, the invention relates to Si--Ge--C compositions, especially for use as etch-stops and related processes and etchants useful for microelectronic and nanotechnology fabrication.

Abstract: The present invention relates to the fabrication of a boron carbide/boron diode on an aluminum substrate, and a boron carbide/boron junction field effect transistor. Our results suggest that with respect to the approximately 2 eV band gap pure boron material, 0.9 eV band gap boron carbide (B.sub.5 C) acts as a p-type material. Both boron and boron carbide (B.sub.5 C) thin films were fabricated from single source borane cage molecules using plasma enhanced chemical vapor deposition (PECVD). Epitaxial growth does not appear to be a requirement. We have doped boron carbide grown by plasma enhanced chemical vapor deposition. The source gas closo-1,2-dicarbadecaborane (orthocarborane) was used to grow the boron carbide while nickelocene (Ni(C.sub.5 H.sub.5)2) was used to introduce nickel into the growing film. The doping of nickel transformed a B.sub.5 C material p-type relative to lightly doped n-type silicon to an n-type material.

Abstract: A multiple peak resonant tunneling diode (10) includes multiple vertical semiconductor structures (12, 13). The vertical structures (12, 13) include a resonant tunneling diode having a predetermined cross-sectional area and a series resistor of a predetermined resistance. The vertical structures (12, 13) are spaced from one another and interconnected in parallel. Additionally, the vertical semiconductor structures (12, 13) are fabricated such that their predetermined diode cross-sectional areas and series resistances have values that vary by predetermined amounts to adjust the respective peak currents and/or peak voltages of the vertical semiconductor structures (12, 13).

Abstract: A semiconductor device of the present invention includes: an SiC substrate; an SiC growth layer for absorbing a grating defect of the SiC substrate and/or a damage at and in the vicinity of a surface of the SiC substrate; and Ga.sub.x Al.sub.y In.sub.1-x-y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) layer formed on the SiC growth layer.

Abstract: A semiconductor switching device is provided having a pn junction composed of a first semiconductor layer made of a first conductivity type semiconductor and a second semiconductor layer made of a second conductivity type semiconductor having a wider band-gap than that of the first semiconductor layer.

Abstract: Modulated-structure polycrystalline or heteroepitaxial multilayers of PZT/PT ferroelectric thin films are deposited on a substrate, preferably by laser ablation. The laser ablation of the PZT/PT layers onto a prepared substrate occurs while maintaining the substrate at a temperature between 380.degree. C. to about 650.degree. C. The target source for the PZT/PT laser ablated film may be either bulk PZT and PT ceramics or powders or individual metal oxides or metal pellets. The ferroelectric thin film device may be used for a random access memory.

Abstract: A semiconductor device comprises two adjacent semiconductor layers of different materials forming a heterojunction therebetween. A first layer has a larger gap between the conduction band and the valence band that a second layer at the interface between the layers. The second layer is made of SiC and the first layer is made of one of at least a) AlN and b) an alloy of AlN and other Group 3B-nitride.

Abstract: A semiconductor device includes a GaAs substrate having a lattice constant; and a III-V mixed crystal semiconductor layer disposed on the GaAs substrate, containing Tl (thallium) and Ga (gallium) as Group III elements and As (arsenic) as a Group V element, and having a lattice constant larger than the lattice constant of the GaAs substrate. Therefore, the lattice mismatch of the III-V mixed crystal semiconductor layer with GaAs and the band gap energy of the III-V mixed crystal semiconductor layer are smaller than those of an InGaAs layer, resulting in a semiconductor device with improved operating characteristics and reliability.