Abstract: A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than about 10 threading dislocations per square centimeter. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a “crosshatch free” surface.

Abstract: In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the active layer. A dielectric layer (TiO2 layer) of a stepwise laminate structure is formed on the AlGaN layer so that the electric field distribution between the gate Schottky electrode and the drain ohmic electrode is substantially uniformed. The dielectric constant of TiO2 of the dielectric layer is made higher than the dielectric constant of GaN and AlGaN of the active layer.

Abstract: A method for forming an epitaxial base layer in a bipolar device. The method comprises the steps of: providing a structure having a field isolation oxide region (12) adjacent to an active silicon region (10); forming a silicon nitride/silicon stack (14, 16) above the field isolation oxide region (12), wherein the silicon nitride/silicon stack (14, 16) includes a top layer of silicon (14) and a bottom layer of silicon nitride (16); performing an etch to the silicon nitride/silicon stack (14, 16) to form a stepped seed layer, wherein the top layer of silicon is etched laterally at the same time the bottom layer of silicon nitride is etched; and growing an Si/SiGe/Si stack (20) over the stepped seed layer and active region (10).

Abstract: A laser diode includes a first n-cladding layer disposed on and lattice-matched to an n-semiconductor substrate, wherein the first n-cladding layer is n-AlGaInP or n-GaInP; a second n-cladding layer of n-AlGaAs supported by the first n-cladding layer; and an inserted layer disposed between the first n-cladding layer and the second n-cladding layer, wherein the inserted layer includes the same elements as the first n-cladding layer, the inserted layer has the same composition ratios of Al and Ga (and P) as the first n-cladding layer, and the inserted layer contains a lower composition ratio of In than the first n-cladding layer.

Abstract: A method is provided of making a semiconductor wafer for a semiconductor junction diode device having a target forward voltage drop and a target reverse breakdown voltage. The method begins by doping a semiconductor substrate of a first conductivity type through the back surface with a first dopant of the first conductivity type in an amount sufficient to form a semiconductor junction diode device having a target forward voltage drop. Next, the substrate is doped through the front surface with a second dopant of the first conductivity type in an amount sufficient to form the semiconductor junction diode device such that it has a target reverse breakdown voltage.

Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/post. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, from a top surface of the post and a sidewall/sidewalls of the trench serving as a nucleus for epitaxial growth, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. As a result, a region having less threading dislocations is formed at the buried trench.

Abstract: The present invention relates to semiconductor electronic devices including molybdenum oxide formed on substrates which consist of materials which are used in known semiconductor electronic devices. The present invention relates to also a new method to fabricate said electronic devices on substrates made of materials which have been used in usual electronic and photonic devices. Suitable substrates consist of materials such as element semiconductors such as silicon and germanium, III-V compound semiconductors such as gallium arsenide and gallium phosphide, II-IV compound semiconductors such as zinc oxide, IV compound semiconductors, organic semiconductors, metal crystals and their derivatives or glasses.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A III-nitride based integrated semiconductor device which includes at least two III-nitride based semiconductor devices formed in a common die.

Abstract: An integrated circuit is provided with a photonic device and a spot-size converter waveguide device integrated on a common substrate. The spot-size converter waveguide device provides for transformation between a larger spot-size and a smaller spot-size corresponding to the photonic device. The spot-size converter waveguide device includes at least one of a bottom mirror and top mirror, which provide highly-reflective lower and upper cladding, respectively, for vertical confinement of light propagating through the waveguide device. The top mirror overlies opposing sidewalls of the spot-converter waveguide device, which provide highly-reflective sidewall cladding for lateral confinement of light propagating through the waveguide device. Advantageously, the highly-reflective lower cladding provided by the bottom mirror limits optical loss of the waveguide device. Similarly, the highly-reflective upper cladding and sidewall cladding provided by the top mirror limits optical loss of the waveguide device.

Abstract: An electronic device comprising a heterojunction, wherein the heterojunction comprises a blend comprising an electron donor and an electron acceptor; and wherein the blend is treated so as to form one or more linkages between the electron donor and/or electron acceptor in the treated blend.

Abstract: The heterostructures are used for creation of semiconductor injection emission sources: injection lasers, semiconductor amplifying elements, semiconductor optical amplifiers that are used in fiber optic communication and data transmission systems, in optical superhigh-speed computing and switching systems, in development of medical equipment, laser industrial equipment, frequency-doubled lasers, and for pumping solid-state and fiber lasers and amplifiers.

Abstract: A heterojunction structure composed of a p-type semiconductor thin film and n-type ZnO-based nanorods epitaxially grown thereon exhibits high luminescence efficiency property due to facilitated tunneling of electrons through the nano-sized junction and the use of ZnO having high exciton energy as a light emitting material, and thus it can be advantageously used in nano-devices such as LED, field effect transistor, photodetector, sensor, etc.

Abstract: There is provided a nitride semiconductor device with low leakage current and high efficiency in which, while a zinc oxide based compound such as MgxZn1-xO (0?x?0.5) is used for a substrate, crystallinity of nitride semiconductor grown thereon is improved and film separation or cracks are prevented. The nitride semiconductor device is formed by laminating nitride semiconductor layers on a substrate (1) made of a zinc oxide based compound such as MgxZn1-xO (0?x?0.5). The nitride semiconductor layers include a first nitride semiconductor layer (2) made of AlyGa1-yN (0.05?y?0.2) which is provided in contact with the substrate (1), and nitride semiconductor layers (3) to (5) laminated on the first nitride semiconductor layer (2) so as to form a semiconductor element.

Abstract: A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1-x)N and a range of x is given by 0<x<2, and a thickness of the GaN layer having indium is 50-200 ?.

Abstract: To provide a semiconductor device that has a sufficiently low on-resistance and excellent low-capacitance and high-speed characteristics as compared with conventional GaN-based diodes. The semiconductor device includes: a substrate (101); a buffer layer (102); a stack structure (103 and 104) including at least one heterojunction unit (103 and 104) that is a stack of a layer (GaN layer 103) made of a nitride semiconductor and a layer (AlGaN layer 104) made of another nitride semiconductor having a larger band gap than the nitride semiconductor (GaN layer 103); a Schottky electrode (106) that is placed at a first end of the stack structure (103 and 104) and forms a Schottky barrier contact with the heterojunction unit (103 and 104); and an ohmic electrode (107) that is placed at a second end of the stack structure (103 and 104) and forms an ohmic contact with the heterojunction unit (103 and 104).

Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

Abstract: Novel GaN/AlGaN metal-semiconductor field-effect transistor (MESFET) structures grown without any impurity doping in the channel. A high-mobility polarization-induced bulk channel charge is created by grading the channel region linearly from GaN to Al0.3Ga0.7N over a distance, e.g., 1000 ?. A polarization-doped field effect transistor (PolFET) was fabricated and tested under DC and RF conditions. A current density of 850 mA/mm and transconductance of 93 mS/mm was observed under DC conditions. Small-signal characterization of 0.7 ?m gate length devices had a cutoff frequency, f?=19 GHz, and a maximum oscillation of fmax=46 GHz. The PolFETs perform better than comparable MESFETs with impurity-doped channels, and are suitable for high microwave power applications. An important advantage of these devices over AlGaN/GaN HEMTs is that the transconductance vs. gate voltage profile can be tailored by compositional grading for better large-signal linearity.

Abstract: A semiconductor device of the invention includes a first conductive type semiconductor base substrate; and a switching mechanism which is formed on a first main surface of the semiconductor base substrate and switches ON/OFF of a current. In the semiconductor base substrate, a plurality of columnar hetero-semiconductor regions are formed at spaced intervals within the semiconductor substrate, and the hetero-semiconductor regions are made of a semiconductor material having a different band gap from the semiconductor substrate and extend between the first main surface and a second main surface opposite to the first main surface.

Abstract: A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.

Abstract: A heterostructure is provided which includes a substantially relaxed SiGe layer present atop an insulating region that is located on a substrate. The substantially relaxed SiGe layer has a thickness of from about 2000 nm or less, a measured lattice relaxation of from about 50 to about 80% and a defect density of less than about 108 defects/cm2. A strained epitaxial Si layer is located atop the substantially relaxed SiGe layer and at least one alternating stack including a bottom relaxed SiGe layer and an top strained Si layer located on the strained epitaxial Si layer.

Abstract: A semiconductor having a an n-type material and a p-type material, wherein the n-type material and p-type material are joined to form a space-charge-free p-n junction. The energy of the Fermi-level of the n-type material is equal to the energy of the Fermi-level of the p-type material. This allows for the pre-alignment of the Fermi-levels of the n-type and the p-type materials. The semiconductor has minimal or no g-r noise. The semiconductor can be operated at TBLIP in the range of about 220° to about 240° K.

Abstract: A high electron mobility transistor is disclosed which has a double-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. The main semiconductor region, buffer region, and part of the substrate taper as they extend away from the rest of the substrate, providing slanting side surfaces. An electroconductive antileakage overlay covers these side surfaces via an electrically insulating overlay. Electrically coupled to the silicon substrate via a contact electrode, the antileakage overlay serves for reduction of current leakage along the side surfaces.

Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.

Abstract: A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made to the inner carbon nanotube, and a gate contact is made to the outer carbon nanotube. The carbon nanotube based memory device is programmed by storing electrons or holes in the middle carbon nanotube through intershell electron transport. Changes in conductance of the inner carbon nanotube due to the charge in the middle shell are detected to determine the charge state of the middle carbon nanotube. Thus, the carbon nanotube based memory device stores information in the middle carbon nanotube in the form of electrical charge.

Abstract: A method of purifying small molecule organic material, performed as a series of operations beginning with a first sample of the organic small molecule material. The first step is to purify the organic small molecule material by thermal gradient sublimation. The second step is to test the purity of at least one sample from the purified organic small molecule material by spectroscopy. The third step is to repeat the first through third steps on the purified small molecule material if the spectroscopic testing reveals any peaks exceeding a threshold percentage of a magnitude of a characteristic peak of a target organic small molecule. The steps are performed at least twice. The threshold percentage is at most 10%. Preferably the threshold percentage is 5% and more preferably 2%. The threshold percentage may be selected based on the spectra of past samples that achieved target performance characteristics in finished devices.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A boron phosphide-based semiconductor device enhanced in properties includes a substrate (11) composed of a {111}-Si single crystal having a surface {111} crystal plane and a boron phosphide-based semiconductor layer formed on the surface of the substrate and composed of a polycrystal layer (12) that is an aggregate of a plurality of a triangular pyramidal single crystal entities (13) of the boron phosphide-based semiconductor crystal, where in each single crystal entity has a twining interface that forms an angle of 60° relative to a <110> crystal direction of the substrate.

Abstract: An avalanche photodiode according to this invention include a light receiving region 101 surrounded by a ring-shaped trench 13, a first electrode 11 formed on the light receiving region 101, a second electrode 12 formed on the periphery of the ring-shaped trench 13 surrounding the light receiving region, a first semiconductor layer lying just under the first electrode 11, and a second semiconductor layer lying just under the second electrode 12. Conductivity types of the first semiconductor and the second semiconductor are identical.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.

Abstract: The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility. The present invention further discloses a 3D-M with seamless 3D-ROM cells. Seamless 3D-ROM can ensure a better manufacturing yield.

Abstract: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 ?) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

Abstract: A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised polycrystalline silicon germanium (SiGe) anode. In another embodiment, the P-N junction device includes a first terminal (anode) including a conductor layer positioned above an upper surface of a substrate and a remaining structure positioned in the substrate, the first terminal positioned over an opening in an isolation region; and a second terminal (cathode contact) positioned over the opening in the isolation region adjacent the first terminal. This latter embodiment reduces parasitic resistance and capacitance, and decreases the required size of a cathode implant area since the cathode contact is within the same STI opening as the anode.

Abstract: Methods and systems for improving heteroepitaxial crystal quality of semiconductor materials include forming a pattern on the semiconductor substrate over which the hetero-epitaxial layer is grown. The pattern provides predetermined sites for dislocation initiation and termination of dislocation propagation. The layer may be treated with a focused laser beam during or subsequent to the layer growth process. Laser light may be focused at a selected depth, where the light intensity is sufficient to cause structural and/or electronic changes localized at that depth. The laser beam may be selectively scanned to provide the desired change only at preferred spatial locations on the substrate. The laser wavelength and power may be selected to be appropriate for the materials being treated.

Abstract: The insulated-gate field-effect transistor includes a substrate surmounted by a layer of silicon-germanium alloy, the ratio of the germanium concentration to the silicon concentration of which increases towards the surface of the substrate. The transistor is formed on the active zone in the silicon-germanium alloy layer and lies between two isolating zones. The transistor includes a narrow heterostructure strained-semiconductor channel including a SiGe alloy layer in compression and a silicon layer in tension, extending between the gate and a dielectric block buried in the substrate.

Abstract: An aspect of the present invention provides a semiconductor device that includes, a first semiconductor body of a first conductivity type, a first switching mechanism provided on the first semiconductor body, configured and arranged to switch on/off current flowing through the semiconductor device, and a first reverse-blocking heterojunction diode provided on the semiconductor body, configured and arranged to block current reverse to the current switched on/off by the first switching mechanism.

Abstract: Thermoelectric devices are provided. In one embodiment, a thermoelectric device may include a glass wafer defined by conductive vias, a second wafer, and a plurality of metal film disposed between the glass wafer and the second wafer and against solid, conductive, integral, end surfaces of the conductive vias. A nanogap may be disposed between the metal film and the second wafer. The nanogap may have been created by applying a voltage extending between the conductive vias and the second wafer. Methods of forming the devices, along with methods of using the devices to transform heat energy to electricity, and for refrigeration, are also provided.

Abstract: A semiconductor apparatus includes an electrostatic protective device having PN junction with N-type Si and P-type SiGe. The electrostatic protective device is directly connected with a terminal to receive static electricity and with a terminal to discharge static electricity.

Abstract: Methods of forming a semiconductor device include forming a protective layer on a semiconductor layer, implanting ions having a first conductivity type through the protective layer into the semiconductor layer to form an implanted region of the semiconductor layer, and annealing the semiconductor layer and the protective layer to activate the implanted ions. An opening is formed in the protective layer to expose the implanted region of the semiconductor layer, and an electrode is formed in the opening. A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact extending through the protective layer to the semiconductor layer.

Abstract: A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity.

Abstract: A semiconductor structure is disclosed that includes a silicon carbide wafer having a diameter of at least 100 mm with a Group III nitride heterostructure on the wafer that exhibits high uniformity in a number of characteristics. These include: a standard deviation in sheet resistivity across the wafer less than three percent; a standard deviation in electron mobility across the wafer of less than 1 percent; a standard deviation in carrier density across the wafer of no more than about 3.3 percent; and a standard deviation in conductivity across the wafer of about 2.5 percent.

Abstract: There is provided a method of producing a thin GaN film-joined substrate, including the steps of: joining on a GaN bulk crystalline body a substrate different in type or chemical composition from GaN; and dividing the GaN bulk crystalline body at a plane having a distance of at least 0.1 ?m and at most 100 ?m from an interface thereof with the substrate different in type, to provide a thin film of GaN on the substrate different in type, wherein the GaN bulk crystalline body had a surface joined to the substrate different in type, that has a maximum surface roughness Rmax of at most 20 ?m. Thus a GaN-based semiconductor device including a thin GaN film-joined substrate including a substrate different in type and a thin film of GaN joined firmly on the substrate different in type, and at least one GaN-based semiconductor layer deposited on the thin film of GaN, can be fabricated at low cost.

Abstract: A laser diode includes a first n-cladding layer disposed on and lattice-matched to an n-semiconductor substrate, wherein the first n-cladding layer is n-AlGaInP or n-GaInP; a second n-cladding layer of n-AlGaAs supported by the first n-cladding layer; and an inserted layer disposed between the first n-cladding layer and the second n-cladding layer, wherein the inserted layer includes the same elements as the first n-cladding layer, the inserted layer has the same composition ratios of Al and Ga (and P) as the first n-cladding layer, and the inserted layer contains a lower composition ratio of In than the first n-cladding layer.

Abstract: A composite structure having a silicon carbide epitaxial layer is provided. The epitaxial layer includes at least four regions arranged vertically and defining respective interfaces, where each of the regions is characterized by a respective impurity concentration, where the impurity concentrations vary across each of the interfaces, and where each of the impurity concentrations exceeds 1×1017 cm?3 for at least one single impurity in all of the regions.

Abstract: A device having an electrode-insulator layer-group III nitride layer structure, wherein an interface between the insulator layer and the group III nitride semiconductor layer lies along a non-polar plane of the group III nitride semiconductor layer is provided.

Abstract: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.

Abstract: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: Gallium nitride material-based semiconductor structures are provided. In some embodiments, the structures include a composite substrate over which a gallium nitride material region is formed. The gallium nitride material structures may include additional features, such as strain-absorbing layers and/or transition layers, which also promote favorable stress conditions. The reduction in stresses may reduce defect formation and cracking in the gallium nitride material region, as well as reducing warpage of the overall structure. The gallium nitride material-based semiconductor structures may be used in a variety of applications such as transistors (e.g. FETs) Schottky diodes, light emitting diodes, laser diodes, SAW devices, and sensors, amongst others devices.

Abstract: A practically realizable semiconductor magnetic body having a flat-band structure is disclosed. The semiconductor magnetic body is formed by semiconductor quantum dots arranged on lattice points such that electrons can transfer between neighboring quantum dots and the electron energy band contains a flat-band structure, where each quantum dot is a structure in which electrons are confined inside a region which is surrounded by high energy potential regions, and the flat-band structure is a band structure in which energy dispersion of electrons has hardly any wave number dependency.