Abstract: Semiconductor devices are provided which have MIM (metal-insulator-metal) capacitor structures that are integrated within air gaps of on-chip interconnect structures, as well as methods for integrating MIM capacitor formation as part of an air gap process flow for fabricating on-chip interconnect structures. For example, a semiconductor device includes a dielectric layer with a first pattern of metal lines and second pattern of metal lines. Air gaps are disposed in spaces between the metal lines. Portions of the spaces between the metal lines of the first pattern of metal lines include a conformal layer of insulating material disposed on sidewalls of the metal lines and metallic material that fills the spaces between the metal lines. The first pattern of metal lines comprises a first capacitor electrode, the metallic fill material comprises a second capacitor electrode, and the conformal layer of insulating material comprises an insulating layer of a MIM capacitor structure.

Abstract: A memory device includes a peripheral circuit portion and an array portion disposed on the peripheral circuit portion. The array portion includes a bottom conductive layer; an isolation layer disposed on the bottom conductive layer; a semiconductor substrate disposed on the isolation layer; a channel layer disposed on a sidewall of a first through opening which exposes the semiconductor substrate and electrically contacting the semiconductor substrate; a memory layer; and a multilayers stack disposed on the semiconductor substrate. The multilayers stack includes a first insulating layer disposed on the semiconductor substrate; a first conductive layer disposed on the first insulating layer; second insulating layers disposed over the first insulating layer; and second conductive layers alternatively stacked with the second insulating layers and insulated from the first conductive layer.

Abstract: According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.

Abstract: A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

Abstract: A semiconductor memory device includes a stacked body including a plurality of word lines; a semiconductor layer extending through the word lines; a memory cell provided at a part where the semiconductor layer crosses one of the word lines, the memory cell including a plurality of cell layers, the cell layers including a first insulating layer; and at least one of a first structural body and a second structural body provided around the stacked body. The first structural body includes a plurality of monitor layers including same materials respectively as materials of the cell layers. The second structural body includes a first electrode, a second electrode and an insulating body positioned between the first electrode and the second electrode. The insulating body includes same material as a material of the first insulating layer, and has almost the same thickness as a thickness of the first insulating layer.

Abstract: An integrated circuit (IC) and a mobile device are provided. The IC includes a memory cell that includes a word line, a bit line pair, and a storage cell connected to the word line and the bit line pair. The IC further includes a timing control circuit configured to generate switch signals based on an operation control signal, and a switch circuit configured to receive a first voltage, a second voltage and a third voltage having different levels, and output, to the word line, one among the first voltage, the second voltage, and the third voltage based on the switch signals.

Abstract: According to the embodiment, a semiconductor device includes: a stacked body; a columnar portion, an insulating portion; and wall portion. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion is provided in the stacked body and extends in a staking direction of the stacked body. The insulating portion is provided around the stacked body and surrounds the stacked body. The wall portion is provided in the insulating portion and is separated from the stacked body. The wall portion extends in the stacking direction and in a first direction crossing the stacking direction.

Abstract: A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. The semiconductor device may include a source side channel layer and a drain side channel layer extended from the pipe channel layer to protrude further than the oxidization layer.

Abstract: A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film.

Abstract: A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.

Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

Abstract: A semiconductor device may include the following elements: a semiconductor substrate, an insulator positioned on the substrate, a source electrode positioned on the insulator, a drain electrode positioned on the insulator, a gate electrode positioned between the source electrode and the drain electrode, a hollow channel surrounded by the gate electrode and positioned between the source electrode and the drain electrode, a dielectric member positioned between the hollow channel and the gate electrode, a first insulating member positioned between the gate electrode and the source electrode, and a second insulating member positioned between the gate electrode and the drain electrode.

Abstract: According to one embodiment, a semiconductor device includes a substrate; a first structure; a second structure; a step; an insulating layer; a first pillar; a second pillar; a first contact portion; and a second contact. The first structure includes a first electrode layer and a first insulator. The first structure has a first terrace on a surface of the first insulator. The second structure includes a second electrode layer and a second insulator. The second structure has a second terrace on a surface of the second insulator. The second contact portion is electrically connected to the second electrode layer via the second terrace. The first contact portion is located between the step and the first pillar. The step is located between the first contact portion and the second pillar.

Abstract: The present disclosure may provide a memory device including a page buffer and bit-lines coupled thereto with a less load of the bit-lines. In one aspect of the present disclosure, there is provided a memory device comprising: bit-lines, each bit-line having opposite first and second ends; plugs coupled respectively to the bit-lines, each plug disposed between and excluding the first and second ends; and a page buffer coupled to the plugs.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, columnar portions, and first and second interconnection portions. The stacked body includes insulating layers and electrode layers alternately stacked one layer by one layer on the substrate. The columnar portions are provided between the first and second interconnection portions and include a first row having a first columnar portion and a second row having a second columnar portion, the first columnar portion being positioned closest to the first interconnection portion, and the second columnar portion being positioned closest to the second interconnection portion. A distance between the first interconnection portion and the first columnar portion is smaller than a distance between the second interconnection portion and the second columnar portion, and the distance between the second interconnection portion and the second columnar portion is greater than 20 nanometers.

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

Abstract: Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the first direction, and elongated metal contacts with longitudinal axes that lie a second direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie the second direction, where the second direction lies orthogonal to the first direction.

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.

Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.

Abstract: A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride layer, a gate oxide layer, a gate, a P-body region, a source region, an interlayer dielectric and a source electrode. The epitaxial layer on the substrate has a trench having a sidewall and a bottom. The electrode inside the trench is coated subsequently by the surrounding-oxide layer, the surrounding-nitride layer and the remnant-oxide layer. The gate formed on the gate oxide layer is separated from the electrode sequentially by the gate oxide layer, the surrounding-nitride layer and the surrounding-oxide layer. The P-body region and the source region, formed at the epitaxial layer, are separated from the gate by the gate oxide layer. The interlayer dielectric covers the source region and the gate. The source electrode covers the P-body region and the interlayer dielectric, and contacts the source region.

Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.

Abstract: Contact areas for three-dimensional memory devices including multiple vertically stacked tier structures can be reduced by overlapping stepped terraces of the tier structures. Sacrificial via structures laterally surrounded by a respective insulating spacer can be formed through an overlying tier structure in the stepped terrace region thereof. After formation of memory stack structures, the sacrificial via structures can be removed to provide first upper via cavities. An isotropic etch can be performed to extend the first upper via cavities to top surfaces of underlying first electrically conductive layers in an underlying tier structure while forming second upper via cavities extending to second electrically conductive layers in the overlying tier structure.

Abstract: An embodiment of a method of forming a portion of a memory array includes forming a conductor with a concentration of germanium that decreases with an increasing thickness of the conductor, removing a portion of the conductor at a rate governed by the concentration of germanium to form a tapered first opening through the conductor, removing a sacrificial material below the conductor to form a second opening contiguous with the tapered first opening, and forming a semiconductor in the contiguous first and second openings, wherein a portion of the semiconductor pinches off within the first opening adjacent an upper surface of the conductor before the contiguous first and second openings are completely filled with the semiconductor.

Abstract: A semiconductor device is manufactured by: i) forming a mask on a process surface of a semiconductor layer, elongated openings of the mask exposing part of the semiconductor layer and extending along a first lateral direction; ii) implanting dopants of a first conductivity type into the semiconductor layer based on tilt angle ?1 between an ion beam direction and a process surface normal and based on twist angle ?1 between the first lateral direction and a projection of the ion beam direction on the process surface; iii) implanting dopants of a second conductivity type into the semiconductor layer based on tilt angle ?2 between an ion beam direction and the process surface normal and based on twist angle ?2 between the first lateral direction and a projection of the ion beam direction on the process surface; and repeating i) to iii) at least one time.

Abstract: An electronically programmable read-only memory (EPROM) cell includes a semiconductor substrate having source and drain regions; a floating gate, adjacent to the source and drain regions and separated from the semiconductor substrate by a first dielectric layer, the floating gate including: a polysilicon layer formed over the first dielectric layer; a first metal layer electrically connected to the polysilicon layer, where the surface area of the first metal layer is less than 1000 ?m2; and a control gate comprising a second metal layer, capacitively coupled to the first metal layer through a second dielectric material disposed therebetween.

Abstract: A three-dimensional memory array device can include mid-plane terrace regions between a pair of memory array regions. The electrically conductive layers of the three-dimensional memory array device continuously extend between the pair of memory array regions through a connection region, which is provided adjacent to the mid-plane terrace regions. Contact via structures contacting the electrically conductive layers can be provided in the mid-plane terrace regions, and through-memory-level via structures that extend through the alternating stack and connected to underlying lower metal interconnect structures and semiconductor devices can be provided through the mid-plane terrace region and/or through the connection region. Upper metal interconnect structures can connect the contact via structures and the through-memory-level via structures.

Abstract: To reduce a manufacturing cost of a semiconductor device in which a high breakdown voltage transistor and a trench capacitive element in which a part of an upper electrode is embedded in a trench formed in a main surface of a semiconductor substrate are mixed together. After an insulating film is formed over a main surface of a semiconductor substrate so as to cover a trench formed in the main surface of the semiconductor substrate, the insulating film is processed to form an upper electrode of a capacitive element, a gate insulating film which insulates the semiconductor substrate to be a lower electrode, and a gate insulting film of a high breakdown voltage transistor.

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.

Abstract: A nonvolatile semiconductor storage device includes a memory string including a plurality of memory cells connected in series with each other, and a select gate transistor connected to a first end of the memory string. The film thickness of a first hard mask on a select gate electrode of the select gate transistor is greater than the film thickness of a second hard mask film on a control gate electrode of the memory cells. The level of an upper surface of a first side wall insulating film provided on a side surface of the select gate transistor is higher than the level of an upper surface of the first hard mask film. The level of an upper surface of a second side wall insulating film provided on a side surface of the memory cells is higher than the level of an upper surface of the second hard mask film.

Abstract: The present disclosure relates to a flash memory cell. In some embodiments, the flash memory cell has a control gate arranged over a substrate, and a select gate separated from the substrate by a gate dielectric layer. A charge trapping layer has a first portion disposed between the select gate and the control gate, and a second portion arranged under the control gate. A first control gate spacer is arranged on the second portion of the charge trapping layer. A second control gate spacer is arranged on the second portion of the charge trapping layer and is separated from the control gate by the first control gate spacer.

Abstract: Disclosed herein is a solid-state imaging apparatus including: a semiconductor base; a photodiode created on the semiconductor base and used for carrying out photoelectric conversion; a pixel section provided with pixels each having the photodiode; a first wire created by being electrically connected to the semiconductor base for the pixel section through a contact section and being extended in a first direction to the outside of the pixel section; a second wire made from a wiring layer different from the first wire and created by being extended in a second direction different from the first direction to the outside of the pixel section; and a contact section for electrically connecting the first and second wires to each other.

Abstract: A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop.

Abstract: A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage.

Abstract: One embodiment includes a plurality of memory cells and a plurality of conducting layers. The memory cells are three-dimensionally disposed on a semiconductor substrate. The conducting layers are disposed in a laminating direction. Each of the plurality of the conducting layers is connected to each of the plurality of the memory cells. Each conducting layer has a structure where a first conductive film and a second conductive film are laminated in the laminating direction. The conducting layers adjacent to one another in the laminating direction have a laminating order of the first conductive film and the second conductive film different from one another.

Abstract: Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

Abstract: A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.

Abstract: A semiconductor integrated circuit device may include a structure, a first capping layer, a channel layer and a second capping layer. The structure may have an opening formed in the structure. The first capping layer may be formed in the opening of the structure. The channel layer may be arranged between the structure and the first capping layer. The second capping layer may be arranged on the channel layer and the first capping layer.

Abstract: According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

Abstract: Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

Abstract: A surface area of a transverse cross section of an upper portion of a columnar portion is greater than a surface area of a transverse cross section of a lower portion of the columnar portion. A configuration of the transverse cross section of the upper portion is a triangle or a pseudo-triangle having three corners, or a quadrilateral or a pseudo-quadrilateral having four corners. A configuration of the transverse cross section of the lower portion is substantially a circle. The upper portion of the columnar portion is adjacent to an upper layer portion of a stacked body including a control gate of an uppermost layer of control gates. The lower portion of the columnar portion is adjacent to a lower layer portion of the stacked body including a control gate of a lowermost layer of the control gates.

Abstract: A memory including a common floating gate structure in simultaneous electrical communication with a first fin structure of a first conductivity type vertically orientated semiconductor device and a second fin structure of a second conductivity type vertically orientated semiconductor device. A back bias electrode is present between the first and second fin structures embedded in a dielectric material positioned in a central portion of the common floating gate structure. The back bias electrode is present overlying an isolation region that is separating a first region of the substrate including the first conductivity type vertically orientated semiconductor device from a second region of the substrate including the second conductivity type vertically orientated semiconductor device.

Abstract: There are provided a memory device and a manufacturing method thereof. A method of manufacturing a memory device may include forming, on a substrate, a conductive layer, a sacrificial layer, and a stack structure. The method may include forming a plurality of vertical holes by etching a portion of the stack structure. The method may include forming a memory layer and a channel layer along internal surfaces of the vertical holes. The method may include forming a slit trench exposing a portion of the sacrificial layer therethrough by etching a portion of the stack structure between the vertical holes. The method may include exposing a portion of the channel layer and the first conductive layer through a lower portion of the stack structure by removing portions of the sacrificial layer and the memory layer. The method may include forming another conductive layer along surfaces of the exposed portion of the channel layer and the first conductive layer.

Abstract: A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

Abstract: A semiconductor device may be provided. The semiconductor device may include conductive patterns surrounding a channel film. The conductive patterns may be stacked and spaced apart from one another. The semiconductor device may include a gate contact plug coupled to one of the conductive patterns. The semiconductor device may include support pillars penetrating the conductive patterns in a periphery of the gate contact plug.

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract: Provided herein is a semiconductor device. The semiconductor device includes: a lower conductive pattern; a lower memory string conductive pattern disposed over the lower conductive pattern; a stack of upper memory string conductive patterns, wherein the stack is disposed over the lower memory string conductive pattern; a lower pad pattern extending from the lower memory string conductive pattern; upper pad patterns respectively extending from the upper memory string conductive patterns; a floating conductive pattern disposed under below the lower pad pattern, the floating conductive pattern overlapping the lower pad pattern; and a contact plug coming into contact with the lower pad pattern and overlapping the floating conductive pattern.

Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.

Abstract: Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of an active pillar that may be formed of a semiconductor material having a charge mobility greater than a charge mobility of silicon. The semiconductor devices may also include a non-channel portion of the active pillar including a semiconductor material having a high silicon content.

Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.