Abstract: A MOSFET device has a funnel-shaped trench etched in a semiconductor substrate. The funnel-shaped trench has flared rim extending from a wider cross section trench mouth at the surface of the semiconductor substrate to a narrower cross section trench body portion which terminates in an epilayer portion of the semiconductor substrate. A gate electrode is disposed in the trench on the flared rim. Source and gate regions of the device abut upper and lower portions of the flared rim, respectively. A drain region of the device, which abuts the narrower cross section trench body portion, is self-aligned with a lower edge of a gate electrode.

Abstract: One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3.

Abstract: Chip packages having power management integrated circuits are described. Power management integrated circuits can be combined with on-chip passive devices, and can provide voltage regulation, voltage conversion, dynamic voltage scaling, and battery management or charging. The on-chip passive devices can include inductors, capacitors, or resistors. Power management using a built-in voltage regulator or converter can provide for immediate adjustment of the voltage range to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices. Related fabrication techniques are described.

Abstract: A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region.

Abstract: Disclosed is a semiconductor component, including: a drift zone arranged between a first and a second connection zone; a channel control layer of an amorphous semi-insulating material arranged adjacent to the drift zone.

Abstract: The present invention discloses a high-voltage ESD protection device including a silicon controlled rectifier and a first PNP transistor. The silicon controlled rectifier includes a high-voltage P-well and N-well; a first N+ and P+ diffusion region are formed in the high-voltage P-well; a second N+ and P+ diffusion region are formed in the high-voltage N-well. The first PNP transistor comprises an N-type buried layer; a low-voltage N-well formed in the N-type buried layer; and a base, emitter and collector formed in the low-voltage N-well. The base and emitter are shorted together; the collector is shorted to the second N+ diffusion region and the second P+ diffusion region; the first N+ diffusion region is shorted to the first P+ diffusion region to act as a ground terminal. The high-voltage ESD protection device can effectively adjust the ESD trigger voltage and improve the snapback sustaining voltage after the device is switched on.

Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

Abstract: A high voltage (HV) semiconductor device includes: a semiconductor substrate having a first conductivity type; a gate structure disposed over a portion of the semiconductor substrate; a pair of spacers respectively disposed over a sidewall of the gate structure, wherein one of the spacers is a composite spacer comprising a first insulating spacer contacting the gate structure, a dummy gate structure, and a second insulating spacer; a first drift region disposed in a portion of the semiconductor, underlying a portion of the gate structure and one of the pair of spacers, having a second conductivity type opposite to the first conductivity type; and a pair of doping regions, respectively disposed in a portion of the semiconductor substrate on opposite sides of the gate structure, wherein the pair of doping regions include the second conductivity type and one of the doping regions is disposed in the first drift region.

Abstract: A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.

Abstract: A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.

Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.

Abstract: An approach for providing bit cells with triple patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process of a metal layer, a first structure that is a first one of a word line structure, a ground line structure, a power line structure, and a bit line structure; providing, via a second patterning process of the metal layer, a second structure that is different from the first structure and that is a second one of the word line structure, the ground line structure, the power line structure, and the bit line structure; and providing, via a third patterning process of the metal layer, a third structure that is different from the first structure and the second structure, and that is a third one of the word line structure, the ground line structure line, the power line structure, and the bit line structure.

Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.

Abstract: An object to provide a material suitably used for used for a semiconductor included in a transistor, a diode, or the like, with the use of a sputtering method. Specifically, an object is to provide a manufacturing process an oxide semiconductor film having high crystallinity. By intentionally adding nitrogen to the oxide semiconductor, an oxide semiconductor film having a wurtzite crystal structure that is a hexagonal crystal structure is formed. In the oxide semiconductor film, the crystallinity of a region containing nitrogen is higher than that of a region hardly containing nitrogen or a region to which nitrogen is not intentionally added. The oxide semiconductor film having high crystallinity and having a wurtzite crystal structure is used as a channel formation region of a transistor.

Abstract: A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.

Abstract: A semiconductor device includes a substrate, and a gate electrode formed on the substrate on a gate insulation film. The semiconductor device also includes a source diffusion layer and a drain diffusion layer which are formed on the substrate where the gate electrode is sandwiched between the source diffusion layer and the drain diffusion layer, one or more source contacts formed on the source diffusion layer; and one or more drain contacts formed on the drain diffusion layer. At least one of the source contacts and the drain contacts includes a first contact region having a first size and a second contact region having a second size larger than the first size on the same source diffusion layer or on the same drain diffusion layer.

Abstract: A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.

Abstract: A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.

Abstract: A high voltage high side DMOS removing the N-buried layer from the DMOS bottom provides lower Ron*A at given breakdown voltage. The high voltage high side DMOS has a P-type substrate, an epitaxial layer, a field oxide, an N-type well region a gate oxide, a gate poly, a P-type base region, a deep P-type region, an N-type lightly doped well region, a first N-type highly doped region, a second N-type highly doped region and a P-type highly doped region.

Abstract: A power semiconductor device includes: a first semiconductor layer; second and third semiconductor layers above and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; and plural fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layer. An array period of the fourth semiconductor layers is larger than that of the second semiconductor layer. A thickness of part of the gate insulating film in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of part of the gate insulating film in an immediate upper region of the fourth semiconductor layers. Sheet impurity concentrations of the second and third semiconductor layers in the central portion are higher than a sheet impurity concentration of the third semiconductor layer in an immediately lower region of the fourth semiconductor layers.

Abstract: A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a raised drain structure above and in contact with the second well and separate from the gate structure. The raised drain structure includes a drain connection point above the surface of the second well.

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation.

Abstract: A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region.

Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

Abstract: The present invention discloses a double diffused drain metal oxide semiconductor (DDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes: a drift region, a gate, a source, a drain, a dielectric layer, and a conductive layer. The drift region includes a first region and a second region. The gate is formed on the substrate, and overlaps the first region from top view. The source and drain are formed at both sides of the gate respectively, and the drain is located in the second region. The drain and the gate are separated by a portion of the second region from top view. The dielectric layer is formed by dielectric material on the gate and the second region. The conductive layer is formed by conductive material on the dielectric layer, and overlaps at least part of the second region from top view.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a well of a substrate. The high voltage device includes: a field oxide region; a gate, which is formed on a surface of the substrate, and part of the gate is located above the field oxide region; a source and a drain, which are formed at two sides of the gate respectively; and a first low concentration doped region, which is formed beneath the gate and has an impurity concentration which is lower than that of the well surrounded, wherein from top view, the first low concentration doped region has an area within the gate and not larger than an area of the gate, and the first low concentration doped region has a depth which is deeper than that of the source and drain.

Abstract: A Lateral Double Diffused Metal-Oxide-Semiconductor (LDMOS) semiconductor device includes a substrate; a gate region, a source region, and a drain region on and/or over the substrate, a well region at one side of the drain region, and a guardring region disposed at one side of the well region and connected electrically to the well region.

Abstract: The semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate; and a first area and a second area which are respectively provided on the semiconductor substrate. The first area includes: a first metal wiring formed in a first wiring layer above the semiconductor substrate and having a certain first width; a second metal wiring formed in a second wiring layer located in an upper layer of the first wiring layer and having the first width; and a first contact connecting the first metal wiring and the second metal wiring and having a second width equal to or less than the first width. The second area includes a third metal wiring having a film thickness from the first wiring layer to the second wiring layer and having a certain third width.

Abstract: In aspects of the invention, an n-type epitaxial layer that forms an n? type drift layer is formed on the upper surface of an n-type semiconductor substrate formed by being doped with a high concentration of antimony. A p-type anode layer is formed on a surface of the n? type drift layer. An n-type contact layer is formed with an impurity concentration in the same region as the impurity concentration of the n-type cathode layer, or higher than the impurity concentration of the n-type cathode layer, on the lower surface of the n-type cathode layer. A cathode electrode is formed so as to be in contact with the n-type contact layer. The n-type contact layer is doped with phosphorus and, without allowing complete recrystallization using a low temperature heat treatment of 500° C. or less, lattice defects are allowed to remain.

Abstract: The present technology discloses a U-shape RESURF MOSFET device. Wherein the MOSFET device comprises a drain having a drain contact region and a drift region, a source, a body, a gate and a recessed-FOX structure. Wherein the recessed-FOX structure is between the gate and the drift region vertically and between the body and the drain contact region laterally, and wherein the recessed-FOX structure is configured to make the drift region into a U shape. The present technology further discloses the depth of the drift region is controlled by adjusting a layout width.

Abstract: A high voltage high side DMOS removing the N-buried layer from the DMOS bottom provides lower Ron*A at given breakdown voltage. The high voltage high side DMOS has a P-type substrate, an epitaxial layer, a field oxide, an N-type well region a gate oxide, a gate poly, a P-type base region, a deep P-type region, an N-type lightly doped well region, a first N-type highly doped region, a second N-type highly doped region and a P-type highly doped region.

Abstract: A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end portion thereof extending over the isolation layer.

Abstract: A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.

Abstract: Mutual triggering of electrostatic discharge (ESD) fingers is improved by creating a base contact in each individual finger and connecting all of these base contacts in parallel. The local base contact in each ESD finger is located at a position where the base voltage significantly increases when the ESD current increases. Thus when an ESD finger is triggered its local base voltage will tend to significantly increase. Since all of the ESD finger bases are connected in parallel this local voltage increase will forward bias the base-emitter junctions of the other ESD fingers, thus triggering them all. By sharing the triggering current from the fastest ESD finger with the slower ones ensures that all ESD fingers are triggered during an ESD event.

Abstract: A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface of a substrate between the gate electrode and the high impurity concentration drain layer so as to surround the high impurity concentration drain layer. When a parasitic bipolar transistor is turned on by an abnormal surge, electrons travel from a source electrode to a drain electrode. Here, electrons travel dispersed in the manner to avoid a vicinity X of the surface of the substrate and travel through a deeper path to the drain electrode as indicated by arrows in FIG. 4.

Abstract: A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.

Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics.

Abstract: A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.

Abstract: A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.

Abstract: Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self-aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate.

Abstract: A semiconductor device is provided. The device includes a semiconductor substrate and a gate structure thereon. A well region is formed in the semiconductor substrate. A drain region and a source region are respectively formed in the semiconductor substrate inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. The semiconductor substrate and the first heavily doped region have a first conductivity type and the well region and the second heavily doped region have a second conductivity type. A method for fabricating a semiconductor device is also disclosed.

Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed thereon is disclosed. A well region of a second conductivity type is formed in the epitaxial structure and the semiconductor substrate. A drain region and a source region are respectively formed in the epitaxial structure inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions of the first and second conductivity type, respectively, are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. A gate structure is disposed on the epitaxial structure. A method for fabricating a semiconductor device is also disclosed.

Abstract: A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.

Abstract: A semiconductor device includes a first conduction-type semiconductor substrate, a first semiconductor region of a first conduction-type formed on the semiconductor substrate, a second semiconductor region of a second conduction-type formed on a surface of the first semiconductor region, a third semiconductor region of the second conduction-type formed to be separated from the second semiconductor region on the surface of the first semiconductor region, a fourth semiconductor region of the second conduction-type formed to be separated from the second semiconductor region and the third semiconductor region on the surface of the first semiconductor region, and a first electrode connected to the second semiconductor region and the third semiconductor region.

Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.

Abstract: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Abstract: An LDMOS device includes a gate which is formed on and/over over a substrate; a source and a drain which are arranged to be separated from each other on both sides of the substrate with the gate interposed therebetween; and a field oxide film formed to have a step between the gate and the drain. The LDMOS device further includes a drift region formed of first conduction type impurity ions between the gate and the drain in the substrate; and at least one internal field ring formed in the drift region by selectively implanting a second conduction type impurity in accordance with the step of the field oxide film.