Abstract: A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in one or more source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array.

Abstract: A semiconductor device includes a semiconductor layer, a plurality of first doped regions, a gate structure, and second and third doped regions. The semiconductor layer has a first conductivity type. The first doped regions are in parallel disposed in a portion of the semiconductor layer along a first direction and have a second conductivity type and a rectangular top view. The gate structure is disposed over a portion of the semiconductor layer along a second direction, covering a portion of the first doped regions. The second doped region is disposed in the semiconductor layer along the second direction, being adjacent to a first side of the gate structure and having the second conductivity type. The third doped region is formed in the semiconductor layer along the second direction, being adjacent to a second side of the gate structure opposing the first side and having the second conductivity type.

Abstract: A super junction semiconductor device includes a semiconductor portion with parallel first and second surfaces. An impurity layer of a first conductivity type is formed in the semiconductor portion. Between the first surface and the impurity layer a super junction structure includes first columns of the first conductivity type and second columns of a second conductivity type. A sign of a compensation rate between the first and second columns may change along a vertical extension of the columns perpendicular to the first surface. A body zone of the second conductivity type is formed between the first surface and one of the second columns. A field extension zone of the second conductivity type may be electrically connected to the body zone or a field extension zone of the first conductivity type may be connected to the impurity layer. The field extension zone improves the avalanche characteristics of the semiconductor device.

Abstract: A slotted gate power transistor is a lateral power device including a substrate, a gate dielectric formed over the substrate, a channel region in the substrate below the gate dielectric and gate electrode layer formed over the gate dielectric. The gate electrode layer overlaps the gate dielectric above the channel region, an accumulation region, and a drift region below an oxide filled shallow trench isolation (or STI) or locally oxidized silicon (LOCOS) region. The slotted gate power transistor includes one or more slots or openings on the gate electrode layer over the accumulation region. Electrical connectivity is maintained over the entire gate electrode layer without external wiring.

Abstract: An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first semiconductor region, a second semiconductor region, a dielectric structure and a gate electrode layer. The first semiconductor region has a first type conductivity. The second semiconductor region has a second type conductivity opposite to the first type conductivity. The first semiconductor region is adjoined to the second semiconductor region. The dielectric structure is on the first semiconductor region and the second semiconductor region. The gate electrode layer is on the dielectric structure.

Abstract: A static electricity preventing circuit and a display device including the same are disclosed. In one aspect, the static electricity preventing circuit includes a power source voltage supply unit configured to apply a power source voltage to drive a display panel, wherein the display panel comprises a plurality of pixels respectively displaying images through light emission according to data voltages of image data signals. It also includes a signal wire unit configured to transmit lighting test signals for a lighting test of the pixels included in the display panel. It further includes a resistor unit positioned between the power source voltage supply unit and the signal wire unit and configured to discharge static electricity generated in the signal wire unit through the power source voltage supply unit.

Abstract: A power semiconductor device includes a semiconductor body having a first surface and including an active area including n-type semiconductor regions and p-type semiconductor regions, the n-type semiconductor regions alternating, in a direction substantially parallel to the first surface, with the p-type semiconductor regions. The semiconductor body further includes a peripheral area surrounding the active area and including a low-doped semiconductor region having a first concentration of n-dopants lower than a doping concentration of n-dopants of the n-type semiconductor regions, and at least one auxiliary semiconductor region having a concentration of n-dopants higher than the first concentration and a concentration of p-dopants higher than the first concentration.

Abstract: An integrated circuit includes a diode/bipolar ESD protection device. The diode/bipolar ESD device includes at least one gate separated ESD diode and at least one gate spaced ESD bipolar transistor coupled in parallel between a fixed voltage and an input/output pin.

Abstract: Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of silicon fins on a substrate layer, separated by a space, wherein adjacent silicon fins are separated by a trench; forming an oxide layer on the substrate layer and filling a portion of each trench; forming two deep isolation trenches into the oxide layer and the substrate layer adjacent to the two pluralities of silicon fins; forming a graded voltage junction by implanting a dopant into the substrate layer below the two pluralities of silicon fins; forming a gate structure on the oxide layer and between the two pluralities of silicon fins; implanting a dopant into and under the two pluralities of silicon fins, forming source and drain regions; and forming an epitaxial layer onto the two pluralities of silicon fins to form merged source and drain fins.

Abstract: A semiconductor device includes a semiconductor layer formed over a semiconductor substrate. A well region is disposed in a portion of the semiconductor layer, and a plurality of first doped regions is disposed in various portions of the well region. A second doped region is disposed in a portion of the well region. An isolation element is disposed in a portion of the top-most one of the first doped regions, and a third doped region is disposed in a portion of the top-most one of the first doped regions. A fourth doped region is disposed in a portion of the second doped region. An insulating layer overlies the third doped region, the isolation element, the second doped region, and the fourth doped region, and a conductive layer overlies the insulating layer.

Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract: The invention provides a semiconductor device having a weak current channel. The semiconductor device includes a gate, a source and a drain. There are a plurality of insulation layers and a plurality of first conductive type lightly doped regions alternatingly arranged between the gate and the drain; each of the first conductive type lightly doped regions providing a weak current channel between the source and the drain. When the gate is in a relatively low voltage range, the weak current channel is conducted; when the gate is in a relatively high voltage range, the weak current channel is not conducted.

Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.

Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a semiconductor layer on a semiconductor substrate of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the semiconductor layer. The semiconductor device includes a first epitaxial layer formed on sidewalls of the trenches where the first epitaxial layer is substantially charge balanced with adjacent semiconductor regions. In another embodiment, a semiconductor device is formed in a first semiconductor layer having trenches and mesas formed thereon where the trenches extend from the top surface to the bottom surface of the first semiconductor layer. The semiconductor device includes semiconductor regions formed on the bottom surface of the mesas of the first semiconductor layer.

Abstract: A semiconductor power device and a method of fabricating the same are provided. The semiconductor power device involving: a first conductivity type semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a second conductivity type well formed in the semiconductor substrate and the epitaxial layer; a drain region formed in the well; an oxide layer that insulates a gate region from the drain region; a first conductivity type buried layer formed in the well; a second conductivity type drift region surrounding the buried layer; and a second conductivity type TOP region formed between the buried layer and the oxide layer.

Abstract: A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.

Abstract: Techniques and structures for shaping the source and drain junction profiles of a finFET are described. A fin may be partially recessed at the source and drain regions of the finFET. The partially recessed fin may be further recessed laterally and vertically, such that the laterally recessed portion extends under at least a portion of the finFET's gate structure. Source and drain regions of the finFET may be formed by growing a buffer layer on the etched surfaces of the fin and/or growing a source and drain layer at the source and drain regions of the fin. The lateral recess can improve channel-length uniformity along the height of the fin.

Abstract: An object is to provide a transistor in which the state of an interface between an oxide semiconductor layer and an insulating film (gate insulating layer) in contact with the oxide semiconductor layer is favorable; and a method for manufacturing the transistor. In order to obtain the transistor, nitrogen is added to a region of the oxide semiconductor layer in the vicinity of the interface with the gate insulating layer. Specifically, a concentration gradient of nitrogen is formed in the oxide semiconductor layer, and a region containing much nitrogen is provided at the interface with the gate insulating layer. By the addition of nitrogen, a region with high crystallinity can be formed in the region of the oxide semiconductor layer in the vicinity of the interface with the gate insulating layer, so that a stable interface state can be obtained.

Abstract: A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract: A semiconductor device is disclosed. An isolation structure is formed in a substrate to define an active region of the substrate, wherein the active region has a field plate region. A gate dielectric layer is formed on the substrate outside of the field plate region. A step gate dielectric structure is formed on the substrate corresponding to the field plate region, wherein the step gate dielectric structure has a thickness greater than that of the gate dielectric layer and less than that of the isolation structure. A method for forming a semiconductor device is also disclosed.

Abstract: A semiconductor device including field insulating films and having first corner portions, provided on a P-type epitaxial growth layer; an N?-type cathode that is provided in the P-type epitaxial growth layer and is located on the inner sides of the field insulating films; and a P?-type anode that is formed on the cathode so as to be in contact with the cathode and covers the first corner portions provided on the inner sides of the field insulating films, wherein the junction between the cathode and the anode serves as a PN junction of the diode, and the PN junction is spaced apart from the first corner portions.

Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

Abstract: A liquid crystal display device includes an inspection control unit configured to alternately perform a first inspection operation in which an inspection signal is input from a first column data line connected to one pixel of the two pixels in each of the pairs into the one pixel and is read out to a second column data line connected to another pixel through the other pixel of the two pixels in each of the pairs and a second inspection operation in which an inspection signal is input from the second column data line into the other pixel and is read out to the first column data line through the one pixel, on all of the plurality of pixels in a unit of pixels in each row when the pixels being inspected.

Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.

Abstract: Semiconductor devices, such as LDMOS devices, are described that include an interlayer-dielectric layer (ILD) region having a thickness of at least two and one half (2.5) microns to increase the maximum breakdown voltage. In one or more implementations, the semiconductor devices include a substrate having a source region and a drain region formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. An ILD region having a thickness of at least two and one half (2.5) microns is formed over the surface and the gate of the device. The device also includes one or more field plates configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.

Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.

Abstract: A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in a region near the body zone and a second thickness in a region near the drift zone.

Abstract: A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type surrounding and being adjacent to the first doped region, wherein the conductive region has a concentration higher than the first doped region; a first heavily doped region disposed in the first doped region; a well having a second conductivity type disposed in the deep well; a second heavily doped region disposed in the well; a gate disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region; and a first trench structure and a second trench structure, wherein a depth of the second trench structure is substantially deeper than a depth of the buried layer.

Abstract: An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow RDSON to be lower for a given BVDSS.

Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.

Abstract: A semiconductor device of an embodiment includes an n-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element A to the concentration of the element D in the above combination is higher than 0.40 but lower than 0.95, and the concentration of the element D forming the above combination is not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3.

Abstract: A semiconductor device comprising a substrate in which a first region and a second region are defined, a gate line which extends in a first direction and traverses the first region and the second region, a source region including a portion formed in the first region, a first part of a body region which is formed under the portion of the source region in the first region and has a first width, a first well which is formed under the first part of the body region in the first region and has a second width greater than the first width, a second part of the body region which is formed in the second region and has a third width, and a second well which is formed under the second part of the body region in the second region and has a fourth width smaller than the third width.

Abstract: A semiconductor device includes a substrate, an insulation layer disposed over the substrate, covering a drift region, and including a first edge and a second edge opposite to the first edge, a gate layer covering the first edge of the insulation layer, and a metal layer including a metal portion connected to the gate layer and overlapping the first edge of the insulation layer. The metal portion includes a first edge located closer to a central portion of the insulation layer than an opposite second edge of the metal portion. A distance from the first edge of the metal portion to the first edge of the insulation layer along a channel length direction is a. A distance from the first edge of the insulation layer to the second edge of the insulation layer is L. A ratio of a/L is equal to or higher than 0.46.

Abstract: A semiconductor device includes an insulated gate bipolar transistor (IGBT) arrangement. The IGBT arrangement includes a carrier confinement reduction region laterally arranged between a cell region and a sensitive region. The IGBT arrangement is configured or formed so that the cell region has a first average density of free charge carriers in an on-state of the IGBT arrangement, the carrier confinement reduction region has a second average density of free charge carriers in the on-state of the IGBT arrangement and the sensitive region has a third average density of free charge carriers in the on-state of the IGBT arrangement. The first average density of free charge carriers is larger than the second average density of free charge carriers and the second average density of free charge carriers is larger than the third average density of free charge carriers.

Abstract: A novel semiconductor device and a method of driving the semiconductor device. A (volatile) node in which data that is rewritten as appropriate by arithmetic processing is held and a node in which the data is stored are electrically connected to each other via a source and a drain of a transistor in which a channel is formed in an oxide semiconductor layer. Then, data and data obtained by inverting the data (inverted data) are stored before supply of power source voltage is stopped, and the two inputs (data) are compared after restart of supply of the power source voltage, so that data obtained by arithmetic processing just before the supply of the power source voltage is stopped is restored.

Abstract: A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.

Abstract: The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type.

Abstract: An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer.

Abstract: The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third impurity layers and fourth impurity layers formed inside the first impurity layer, a fifth impurity layer formed from the uppermost surface of the first impurity layer to the inside of the first impurity layer so as to protrude along the main surface in the direction where the second impurity layer is disposed, and a conductive layer formed above the uppermost surface of the second impurity layer. The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and the fifth impurity layers, and the concentration of the impurity in the fifth impurity layer is higher than the concentration of the impurity in the third impurity layer.

Abstract: A semiconductor rectifier includes a first conductivity type wide bandgap semiconductor substrate having a first conductivity type wide bandgap semiconductor layer on an upper surface of which is formed a plurality of first wide bandgap semiconductor regions of the first conductivity type sandwiching a plurality of second wide bandgap semiconductor regions of a second conductivity type, and a plurality of third wide bandgap semiconductor regions of the second conductivity type, at least a part of the third wide bandgap semiconductor regions being connected to the second wide bandgap semiconductor regions and each of the third wide bandgap semiconductor regions having a width smaller than that of the second wide bandgap semiconductor regions. A first electrode is formed on the first and second wide bandgap semiconductor regions and a second electrode is formed on a lower surface of the wide bandgap semiconductor substrate.

Abstract: A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region parallel to channel current flow. The RESURF trenches have dielectric liners and electrically conductive RESURF elements on the liners. Source contact metal is disposed over the body region and source regions. A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer, and channel regions laterally disposed at the top surface of the substrate. RESURF trenches cut through the drain drift region and body region perpendicular to channel current flow. Source contact metal is disposed in a source contact trench and extended over the drain drift region to provide a field plate.

Abstract: A structure including a semiconductor substrate including a source region and a drain region, a gate located above the semiconductor substrate and between the source region and the drain region, and two opposing halo regions being part of the source and drain regions, respectively, the halo regions being grown epitaxially, wherein the source region and the drain region include a stressor material.

Abstract: The invention relates to a field-effect transistor and a method for its manufacturing having at least one layer, said layer comprising a III-V compound semiconductor, wherein the compound semiconductor comprises at least one element from the chemical group III being selected from any of gallium, aluminium, indium and/or boron and wherein the compound semiconductor comprises at least one element from the chemical group V being selected from nitrogen, phosphorous and/or arsenic, wherein the compound semiconductor comprises at least nitrogen, wherein the field-effect transistor comprises at least any of a source electrode and/or a drain electrode, said source electrode and/or drain electrode comprising at least one doped region extending from the surface into the at least one layer, wherein the depth of penetration of said doped region is selected from approximately 10 nm to approximately 200 nm.

Abstract: A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.

Abstract: A semiconductor device has a source region, channel region, and drain region disposed in order from the surface of the device in the thickness direction of a semiconductor substrate. The device includes a source metal embedded in a source contact groove penetrating the source region and reaching the channel region, a gate insulating film formed on the side wall of a gate trench that is formed to penetrate the source region and channel and reach the drain region, a polysilicon gate embedded in trench so that at least a region facing the channel region in the insulating film is covered with the gate and so that the entire gate is placed under a surface of the source region, and a gate metal that is embedded in a gate contact groove formed in the gate so as to reach the depth of the channel region and in contact with the gate.

Abstract: A semiconductor device of an embodiment has a first conductive type first semiconductor layer, a second conductive type second semiconductor layer provided in the first semiconductor layer having a first lateral surface and a first bottom portion contacting the first semiconductor layer. The second semiconductor layer has a first void portion inside. A second conductive type impurity concentration decreases from the first lateral surface toward the first void portion. And the device has a second conductive type third semiconductor layer provided in the first semiconductor layer such that the first semiconductor layer is sandwiched between the third semiconductor layer and the second semiconductor layer. The third semiconductor layer has a second lateral surface and a second bottom portion contacting the first semiconductor layer. The third semiconductor layer has a second void portion inside.