Abstract: An electrostatic discharge (ESD) protection circuit includes a polysilicon diode, a switch element, and a load element. The poly silicon diode has a first terminal and a second terminal. The switch element has a control terminal coupled to the first terminal of the polysilicon diode, a first terminal coupled to the second terminal of the polysilicon diode, and a second terminal. The load element is coupled to the control terminal of the switch element and the second terminal of the switch element.

Abstract: Perovskite semiconductor thin films and the method of making Perovskite semiconductor thin films are disclosed. Perovskite semiconductor thin films were deposited on inexpensive substrates such as glass and ceramics. CsSnI3 films contained polycrystalline domains with typical size of 300 nm and larger. It is confirmed experimentally that CsSnI3 compound in its black phase is a direct band-gap semiconductor, consistent with the calculated band structure from the first principles.

Abstract: A TFT is provided which includes on a substrate, at least a gate electrode, a gate insulating layer, an active layer containing an amorphous oxide semiconductor, a source electrode, and a drain electrode, wherein a mean square interface roughness between the gate insulating layer and the active layer is less than 2 nm, a carrier concentration of the active layer is 1×1015 cm?3 or more, and a film thickness of the active layer is 0.5 nm or more and less than 20 nm. A TFT is provided which has high field effect mobility and a high ON-OFF ratio, and is improved in environmental temperature dependency. Also, a display using the TFT is provided.

Abstract: A thin film transistor including a lightly doped drain (LDD) region or offset region, wherein the thin film transistor is formed so that primary crystal grain boundaries of a polysilicon substrate are not positioned in the LDD or offset region.

Abstract: There is provided a method for manufacturing a flexible semiconductor device. The method of the present invention comprises the steps of: (a) preparing a metal foil having a concave portion; (b) forming a gate insulating film on a bottom face of the concave portion of the metal foil; (c) forming a semiconductor layer above the bottom face of the concave portion via the gate insulating film while making use of the concave portion as a bank member; and (d) forming a source electrode and a drain electrode such that they make contact with the semiconductor layer.

Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.

Abstract: Epitaxially coated silicon wafers have a rounded and polished edge region and a region adjacent to the edge having a width of 3 mm on the front and rear sides, a surface roughness in edge region of 0.1-1.5 nm RMS relative to a spatial wavelength range of 10-80 ?m, and a variation of surface roughness of 1-10%. The wafer edges, after polishing, are examined for defects and roughness at the edge and surrounding region. Silicon wafers having a surface roughness of less than 1 nm RMS are pretreated in single wafer epitaxy reactors, first in a hydrogen atmosphere at a flow rate of 1-100 slm and in a second step, an etching medium with a flow rate of 0.5-5 slm is conducted onto the edge region of the wafer by a gas distribution device. The wafer is then epitaxially coated.

Abstract: An organic light emitting device according to one or more embodiments includes a gate line, a data line intersecting the gate line, a switching thin film transistor connected to the gate line and the data line, a driving thin film transistor connected to the switching thin film transistor, and a light emitting diode (LED) connected to the driving thin film transistor. The switching thin film transistor includes a control electrode connected to the gate line, a crystalline semiconductor overlapping the control electrode, and an input electrode and an output electrode are spaced apart from each other on the crystalline semiconductor, wherein the control electrode and the gate line are respectively disposed under and on the crystalline semiconductor and include different materials.

Abstract: A transfer layer includes a transparent substrate. A buffer layer is formed on the transparent substrate that comprises PbO, GaN, PbTiO3, La0.5Sr0.5CoO3 (LSCO), or LaxPb1-xCoO3 (LPCO) so that separation between the buffer layer and the transparent substrate occurs at substantially high temperatures.

Abstract: An aqueous acidic composition which includes alkaline compounds, fluoride ions and oxidizing agents is provided for texturing polycrystalline semiconductors. Methods for texturing are also disclosed. The textured polycrystalline semiconductors have reduced reflectance of light incidence.

Abstract: A method is provided for forming a fine pattern. In the method, a first fine pattern and a first metal pattern are formed by respectively patterning a first fine pattern layer on a base substrate and a first metal layer on the first fine pattern layer. A second fine pattern layer and a second metal layer are sequentially formed over the first fine pattern and the first metal pattern. The second metal layer is patterned, so that a second metal pattern between adjacent portions of the first fine pattern. The second fine pattern layer is patterned using the second metal pattern as a mask, so that a second fine pattern is formed between adjacent portions of the first fine pattern.

Abstract: A method of forming a photosensitive pattern on a substrate with a photosensitive layer disposed thereon may include moving at least one of the substrate and a set of micro-mirrors in a first direction, the set of micro-mirrors being disposed above the substrate and being arranged as an array, the array having a first edge extending in a second direction, the second direction being at an acute angle with respect to the first direction. The method may also include selectively turning on one or more micro-mirrors of the set of micro-mirrors according to a position of the set of micro-mirrors relative to the photosensitive layer, thereby irradiating one or more spot beams on the photosensitive layer. The photosensitive layer exposed by the spot beams is developed to form a photosensitive pattern having an edge portion extending in a third direction crossing the first and second directions.

Abstract: Provided is a thin film transistor that may be manufactured using Metal Induced Crystallization (MIC) and method for fabricating the same. Also provided is an active matrix flat panel display using the thin film transistor, which may be created by forming a crystallization inducing metal layer below a buffer layer and diffusing the crystallization inducing metal layer. The thin film transistor may include a crystallization inducing metal layer formed on an insulating substrate, a buffer layer formed on the crystallization inducing metal layer, and an active layer formed on the buffer layer and including source/drain regions, and including polycrystalline silicon crystallized by the MIC process.

Abstract: An organic electronic device including: a first layer including a conductive or semiconductive organic material; a second layer including a conductive or semiconductive inorganic material, and in contact with the first layer; and an interface layer between the first layer and the second layer, wherein the interface layer includes a conductive or semiconductive organic material and a conductive or semiconductive inorganic material.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate.

Abstract: An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate comprises: a substrate; a first oxide layer formed above the substrate; a second oxide layer formed above the first oxide layer with a channel part interposed therebetween; a gate insulating film formed above the substrate, the first oxide layer and the second oxide layer; a gate electrode and a gate wire formed above the gate insulating film.

Abstract: A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area.

Abstract: A pressure sensor 1 comprises a semiconductor substrate 10, insulating layers 21, 22, 23 formed on the semiconductor substrate 10, a semiconductor layer 30 formed on the semiconductor substrate 10 with the insulating layers 21, 23 intervening therebetween, and a cavity portion 13 provided between the semiconductor substrate 10 and the semiconductor layer 30. The portion of the semiconductor layer 30 which overlaps the cavity portion 13 as viewed in a lamination direction serves as a movable portion 31. The cavity portion 13 is surrounded by the insulating layers 22, 23. With this arrangement, the pressure sensor 1 can be manufactured easily with high precision.

Abstract: A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate electrode and a gate line on a substrate through a first mask process, forming a first insulating layer, an active layer, an ohmic contact layer, a buffer metallic layer, and a data line on the substrate including the gate electrode and the gate line through a second mask process, and forming a source electrode, a drain electrode, and a pixel electrode through a third mask process, the pixel electrode extending from the drain electrode, wherein the active layer is disposed over and within the gate electrode.

Abstract: To provide a liquid crystal display device having high visibility and high image quality by relieving color phase irregularity. A light-shielding layer is selectively provided so as to overlap with a contact hole for electrical connection to a source region or a drain region of a thin film transistor. Alternatively, by providing an opening portion of a colored layer (color filter) with an opening so as to overlap with a contact hole, uneven alignment of liquid crystal molecules does not influence display, and a liquid crystal display having high image quality can be provided.

Abstract: A semiconductor structure may include a polycrystalline substrate comprising a metal, the polycrystalline substrate having substantially randomly oriented grains, as well as a buffer layer disposed thereover. The buffer layer may comprise a plurality of islands having an average island spacing therebetween. A polycrystalline semiconductor layer is disposed over the buffer layer.

Abstract: The present invention provides a clean and high-purity polycrystalline silicon mass having a small content of chromium, iron, nickel, copper, and cobalt in total, which are heavy metal impurities that reduce the quality of single-crystal silicon. In the vicinity of an electrode side end of a polycrystalline silicon rod obtained by the Siemens method, the total of the chromium, iron, nickel, copper, and cobalt concentrations is high. Accordingly, before a crushing step of a polycrystalline silicon rod 100, a removing step of removing at least 70 mm of a polycrystalline silicon portion from the electrode side end of the polycrystalline silicon rod 100 extracted to the outside of a reactor is provided. Thereby, the polycrystalline silicon portion in which the total of the chromium, iron, nickel, copper, and cobalt concentrations in a bulk is not less than 150 ppta can be removed.

Abstract: In a nitride semiconductor light emitting diode including a substrate made of a nitride semiconductor, a first conductive-type nitride semiconductor layer formed on the substrate, an active layer made of a nitride semiconductor, and a second conductive-type nitride semiconductor layer, characterized in that light emitted is extracted from the under surface side of the substrate or the upper surface side of the second conductive-type nitride semiconductor layer, an intermediate layer is formed between the substrate and the active layer, and dislocations is allowed to generates from the dislocation generating layer as the origin and to distribute in a light emitting region of the active layer.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot ?+cot ?) (where ? and ? are variables that satisfy the relations 0.5??, ??45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.

Abstract: Disclosed are methods and materials useful in the preparation of semiconductor devices. In particular embodiments, disclosed are methods for engineering polycrystalline aluminum nitride substrates that are thermally matched to further materials that can be combined therewith. For example, the polycrystalline aluminum nitride substrates can be engineered to have a coefficient of thermal expansion (CTE) that is closely matched to the CTE of a semiconductor material and/or to a material that can be used as a growth substrate for a semiconductor material. The invention also encompasses devices incorporating such thermally engineered substrates and semiconductor materials grown using such thermally engineered substrates. The thermally engineered substrates are advantageous for overcoming problems caused by damage arising from CTE mismatch between component layers in semiconductor preparation methods and materials.

Abstract: The invention provides a display panel and display device enabling easy connection to an external connection component depending on the type of a mounted component, and provides a display device manufacturing method allowing a simple manufacturing process. The display panel of the present invention is a display panel in which a thin film transistor array substrate and an opposed substrate are disposed opposing each other. The thin film transistor array substrate has a first routing wiring that is routed at the outer edge of the substrate, a common transfer section that is formed at a position overlapping with the first routing wiring when the substrate surface is viewed from a normal direction, and a first terminal region, having a plurality of terminals formed thereon including a terminal that is joined to the first routing wiring, at an end portion of the substrate.

Abstract: Disclosed are methods for manufacturing semiconductor devices and the devices thus obtained. In one embodiment, the method comprises obtaining a semiconductor substrate comprising a germanium region doped with n-type dopants at a first doping level and forming an interfacial silicon layer overlying the germanium region, where the interfacial silicon layer is doped with n-type dopants at a second doping level and has a thickness higher than a critical thickness of silicon on germanium, such that the interfacial layer is at least partially relaxed. The method further includes forming over the interfacial silicon layer a layer of material having an electrical resistivity smaller than 1×10?2 ?cm, thereby forming an electrical contact between the germanium region and the layer of material, wherein the electrical contact has a specific contact resistivity below 10?4 ?cm2.

Abstract: Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotating element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points.

Abstract: A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n?-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.

Abstract: An organic light emitting device according to one or more embodiments includes a gate line, a data line intersecting the gate line, a switching thin film transistor connected to the gate line and the data line, a driving thin film transistor connected to the switching thin film transistor, and a light emitting diode (LED) connected to the driving thin film transistor. The switching thin film transistor includes a control electrode connected to the gate line, a crystalline semiconductor overlapping the control electrode, and an input electrode and an output electrode are spaced apart from each other on the crystalline semiconductor, wherein the control electrode and the gate line are respectively disposed under and on the crystalline semiconductor and include different materials.

Abstract: An electric double layer capacitor, a lithium ion capacitor, and a charging device including a solar cell and either of the capacitors are disclosed. The electric double layer capacitor includes a first and second light-transmitting substrates; a pair of current collectors provided perpendicular to the substrates; active material layers provided on facing planes of the current collectors; and an electrolyte in a region surrounded by the substrates and the facing active material layers. The lithium ion capacitor includes a first and second light-transmitting substrates; a positive and negative electrode active material layers provided perpendicular to the substrates; and an electrolyte in a region surrounded by the facing substrates and the positive and negative electrode active material layers.

Abstract: An active matrix substrate is provided with a lead wire led from a switching element to a surrounding region; a pad portion formed in the lead wire and positioned in surrounding region; an insulation film including a planarization film positioned uppermost, and a passivation film and a gate insulation film positioned under planarization film, formed so as to cover the pad portion, and having a contact hole formed so as to reach pad portion; and an ITO film positioned in contact hole, and formed on pad portion.

Abstract: The present invention discloses a pixel unit, a liquid crystal display panel and method for forming the same. The liquid crystal display panel comprises a common line, a first shading line, and a second shading line, all of which are under the pixel electrode and are formed by a metallic layer. A lateral side of the first or second shading line, which is not covered by the pixel electrode is a curve edge. The curve first or second shading line expands an area of the common line, resulting in an increase of a storage capacitor. Even if a G/D overlay tolerance exists during the process of forming an LCD panel, a problem of uneven display brightness occurring in the LCD panel is still being improved.

Abstract: A thin film transistor array panel, in which a middle storage electrode and a storage electrode overlapping a drain electrode of a thin film transistor thereby forming a storage capacitance are formed. Accordingly, sufficient storage capacitance may be formed without a decrease of the aperture ratio and light transmittance of a liquid crystal display. Also, the capacitance may be sufficiently formed through the connecting member connected to a gate metal layer.

Abstract: Exact alignment of a recrystallized region, which is to be formed in an amorphous or polycrystalline film, is facilitated. An alignment mark is formed, which is usable in a step of forming an electronic device, such as a thin-film transistor, in the recrystallized region. In addition, in a step of obtaining a large-grain-sized crystal-phase semiconductor from a semiconductor film, a mark structure that is usable as an alignment mark in a subsequent step is formed on the semiconductor film in the same exposure step. Thus, the invention includes a light intensity modulation structure that modulates light and forms a light intensity distribution for crystallization, and a mark forming structure that modulates light and forms a light intensity distribution including a pattern with a predetermined shape, and also forms a mark indicative of a predetermined position on a crystallized region.

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.

Abstract: The invention is related to a semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same. For P-type device, the method includes trench formation, thermal oxide formation on trench sidewalls, N-type silicon formation in trenches, N-type impurity diffusion through thermal oxide into P-type epitaxial layer, oxidation of N-type silicon in trenches and oxide removal. In the semiconductor device, N-type thin semiconductor layers are formed by N-type impurity diffusion through oxide to P-type epitaxial layers, and trenches are filled with oxide. With this method, relatively low concentration impurity in high voltage device can be realized by current mass production process, and the device development cost and manufacturing cost are decreased.

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.

Abstract: A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer.

Abstract: The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.

Abstract: A gate insulating film (13) is formed on a substrate (1) so as to cover a gate electrode (11), and an amorphous silicon film (semiconductor thin film) (15) is further formed. A light absorption layer (19) is formed thereon through a buffer layer (17). Energy lines Lh are applied to the light absorption layer (19) from a continuous-wave laser such as a semiconductor laser. This oxidizes only a surface side of the light absorption layer Lh and produces a beautiful crystalline silicon film (15a) obtained by crystallizing the amorphous silicon film (15) using heat generated by thermal conversion of the energy lines Lh at the light absorption layer (19) and heat of the oxidation reaction. This provides a method for crystallizing a thin film with good controllability at low costs achieved with simpler process.

Abstract: A polycrystalline metal-based LED heat dissipating structure includes a composite substrate, an insulated heat conducting layer, printed circuit layer, electric and heat conducting layer, and a polycrystalline metal-based LED. The composite substrate and the printed circuit layer are linked by the insulated heat conducting layer. The printed circuit layer and the polycrystalline metal-based LED are linked by the electric and heat conducting layer. Through the above structure, the life time of the polycrystalline metal-based LED will be prolonged and the light decadency will be prevented.

Abstract: A diode structure includes: a lower electrode and an insulating layer disposed on the lower electrode. The insulating layer includes aperture exposing a portion of the lower electrode. The diode structure further includes: a first layer and a second layer. The first layer is disposed in the aperture and having a depressed portion. The second layer is disposed in the depressed portion of the first layer. A resistive random access memory (RRAM) device includes the above-described diode structure.

Abstract: A conformal electro-magnetic (EM) detector and a method of applying such a detector are provided herein as well as variations thereof Variations include, but are not limited to, single-element, area detectors; an array of multiple active elements.

Abstract: A solar cell include a polycrystalline semiconductor substrate of a p-type, an emitter region of an n-type and forming a p-n junction with the polycrystalline semiconductor substrate, a first electrode connected to the emitter region, and a second electrode connected to the polycrystalline semiconductor substrate, wherein the polycrystalline semiconductor substrate has a pure p-type impurity concentration of substantially 7.2×1015/cm3 to 3.5×1016/cm3.

Abstract: A thin film transistor (TFT), including a crystalline semiconductor pattern on a substrate, a gate insulating layer on the crystalline semiconductor pattern, the gate insulating layer having two first source/drain contact holes and a semiconductor pattern access hole therein, a gate electrode on the gate insulating layer, the gate electrode being between the two first source/drain contact holes, an interlayer insulating layer covering the gate electrode, the interlayer insulating layer having two second source/drain contact holes therein, and source and drain electrodes on the interlayer insulating layer, each of the source and drain electrodes being insulated from the gate electrode, and having a portion connected to the crystalline semiconductor pattern through the first and second source/drain contact holes.

Abstract: The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing with diffusive scattering and with a smooth front surface of the solar cell results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy.

Abstract: The present invention is to provide GaN crystal growing method for growing a GaN crystal with few stacking faults on a GaN seed crystal substrate having a main surface inclined at an angle of 20° to 90° from the (0001) plane, and also to provide a GaN crystal substrate with few stacking faults. A method for growing a GaN crystal includes the steps of preparing a GaN seed crystal substrate 10 having a main surface 10m inclined at an angle of 20° to 90° from a (0001) plane 10c and growing a GaN crystal 20 on the GaN seed crystal substrate 10. The GaN seed crystal substrate 10 and the GaN crystal 20 have a difference in impurity concentration of 3×1018 cm?3 or less.

Abstract: A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.