Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

Abstract: A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer.

Abstract: A photolithography mask and method includes receiving a layout of an integrated circuit including main pattern elements, inserting an array of dummy pattern elements between and around the main pattern elements, analyzing a diffraction spectrum of at least one of the main pattern elements and the array of dummy pattern elements, and varying one or more of a first pitch between corresponding features of dummy pattern elements adjacent to each other in a first direction and a second pitch between corresponding features of dummy pattern elements adjacent to each other in a second direction based on the analyzed diffraction spectrum to form a modified array of dummy pattern elements. The diffraction spectrum of the modified array of dummy pattern elements and the main pattern elements is more diffuse than a diffraction spectrum of a corresponding array of dummy pattern elements in which neither the first nor second pitch are varied and the main pattern elements.

Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).

Abstract: The dominant source of thermal resistance for silicon photonic devices patterned on SOI wafers is the buried oxide layer. To ensure efficient thermally driven silicon devices there is a need for a large thermal resistance. This is in contrast to temperature sensitive components need to have low thermal resistance in order to reduce their temperature to ensure good performance. Embodiments comprise etching the back of an SOI wafer to expose the buried oxide layer and depositing an additional layer of silicon oxide to increase the local thermal resistance. Thus, embodiments provide the ability to tailor the thermal resistance across the wafer or die depending on the device being fabricated.

Abstract: A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material.

Abstract: The present invention provides polyimide polymer materials for passivating semiconductor wafers and methods for fabricating thereof. The present invention further provides a device that includes a semiconductor wafer and a passivating layer disposed on the surface of the wafer, wherein the passivating layer comprises such polyimide polymers.

Abstract: A method of modifying a fluorinated polymer surface comprising the steps of depositing a first layer on at least a portion of the fluorinated polymer surface, the first layer comprising a first polymer, the first polymer being a substantially perfluorinated aromatic polymer; and depositing a second layer on at least a portion of the first layer, the second layer comprising a second polymer, the second polymer being an aromatic polymer having a lower degree of fluorination than said first polymer, whereby the second layer provides a surface on to which a substance having a lower degree of fluorination than the first polymer, e.g. a non-fluorinated substance is depositable.

Abstract: Described herein are methods of forming dielectric films comprising silicon, oxide, and optionally nitrogen, carbon, hydrogen, and boron. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer.

Abstract: A method for manufacturing a bonded wafer includes: an ion implantation step of using a batch type ion implanter; a bonding step of bonding an ion implanted surface of a bond wafer to a surface of a base wafer directly or through an insulator film; and a delamination step of delaminating the bond wafer at an ion implanted layer, thereby manufacturing a bonded wafer having a thin film on the base wafer, wherein the ion implantation into the bond wafer carried out at the ion implantation step is divided into a plurality of processes, the bond wafer is rotated on its own axis a predetermined rotation angle after each ion implantation, and the next ion implantation is carried out at an arrangement position obtained by the rotation.

Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal.

Abstract: Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties.

Abstract: A process for producing a semiconductor device comprises the following process steps: provision of a semiconductor substrate (1); formation of a functional layer (2) on a semiconductor surface (11) of the semiconductor substrate (1); and production of at least one doped section (3) on the semiconductor surface (11) by driving a dopant into the semiconductor substrate (1) from the functional layer (2). The functional layer (2) is formed in such a way that it passivates the semiconductor surface (11), acting as a passivation layer upon completion of the semiconductor device.

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer that has a portion over the metal pad. A dummy pattern is disposed adjacent to the metal pad. The dummy pattern is level with, and is formed of a same material as, the metal pad. The dummy pattern forms at least a partial ring surrounding at least a third of the metal pad.

Abstract: A passivation layer structure of a semiconductor device is provided, which includes a passivation layer formed of halogen-doped aluminum oxide and disposed on a semiconductor layer on a substrate, in which the semiconductor layer includes indium gallium zinc oxide (IGZO) or nitride-based III-V compounds. A method for forming the passivation layer structure of a semiconductor device is also disclosed.

Abstract: According to the present invention, an epoxy resin composition for semiconductor encapsulant including (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) a compound in which a copolymer of a 1-alkene having 5 to 80 carbon atoms and maleic anhydride is esterified with an alcohol having 5 to 25 carbon atoms in the presence of a compound represented by General Formula (1), wherein R1 in General Formula (1) is selected from the group consisting of an alkyl group having 1 to 5 carbon atoms, a halogenated alkyl group having 1 to 5 carbon atoms, and an aromatic group having 6 to 10 carbon atoms is provided.

Abstract: Wafer-level package (semiconductor) devices are described that have a pillar structure that extends at least partially into a solder bump to mitigate thermal stresses to the solder bump. In implementations, the wafer-level package device may comprise an integrated circuit chip having a surface and a solder bump disposed over the surface. The wafer-level package device may also include a pillar structure disposed over the surface that extends at least partially into the solder bump.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.

Abstract: To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property. A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, and has a first interlayer filler layer containing a resin (A) and an organic filler (B) and having a thermal conductivity of at least 0.8 W/(m·K) between the semiconductor substrate.

Abstract: Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase sulfur precursor to passivate the high-mobility semiconductor surface.

Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.

Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.

Abstract: An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact.

Abstract: The present invention relates to aluminium oxide-based passivation layers which simultaneously act as diffusion barrier for underlying wafer layers against aluminium and other metals. Furthermore, a process and suitable compositions for the production of these layers are described.

Abstract: According one embodiment, a film forming apparatus includes a stage, a coating section, a vapor supply section, a blower section, and a controller. On the stage, an coating target is placed. The coating section applies a material to a predetermined region on the coating target placed on the stage to form a coating film. The vapor supply section generates solvent vapor capable of dissolving the coating film. The blower section blows the solvent vapor generated by the vapor supply section onto the coating film on the coating target placed on the stage. The controller controls an amount of the solvent vapor to be blown by the blower section so that: the coating film is dissolved; viscosity in a part of the coating film on a surface layer side is lower than that in a part thereof on the coating target side; and the viscosity in the part on the surface layer side and the viscosity of the coating target side take such values that prevent the coating film on the coating target from spreading.

Abstract: A semiconductor apparatus includes a semiconductor chip, a lead frame that has a first surface having the semiconductor chip mounted thereover and a second surface opposite to the first surface, a bonding wire that couples the semiconductor chip and the lead frame, and a high dielectric constant layer that is disposed over a surface of the lead frame opposite to a surface having the semiconductor chip mounted thereover and that has a relative permittivity of 5 or more. The lead frame includes a source electrode lead coupled to the source of a semiconductor device formed over the semiconductor chip and a source-wire junction at which the source electrode lead and the bonding wire are coupled together. The high dielectric layer is disposed in a region including at least a position corresponding to the source-wire junction over the second surface of the lead frame.

Abstract: A semiconductor element includes a semiconductor layer, an electrode, an adhesion layer, and an insulating layer. The electrode is disposed over the semiconductor layer and has a first upper surface and a second upper surface disposed further away from the semiconductor layer than the first upper surface. The adhesion layer is disposed on the first upper surface of the electrode so that the second upper surface of the electrode is disposed further away from the semiconductor layer than an upper surface of the adhesion layer. The insulating layer covers from the upper surface of the adhesion layer to the semiconductor layer.

Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.

Abstract: Described are methods of forming a semiconductor device. Certain methods comprises depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer. Also described are semiconductor devices. Certain semiconductor devices comprise a low-k dielectric layer; a manganese nitride layer overlying the low-k dielectric layer; a seed layer selected from a copper seed layer or electrochemical deposition seed layer overlying the manganese nitride layer; a copper layer overlying the copper seed layer.

Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.

Abstract: There is provided a composition for forming a resist underlayer film having heat resistance for use in a lithography process in semiconductor device production. A composition for forming a resist underlayer film, comprising a polymer that contains a unit structure of formula (1) and a unit structure of formula (2) in a proportion of 3 to 97:97 to 3 in molar ratio: A method for producing a semiconductor device, including the steps of: forming an underlayer film using the composition for forming a resist underlayer film on a semiconductor substrate; forming a hard mask on the underlayer film; further forming a resist film on the hard mask; forming a patterned resist film and developing; etching the hard mask according to the patterned resist film; etching the underlayer film according to the patterned hard mask; and processing the semiconductor substrate according to the patterned underlayer film.

Abstract: According to an embodiment of the invention, a passivation layer structure of a semiconductor device disposed on a semiconductor substrate is provided, which includes a passivation layer structure disposed on the semiconductor substrate, wherein the passivation layer structure includes a halogen-doped aluminum oxide layer. According to an embodiment of the invention, a method for forming a passivation structure of a semiconductor device is provided.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition.

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

Abstract: A method for reducing a dielectric constant of a film includes (i) forming a dielectric film on a substrate; (ii) treating a surface of the film without film formation, and (III) curing the film. Step (i) includes providing a dielectric film containing a porous matrix and a porogen on a substrate, step (ii) includes, prior to or subsequent to step (iii), treating the dielectric film with charged species of hydrogen generated by capacitively-coupled plasma without film deposition to reduce a dielectric constant of the dielectric film, and step (iii) includes UV-curing the dielectric film to remove at least partially the porogen from the film.

Abstract: A semiconductor device according to an embodiment, includes a dielectric film and an Si semiconductor part. The dielectric film is formed by using one of oxide, nitride and oxynitride. The Si semiconductor part is arranged below the dielectric film, having at least one element of sulfur (S), selenium (Se), and tellurium (Te) present in an interface with the dielectric film, and formed by using silicon (Si).

Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

Abstract: A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 ?m may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region.

Abstract: According to one embodiment, a_semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a mark and a supporting unit. The mark is opened onto a surface of the stacked body. The supporting unit is provided around the mark. The supporting unit extends in a stacked direction of the stacked body. The supporting unit is in contact with at least a plurality of conductive layers.

Abstract: The present invention provides polyimide polymer materials for passivating semiconductor wafers and methods for fabricating thereof. The present invention further provides a device that includes a semiconductor wafer and a passivating layer disposed on the surface of the wafer, wherein the passivating layer comprises such polyimide polymers.

Abstract: A resist underlayer film forming composition for lithography includes: as a component (I), a fluorine-containing highly branched polymer obtained by polymerizing a monomer A having two or more radical polymerizable double bonds in the molecule thereof, a monomer B having a fluoroalkyl group and at least one radical polymerizable double bond in the molecule thereof, and a monomer D having a silicon atom-containing organic group and at least one radical polymerizable double bond in the molecule thereof, in the presence of a polymerization initiator C in a content of 5% by mole or more and 200% by mole or less, based on the total mole of the monomer A, the monomer B, and the monomer D; and as a component (II), a hydrolyzable silane compound, a hydrolysis product thereof, a hydrolysis-condensation product thereof, or a silicon-containing compound that is a combination of these compounds.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: A dielectric layer for an electronic device, such as a thin-film transistor, is provided. The dielectric layer comprises a molecular glass. The resulting dielectric layer is very thin, pure, and stable. Processes and compositions for fabricating such a dielectric layer are also disclosed.

Abstract: Embodiments of to invention relate to a process for fabricating a silicon-on-insulator structure comprising the following steps: providing a donor substrate and a support substrate, only one of the substrates being covered with an oxide layer; forming, in the donor substrate, a weak zone; plasma activating the oxide layer; bonding the donor substrate to the support substrate in a partial vacuum; implementing a bond-strengthening anneal at a temperature of 350° C. or less causing the donor substrate to cleave along the weak zone; and carrying out a heat treatment at a temperature above 900° C. A transition from the temperature of the bond-strengthening anneal to the temperature of the heat treatment may be achieved at a ramp rate above 10° C./s.

Abstract: Low-k porous insulating films with a high modulus of elasticity are made by depositing alkylated cyclic siloxane precursors over a semiconductor substrate by CVD. Plasma enhancement of the CVD is performed either during CVD or in situ on the deposited film. A UV cure of the film is effected under controlled temperature and time conditions, which generates a tight bonding structure between adjacent ring moieties without disrupting the Si—O ring bonding.

Abstract: A method of forming a semiconductor structure includes forming a photoresist layer over a substrate. The photoresist layer includes a first material removable by a removal process. The first material at a guard band portion of the photoresist layer along an edge portion of the photoresist layer is converted to a second material. The second material is not removable by the removal process. Also, the first material at the edge portion of the photoresist layer is not converted to the second material. The guard band portion is farther from a periphery of the substrate than the edge portion. The removal process is performed to remove the first material after the conversion of the guard band portion.

Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).

Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.

Abstract: The invention relates to a method for producing passivation layers on crystalline silicon by a) coating the silicon with a solution containing at least one polysilazane of the general formula (1): —(SiR?R?—NR??)-n, wherein R?, R?, R?? are the same or different and stand independently of each other for hydrogen or a possibly substituted alkyl, aryl, vinyl, or (trialkoxysilyl)alkyl group, wherein n is an integer and n is chosen such that the polysilazane has a number average molecular weight of 150 to 150,000 g/mol, b) subsequently removing the solvent by evaporation, whereby polysilazane layers of 50-500 nm thickness remain on the silicon wafer, and c) heating the polysilazane layer at normal pressure to 200-1000° C. in the presence of air or nitrogen, wherein upon tempering the ceramic layers release hydrogen for bulk passivation of the silicon.