Abstract: An integrated circuit includes at least one porous silicon oxycarbide (SiOC) insulator, which provides good mechanical strength and a low dielectric constant (e.g., &egr;R<2) for minimizing parasitic capacitance. The insulator provides IC isolation, such as between circuit elements, between interconnection lines, between circuit elements and interconnection lines, or as a passivation layer overlying both circuit elements and interconnection lines. The low dielectric constant silicon oxycarbide isolation insulator of the present invention reduces the parasitic capacitance between circuit nodes. As a result, the silicon oxycarbide isolation insulator advantageously provides reduced noise and signal crosstalk between circuit nodes, reduced power consumption, faster circuit operation, and minimizes the risk of potential timing faults.

Abstract: A semiconductor device less susceptible to inverse narrow channel effect and its manufacturing method are provided. A silicon nitride film (13) is adopted as element isolation regions; the silicon nitride film (13) has a smaller etch rate than a sacrificial silicon oxide film (7) which serves as a sacrificial layer during ion implantation (8). This prevents formation of recesses in the silicon nitride film (13) during the removal of the sacrificial silicon oxide film (7), which weakens the strength of the electric fields at the gate edges. Weakening the strength of the electric fields at the gate edges suppresses the inverse narrow channel effect, so that the MOS transistor offers a characteristic closer to a characteristic in which the threshold voltage keeps a constant value independently of the channel width. Thus an MOS transistor having a good characteristic can be manufactured.

Abstract: A method of forming semiconductor device. treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C.

Abstract: A method for depositing a silicon oxycarbide hard mask on a low k dielectric layer is provided. Substrates containing a silicon oxycarbide hard mask on a low k dielectric layer are also disclosed. The silicon oxycarbide hard mask may be formed by a processing gas comprising a siloxane.

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: A semiconductor device of this invention includes a silicon nitride film formed on a semiconductor substrate and having a density of 2.2 g/cm3 or less, and a silicon oxide film formed on the silicon nitride film in an ambient atmosphere containing TEOS and O3.

Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.

Abstract: The present invention relates to nanoporous dielectric films and to a process for their manufacture. A substrate having a plurality of raised lines on its surface is provided with a relatively high porosity, low dielectric constant, silicon containing polymer composition positioned between the raised lines and a relatively low porosity, high dielectric constant, silicon containing composition positioned on the lines.

Abstract: A semiconductor device of the present invention comprises a first split Pad electrode which is electrically connected to wirings and a MOSFET and a second split Pad electrode which is not electrically connected to wirings and a MOSFET. Then, a passivation film which covers a part of the surface of the second split pad electrode is formed and a non-split pad electrode which covers the surfaces of the first and second split pad electrodes which are not covered with the passivation film is formed.

Abstract: The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

Abstract: A low k porous dielectric film is described wherein the exposed surface or surfaces of the film are substantially non-porous. A densification method is described for treating such exposed surfaces to render porous surfaces non-porous.

Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.

Abstract: Within a method for forming a dielectric layer, there is first provided a substrate. There is then formed over the substrate a dielectric layer, wherein the dielectric layer is formed from a dielectric material comprising silicon, carbon and nitrogen. Preferably, a nitrogen content is graded within a thickness of the dielectric layer to provide an upper lying nitrogen rich contiguous surface layer of the dielectric layer and a lower lying nitrogen poor contiguous layer of the dielectric layer. The method contemplates a microelectronic fabrication having formed therein a dielectric layer formed in accord with the method. The method provides the resulting dielectric layer with a lower dielectric constant and enhanced adhesion properties as a substrate layer.

Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critcal width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g.

Abstract: A vertical cavity-type semiconductor light-emitting device comprises a first semiconductor distributed Bragg reflector type mirror formed on a substrate, a first semiconductor layer formed on the first semiconductor distributed Bragg reflector type mirror and including at least an active layer which becomes an emission layer, a second semiconductor distributed Bragg reflector type mirror formed on the first semiconductor layer and including Al as a configuration element, and a second semiconductor layer including InxGa1−xP (0≦x≦1) layer provided on the second semiconductor distributed Bragg reflector type mirror.

Abstract: The present invention relates to a semiconductor device manufacturing method for forming an interlayer insulating film containing a coating insulating film having a low dielectric constant. In construction, there are provided the steps of preparing a substrate 20 on a surface of which a coating insulating film 26 is formed by coating a coating liquid containing any one selected from a group consisting of silicon-containing inorganic compound and silicon-containing organic compound, and forming a protection layer 27 for covering the coating insulating film 26 by plasmanizing a first film forming gas to react, wherein the first film forming gas consists of any one selected from a group consisting of alkoxy compound having Si—H bonds and siloxane having Si—H bonds and any one oxygen-containing gas selected from a group consisting of O2, N2O, NO2, CO, CO2, and H2O.

Abstract: Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.

Abstract: A semiconductor device and a method for manufacturing the same, wherein a gate electrode structure is formed on a surface of a semiconductor substrate. Next, a gate poly oxide (GPOX) layer is deposited on a surface of the gate electrode structure and on the semiconductor substrate. Then, the surface of the semiconductor substrate is cleaned to remove any residue and the GPOX layer remaining on the semiconductor substrate. Next, an etch stopper is formed on the surface of the gate electrode structure and on the semiconductor substrate. Last, a high-density plasma (HDP) oxide layer is deposited on the etch stopper. The semiconductor device and method for manufacturing the same are capable of preventing bubble defects.

Abstract: A substrate with at least one conductive post formed prior to the formation of an inter-layer dielectric (ILD) coating on the substrate. The conductive post may be formed from a metal layer of the substrate. Additionally, the conductive post may be built up on the substrate.

Abstract: A semiconductor device comprising a substrate having an insulating surface layer and an active layer comprising a semiconductor thin film formed thereon, wherein the substrate and the insulating surface layer in contact with the substrate each has at least one concave part, and the influence of the concave part is removed by conducting a flattening treatment and heat treatment of the undercoat film of the semiconductor thin film.

Abstract: A dielectric thin film element enables controlling of a crystal orientation of a dielectric thin film and optimization of a variety of characteristics such as electric characteristics. This dielectric thin film element (10) comprises a substrate (11), a first electrode (12) formed on the substrate (11), a dielectric thin film (13) formed on the first electrode (12) and a second electrode (14) formed on the dielectric thin film (13) and is fabricated with the substrate (11) being heated. A material having a predetermined thermal expansion coefficient is used as the material of the substrate (11), and a crystal orientation of the dielectric thin film (13) is controlled by the thermal expansion coefficient of the substrate (11).

Abstract: A photomask and method of patterning a photosensitive layer using a photomask, the photomask including a substrate and a film coupled to substrate. The film is etched with a phase shifted assist feature, a low aspect ratio assist feature or phase shifted low aspect primary features.

Abstract: In order to determine the dielectric constant of a layer deposited on a semiconducotr wafer (2), the density of the layer is obtained. To obtain that density, the wafer (2) without the layer is weighed in a weighing chamber (4) in which a weighing pan (7) supports the wafer on a weighing balance. The weight of the wafer is determined taking into account the buoyancy exerted by the air on the wafer (2). Then the layer is deposited on the wafer (2) and the weighing operation repeated. Alternatively a reference wafer may be used. If the material of the layer is known, the weight of the layer can be used to derive its density using a thickness measurement. Alternatively, if the density is known, the thickness can be obtained.

Abstract: A process for forming a final passivation layer over an integrated circuit comprises a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition.

Abstract: A method of producing a protective inhibitor layer of moisture-generated corrosion for aluminum (Al) alloy metallization layers, particularly in semiconductor electronic devices, includes chemically treating the metallization layer in at least two steps using a mixture of concentrated nitric acid and trace phosphoric acid to produce a thin protective phosphate layer. Alternatively, the method may include dipping the electronic device at least once in a mixture of a polar organic solvent and phosphoric acid (H3PO4) or phosphate derivatives thereof in a low percentage amount (e.g., with a phosphate reactant such as orthophosphoric acid or even R—HxPOy, where R is an alkaline type of ion group or an alkyl radical). The thin film may be formed on top of a thin layer of native aluminum oxide hydrate Al2O3.xH2O.

Abstract: A platen for use in a dry etching process for substrate production, the platen having a surface susceptible to chipping and/or particle generation from the dry etching process and a coating applied to at least a portion of the surface for rendering the surface less susceptible to chipping and/or particle generation, the coating comprising a silicon carbide coating

Abstract: A method of surface treating a surface and semiconductor article is disclosed. A deposited surface layer on a substrate, such as a semiconductor surface, is treated and annealed within an alkyl environment of a chemical vapor deposition chamber to passivate the surface layer by bonding with the silicon and attaching alkyl terminating chemical species on the surface of the surface layer to aid in dehydroxylating the surface. The surface layer comprises a silicon-oxy-carbide surface layer having a carbon content ranging from about 5% to about 20% at the molecular level and a dielectric constant of about 2.5 to about 3.0.

Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.

Abstract: Moisture seal apparatus and methodologies are disclosed for protecting semiconductor devices from moisture. An upper seal layer, such as SiN is formed over an upper insulator layer and an exposed portion of a die seal metal structure so as to form a vertical moisture seal between electrical components in the semiconductor device and the ambient environment. A lateral seal may be formed from the die seal metal structure in an upper metal layer in the device and one or more contacts extending downward from the die seal metal to the substrate or to a lower die seal metal structure.

Abstract: An MOS heterostructure includes: a single crystal silicon substrate; an insulating film formed on the substrate; and a conductive film formed on the insulating film. The substrate includes a plurality of terraces and steps, which have been formed as a result of rearrangement of silicon atoms on the surface of the substrate. Each of the step is located in a boundary between an adjacent pair of the terraces. The insulating film contains crystalline silicon dioxide that has grown epitaxially over the steps.

Abstract: An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.

Abstract: The present invention provides a novel visible light curable composition for forming a thermally conductive interface and a method of using the same. The composition is used to promote the transfer of heat from a source of heat such as an electronic device to a heat dissipation device such as a heat sink. The composition includes an elastomeric base matrix containing a light curable catalyst, loaded with a thermally conductive filler material such as boron nitride grains or ceramic filler. After the compound is prepared, it is screen or stencil printed onto the desired surface and cured by exposure to visible light. The present invention provides a thermal interface that is bonded to the surface of the desired surface and has sufficient compressibility to allow it to overcome the voids in the mating surface to which the assembly is mounted.

Abstract: A process for producing semiconductor substrates with a coating film having an excellent chemical resistance with a high yield and an excellent production reliability without any development of cracks and any generation of foreign matters due to a projected portion of the coating film is described, which includes the steps of:

Abstract: A process for forming a nanoporous dielectric coating on a substrate. The process includes forming a substantially uniform alkoxysilane gel composition on a surface of a substrate, which alkoxysilane gel composition comprises a combination of at least one alkoxysilane, an organic solvent composition, water, and an optional base catalyst; heating the substrate for a sufficient time and at a sufficient temperature in an organic solvent vapor atmosphere to thereby condense the gel composition; and then curing the gel composition to form a nanoporous dielectric coating having high mechanical strength on the substrate.

Abstract: A sealing dielectric layer is applied between a porous dielectric layer and a metal diffusion barrier layer. The sealing dielectric layer closes the pores on the surface and sidewalls of the porous dielectric layer. This invention allows the use of a thin metal diffusion barrier layer without creating pinholes in the metal diffusion barrier layer. The sealing dielectric layer is a CVD deposited film having the composition SixCy:Hz.

Abstract: A method for making an apparatus, for example, comprises attaching at least one self-assembled monolayer to a first element formed on a substrate. Thereafter, at least one attaching layer is formed on the substrate, adjacent to the one or more self-assembled monolayers. A second element is then formed on the one or more attaching layers spaced from the first element by about a length of the one or more self-assembled monolayers.

Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same. In the present invention, a protection insulating film for preventing Cu from diffusing into the inside of the wafer is formed on a peripheral portion of a principal plane, a external side plane and a rear plane of the wafer. With this protection insulating film, the diffusion of Cu that is a wiring material into a chip formation region of the wafer is prevented, so that the variations of the transistor characteristic.

Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.

Abstract: A method of producing a protective inhibitor layer of moisture-generated corrosion for aluminum (Al) alloy metallization layers, particularly in semiconductor electronic devices, includes chemically treating the metallization layer in at least two steps using a mixture of concentrated nitric acid and trace phosphoric acid to produce a thin protective phosphate layer. Alternatively, the method may include dipping the electronic device at least once in a mixture of a polar organic solvent and phosphoric acid (H3PO4) or phosphate derivatives thereof in a low percentage amount (e.g., with a phosphate reactant such as orthophosphoric acid or even R—HxPOy, where R is an alkaline type of ion group or an alkyl radical). The thin film may be formed on top of a thin layer of native aluminum oxide hydrate Al2O3.xH2O.

Abstract: A semiconductor processing component includes a quartz body characterized by silicon oxide filled micro cracks. The component is utilized as a processing component in a semiconductor furnace system. The quartz body is prepared by cleaning the component to remove a build up silicon layer and to expose micro cracks in the surface of the component and to etch the micro cracks into trenches. A silicon layer is applied onto the processing component body and at least a portion of the silicon is oxidized to silica to fill the trenches in the surface of the component body.

Abstract: Porous dielectric materials having low dielectric constants, ≧30% porosity and a closed cell pore structure are disclosed along with methods of preparing the materials. Such materials are particularly suitable for use in the manufacture of electronic devices.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.

Abstract: The present invention relates to low dielectric constant nanoporous silica films and to processes for their manufacture. A substrate, e.g., a wafer suitable for the production of an integrated circuit, having a plurality of raised lines and/or electronic elements present on its surface, is provided with a relatively high porosity, low dielectric constant, silicon-containing polymer film composition.

Abstract: A novel technology is provided for encapsulating electronics for use in harsh media applications, such as biomedical implants. The present invention includes electroplating a metal film on top of an insulating layer to hermetically seal an electronic system, microstructure, or micro device.

Abstract: An oxide for use in integrated circuits is substantially stress-free both in the bulk and at the interface between the substrate and the oxide. The interface is planar and has a low interface trap density (Nit). The oxide has a low defect density and may have a thickness of less than 1.5 nm or less.

Abstract: A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded in the foamed polymer layer. An insulator is formed by forming a polymer layer having a thickness on a substrate. The polymer layer is foamed to form a foamed polymer layer having a surface and a foamed polymer layer thickness, which is greater than the polymer layer thickness. The surface of the foamed polymer layer is treated to make the surface hydrophobic.

Abstract: A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer.

Abstract: Insulating material is formed to surround interconnect structures of an integrated circuit. A first semiconductor wafer is placed in a reaction chamber for forming the insulating material surrounding the interconnect structures of the integrated circuit on the first semiconductor wafer. A corrosive dielectric material having low dielectric constant is deposited to surround the interconnect structures, and the corrosive dielectric material fills any gaps between the interconnect structures. Deposition of the corrosive dielectric material is performed within the reaction chamber, and the corrosive dielectric material is deposited on the reaction chamber during deposition of the corrosive dielectric material on the first semiconductor wafer.

Abstract: A dielectric structure is disclosed for silicon carbide-based semiconductor devices. In gated devices, the structure includes a layer of silicon carbide, a layer of silicon dioxide on the silicon carbide layer, a layer of another insulating material on the silicon dioxide layer, with the insulating material having a dielectric constant higher than the dielectric constant of silicon dioxide, and a gate contact to the insulating material. In other devices the dielectric structure forms an enhanced passivation layer or field insulator.