Abstract: The process of Polymer Assisted Chemical Vapor Deposition (PACVD) and the semiconductor, dielectric, passivating or protecting thin films produced by the process are described. A semiconductor thin film of amorphous silicon carbide is obtained through vapor deposition following desublimation of pyrolysis products of polymeric precursors in inert or active atmosphere. PA-CVD allows one or multi-layers compositions, microstructures and thicknesses to be deposited on a wide variety of substrates. The deposited thin film from desublimation is an n-type semiconductor with a low donor concentration in the range of 1014-1017 cm?3. Many devices can be fabricated by the PA-CVD method of the invention such as; solar cells; light-emitting diodes; transistors; photothyristors, as well as integrated monolithic devices on a single chip. Using this novel technique, high deposition rates can be obtained from chemically synchronized Si—C bonds redistribution in organo-polysilanes in the temperature range of about 200-450° C.

Abstract: In a method for producing at least at least one area (8) with reduced electrical conductivity within an electrically conductive III-V semiconductor layer (3), a ZnO layer (1) is applied to the area (8) of the semiconductor layer (3) and subsequently annealed at a temperature preferably between 300° C. and 500° C. The ZnO layer (1) is preferably deposited on the III-V semiconductor layer (3) at a temperature of less than 150° C., preferably at a temperature greater than or equal to 25° C. and less than or equal to 120° C. The area (8) with reduced electrical conductivity is preferably located in a radiation emitting optoelectronic device between the active zone (4) and a connecting contact (7) in order to reduce current injection into the areas of the active zone (4) located opposite to the connecting contact (7).

Abstract: Organic polymers for use in electronic devices, wherein the polymer includes repeat units of the formula: wherein: each R1 is independently H, an aryl group, Cl, Br, I, or an organic group that includes a crosslinkable group; each R2 is independently H, an aryl group or R4; each R3 is independently H or methyl; each R5 is independently an alkyl group, a halogen, or R4; each R4 is independently an organic group that includes at least one CN group and has a molecular weight of about 30 to about 200 per CN group; and n=0-3; with the proviso that at least one repeat unit in the polymer includes an R4. These polymers are useful in electronic devices such as organic thin film transistors.

Abstract: Molecular fluorine may be generated and distributed on-site at a fabrication facility. A molecular fluorine generator may come in a variety of sizes to fit better the needs of the particular fabrication facility. The generator may service one process tool, a plurality of process tool along a process bay, the entire fabrication facility, or nearly any other configuration within the facility. The process can obviate the need and inherent risks with transporting or handling gas cylinders. The process can be used in conjunction with a cleaning or fabrication operation used in the electronics fabrication industry.

Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

Abstract: The invention provides a substantially transparent material comprising particles of an inorganic titanate or an inorganic zirconate and at least one compound, wherein the particles are uniformly dispersed in the at least one compound, and wherein the particles are bonded to the at least one compound via at least one surface functional group of the particles. The invention also provides a light emitting device comprising a light emitting diode encapsulated with the substantially transparent material.

Abstract: Disclosed herein is a method for forming an interlayer dielectric film for a semiconductor device by using a polyhedral molecular silsesquioxane. According to the method, the polyhedral molecular silsesquioxane is used as a monomer for a siloxane-based resin or as a pore-forming agent (porogen) to prepare a composition for forming a dielectric film, and the composition is coated on a substrate to form an interlayer dielectric film for a semiconductor device. The interlayer dielectric film formed by the method has a low dielectric constant and shows superior mechanical properties.

Abstract: A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

Abstract: A method of manufacturing a semiconductor device includes forming a metal oxide on a semiconductor substrate, forming a gate electrode film on the metal oxide, and executing a thermal treatment on the semiconductor substrate provided with the metal oxide and the gate electrode film to crystallize the metal oxide.

Abstract: A method for manufacturing a semiconductor device, in which a substrate is disposed in a chamber and a fluorine-containing silicon oxide film is formed on the substrate using a plasma CVD process. The fluorine-containing silicon oxide film is formed such that the release of fluorine from this silicon oxide layer is suppressed. According to this semiconductor device manufacturing method, a stable semiconductor device can be provided such that the device includes a fluorine-containing silicon oxide film (FSG film) at which the release of fluorine is suppressed, and thus peeling does not occur.

Abstract: Provided is a porous-film-forming composition containing silicon-oxide-based fine particles and a polysiloxane compound obtained by hydrolysis and condensation reactions, in the presence of an acid catalyst, of a hydrolyzable silane compound containing at least one tetrafunctional alkoxysilane compound represented by the following formula (1): Si(OR1)4 ??(1) wherein, R1s may be the same or different and each independently represents a linear or branched C1-4 alkyl group and/or at least one alkoxysilane compound represented by the following formula (2): R2nSi(OR3)4-n ??(2) wherein, R2(s) may be the same or different when there are plural R2s and each independently represents a linear or branched C1-8 alkyl group, R3(s) may be the same or different when there are plural R3s and each independently represents a linear or branched C1-4 alkyl group, and n is an integer from 1 to 3 in the reaction mixture containing a large excess of water.

Abstract: Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of ?4 to ?3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B) manufactured from SiH4 and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.

Abstract: The present invention relates to a process for producing an SiO2-containing insulating layer on chips and the use of specific precursors for this purpose. The invention further relates to an insulating layer obtainable in this way and also to chips which have been provided with such an insulating layer.

Abstract: Disclosed herein is a semiconductor device including a gate insulating film formed over a semiconductor substrate, and a gate electrode formed over the gate insulating film, wherein the gate insulating film is so provided as to protrude from both sides of the gate electrode, and the gate electrode includes a wholly silicided layer.

Abstract: An integrated circuit including a dielectric layer and a method for producing an integrated circuit. In one embodiment, a dielectric layer is deposited in a process atmosphere. The process atmosphere includes a first starting component at a first point in time, a second starting component at a second point in time and a third starting component at a third point in time. The third starting component includes a halogen.

Abstract: A wafer processing apparatus is fabricated by depositing a film electrode onto the surface of a base substrate, the structure is then overcoated with a protective coating film layer comprising at least one of a nitride, carbide, carbonitride or oxynitride of elements selected from a group consisting of B, Al, Si, Ga, refractory hard metals, transition metals, and combinations thereof. The film electrode has a coefficient of thermal expansion (CTE) that closely matches the CTE of the underlying base substrate layer as well as the CTE of the protective coating layer.

Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.

Abstract: A porous composite material useful in semiconductor device manufacturing, in which the diameter (or characteristic dimension) of the pores and the pore size distribution (PSD) is controlled in a nanoscale manner and which exhibits improved cohesive strength (or equivalently, improved fracture toughness or reduced brittleness), and increased resistance to water degradation of properties such as stress-corrosion cracking, Cu ingress, and other critical properties is provided. The porous composite material is fabricating utilizing at least one bifunctional organic porogen as a precursor compound.

Abstract: One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.

Abstract: The present invention relates to a magnesium oxide-based (MgO) inorganic coating intended to electrically insulate semiconductive substrates such as silicon carbide (SiC), and to a method for producing such an insulating coating. The method of the invention comprises the steps of preparing a treatment solution of at least one hydrolysable organomagnesium compound and/or of at least one hydrolysable magnesium salt, capable of forming a homogeneous polymer layer of magnesium oxyhydroxide by hydrolysis/condensation reaction with water; depositing the treatment solution of the hydrolysable organomagnesium compound or of the hydrolysable magnesium salt, onto a surface to form a magnesium oxide-based layer; and densifying the layer formed at a temperature of less than or equal to 1000° C.

Abstract: The present invention relates to a polymeric compound comprising, as structural units, groups each represented by the following general formula (1); and an insulating film for a semiconductor integrated circuit which comprises the polymeric compound: —R1—C?C—C?C—, wherein R1 represents a group having a cage-shaped structure. The insulating film has a high heat resistance, a high mechanical strength and a low dielectric constant. In addition, the insulating film has a high stability of its dielectric constant with the elapse of time. Furthermore, the present invention can provide an interlayer insulating film for electronic devices having a high heat resistance, a high mechanical strength and a low dielectric constant which can be maintained over an extremely long period of time as well as an electronic device whose layer structure is provided with such an insulating film as a constituent thereof.

Abstract: A method is disclosed which includes forming an opening in an insulating material, performing a plasma process to introduce nitrogen into a portion of the insulating material to thereby form a nitrogen-containing region at least on an inner surface of the opening, and, after forming the nitrogen-containing region, performing an etching process through the opening. A device is disclosed which includes an insulating material comprising a nitrogen-enhanced region that is proximate an opening that extends through the insulating material and a conductive structure positioned within the opening.

Abstract: A method for capturing process history includes performing at least a first process for forming features on a semiconducting substrate. A first cap is formed over a first region of the semiconducting substrate after performing the first process. At least a second process is performed for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process. A first characteristic of a first feature is measured in the first region, and a second characteristic of a second feature in the second region is measured. A wafer includes a first partially completed feature disposed in a first region. A first cap is formed above the first partially completed feature. A second partially completed feature is disposed in a second region of the wafer different than the first region.

Abstract: A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties include reduced current leakage which is achieved without adversely affecting (increasing) the dielectric constant of the SiCOH dielectric film. In accordance with the present invention, a SiCOH dielectric film exhibiting reduced current leakage and improved reliability is obtained by subjecting an as deposited SiCOH dielectric film to a DUV laser anneal. The DUV laser anneal step of the present invention likely removes the weakly bonded C from the film, thus improving leakage current.

Abstract: An insulating film for semiconductor devices is obtained by curing, on a substrate, a high molecular compound obtained by polymerizing a cage-type silsesquioxane compound having two or more unsaturated groups as substituents and having a cyclic siloxane structure, wherein the structure of the cage-type silsesquioxane compound is not broken by curing, and the breakage of the cage structure can be detected by observing a peak at approximately 610 cm?1 in Raman spectrum of the film after curing.

Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

Abstract: Methods for applying a dielectric protective layer to a wafer in wafer-level chip scale package manufacture are disclosed. A flowable dielectric protective material with fluxing capability is applied over the active surface of an unbumped semiconductor wafer to cover active device areas, bond pads, test socket contact locations, and optional pre-scribed wafer street trenches. Preformed solder balls are then disposed over the bond pads, and the wafer is subjected to a heating process to reflow the solder balls and at least partially cure the dielectric protective material. During the heating process, the dielectric protective material provides a fluxing capability to enable the solder balls to wet the bond pads. In other exemplary embodiments, the dielectric protective material is applied over only intended physical contact locations and/or pre-scribed wafer street trenches, in which case the dielectric protective material need not include flux material and may additionally include a filler material.

Abstract: A substrate polishing method, a semiconductor device and a fabrication method for a semiconductor device are disclosed by which high planarization polishing can be achieved. In the substrate polishing method, two or more different slurries formed from ceria abrasive grains having different BET values from each other are used to carry out two or more stages of chemical-mechanical polishing processing of a polishing object oxide film on a substrate to flatten the polishing object film.

Abstract: It is an object to provide an insulating film having a very low dielectric constant and a great mechanical strength. Moreover, it is another object to provide a semiconductor device capable of reducing both a capacity between wiring layers and a capacity between wirings also in microfabrication and an increase in integration in the semiconductor device. In order to attain the objects, there is provided an inorganic insulating film comprising a porous structure having a skeletal structure in which a vacancy is arranged periodically and a large number of small holes are included.

Abstract: A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ polysilicon layer on one side of the channel region and a P+ polysilicon layer on an opposite side of the channel region, thereby, partitioning the fin structure into a first side and a second side, respectively. The channel region is in mechanical tension on the first side and in mechanical compression on the second side. The FinFET may comprise any of a nFET and a pFET, wherein the nFET comprises a N-channel inversion region in the first side, and wherein the pFET comprises a P-channel inversion region in the second side. The CMOS device may further comprise a tensile film and a relaxed film on opposite sides of the fin structure adjacent to the source and drain regions, and an oxide cap layer over the fin structure.

Abstract: An electronic device and a process for manufacturing the same are disclosed. In one aspect, the device comprises an electrode comprising a metal compound selected from the group of tantalum carbide, tantalum carbonitride, hafnium carbide and hafnium carbonitride. The device further comprises a high-k dielectric layer of a hafnium oxide comprising nitrogen and silicon, the high-k dielectric layer having a k value of at least 4.0. The device further comprises a nitrogen and/or silicon and/or carbon barrier layer placed between the electrode and the high-k dielectric layer. The nitrogen and/or silicon and/or carbon barrier layer comprises one or more metal oxides, the metal of the metal oxides being selected from the group of lanthanides, aluminium or hafnium.

Abstract: The present invention provides inhibiting an electrical leakage caused by anion migration. A trenched portion 15 is provided as ion migration-preventing zone between a source electrode 4 and a gate electrode 5. The trenched portion 15 is formed so as to surround a periphery of the source electrode 4.

Abstract: A low-k organic dielectric material having stable nano-sized porous is provided as well as a method of fabricating the same. The porous low-k organic dielectric material is made from a composition of matter having a vitrification temperature (Tv-comp) which includes a b-staged thermosetting resin having a vitrification temperate (Tv-resin), a pore generating material, and a reactive additive. The reactive additive lowers Tv-comp below Tv-resin.

Abstract: A porous dielectric element is produced by forming a first dielectric and a second dielectric. The second dielectric is dispersed in the first dielectric. The second dielectric is then removed from the second dielectric by using a chemical dissolution. The removal of the second dielectric from the first dielectric leaves pores in the first dielectric. The pores, which are filled with air, improves the overall dielectric constant of the resulting dielectric element.

Abstract: The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.

Abstract: Thin oxide films are grown on silicon which has been previously treated with a gaseous or liquid source of chloride ions. The resulting oxide is of more uniform thickness than obtained on untreated silicon, thereby allowing a given charge to be stored on a floating gate formed over said oxide for a longer time than previously required for a structure not so treated.

Abstract: Nanolaminate-structure SrO/TiO films are formed on a lower electrode of a capacitor by molecular layer deposition kept in a rate-determined state by a surface reaction. The nanolaminate-structure SrO/TiO films are formed by alternately laminating one or more and 20 or less SrO molecular layers and one or more and 20 or less TiO molecular layers at 150° C. or more and 400° C. or less and at 10 Torr or more and the atmospheric pressure or less. This makes it possible to obtain the nanolaminate-structure SrO/TiO films with a high permittivity and a high coverage and with no occurrence of crystalline foreign substance.

Abstract: The invention is characterized by attaining a lower dielectric constant and including an inorganic dielectric film which is formed on the surface of a substrate and has a cyclic porous structure having a pore ratio of 50% or higher.

Abstract: A semiconductor device includes a substrate having a trench, a liner layer pattern on sidewalls and a bottom surface of the trench, the liner layer pattern including a first oxide layer pattern and a second oxide layer pattern, a diffusion blocking layer pattern on the liner layer pattern, and an isolation layer pattern in the trench on the diffusion blocking layer pattern.

Abstract: An insulating film according to an embodiment of the present invention has Chemical Formula 1 wherein the Rs are equal to or different from each other, m is an integer, the Rs have Chemical Formula 2: R=R1R2R3,??(2) and R1, R2, and R3 in the Chemical Formula 2 are one selected from Chemical Formulae 3, 4 and 5, respectively (n is an integer):

Abstract: A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.

Abstract: A semiconductor substrate in a state that an inter-layer insulation film is formed is loaded in a chamber, air in the chamber is purged by introducing a large amount of a nitrogen gas in the chamber, and an atmospheric gas in the chamber is substituted with a nitrogen gas. After that, UV cure is performed by introducing a small amount of an oxygen gas adjusted to an atmospheric pressure or a little more positive pressure in the chamber by nitrogen purge. For the introduction of an oxygen gas, an oxygen gas is introduced while controlling the flow rate by using a flow meter, and adjustment is performed using the flow meter so that the oxygen concentration in the chamber becomes a constant value in the range of 5 ppm to 400 ppm.

Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Abstract: The present invention relates to a coating composition for insulating film production, a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same, and more particularly to a coating composition for insulating film production having a low dielectric constant and that is capable of producing an insulating film with superior mechanical strength (elasticity), a preparation method of a low dielectric insulating film using the same, a low dielectric insulating film for a semiconductor device prepared therefrom, and a semiconductor device comprising the same. The coating composition of the present invention comprises an organic siloxane resin having a small molecular weight, and water, and significantly improves low dielectricity and mechanical strength of an insulating film.

Abstract: A semiconductor device has a semiconductor substrate having first and second surface, a first resin film formed on the first surface of the semiconductor substrate and a second resin film formed on the second surface of the semiconductor substrate. A projection electrode or an interconnection is formed on the first surface of the semiconductor substrate, the second resin film is made of low elastic resin which is capable of absorbing an impact applied to the second surface of the semiconductor substrate and the second resin film is thinner than the semiconductor substrate.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.

Abstract: In order to determine the dielectric constant of a layer deposited on a semiconductor wafer (2), the density of the layer is obtained. To obtain that density, the wafer (2) without the layer is weighed in a weighing chamber (4) in which a weighing pan (7) supports the wafer on a weighing balance. The weight of the wafer is determined taking into account the buoyancy exerted by the air on the wafer (2). Then the layer is deposited on the wafer (2) and the weighing operation repeated. Alternatively a reference wafer may be used. If the material of the layer is known, the weight of the layer can be used to derive its density using a thickness measurement. Alternatively, if the density is known, the thickness can be obtained.

Abstract: A method is disclosed for inhibiting oxygen and moisture penetration of a device comprising the steps of depositing a tin phosphate low liquidus temperature (LLT) inorganic material on at least a portion of the device to create a deposited tin phosphate LLT material, and heat treating the deposited LLT material in a substantially oxygen and moisture free environment to form a hermetic seal; wherein the step of depositing the LLT material comprises the use of a resistive heating element comprising tungsten. An organic electronic device is also disclosed comprising a substrate plate, at least one electronic or optoelectronic layer, and a tin phosphate LLT barrier layer, wherein the electronic or optoelectronic layer is hermetically sealed between the tin phosphate LLT barrier layer and the substrate plate. An apparatus is also disclosed having at least a portion thereof sealed with a tin phosphate LLT barrier layer.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the low k stress liner from compressive to tensile. The use of such a tensile, low k stress liner improves electron mobility in nFET devices.