Abstract: A semiconductor memory device capable of being electrically written and erased comprising a floating gate, wherein, a silicon nitride, silicon oxinitride, aluminum oxide, or silicon carbide film is incorporated between the drain region and the floating gate.

Abstract: A field emission device including an electron emitter and a peripherally disposed gate extraction electrode defining a free space region therebetween. The device has an insulating layer substantially isolating the gate extraction electrode from the free space region. The device prevents damaging arc discharge between the electron emitter and gate extraction electrode because of the improved insulation and provides an additional mechanism for electric field enhancement.

Abstract: A structure is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Abstract: Diamond is used as a dielectric layer to separate the metalization layers multichip module substrates. The diamond has use for both electrical and thermal conduction. Such multichip module substrates may have a diamond base, or a base constructed from silicon, aluminum nitride, molybdenum, or any other material supportive of the nucleation and growth of diamond films. The metalization may be molybdenum or other conductor supportive of the nucleation and growth of diamond films. Using diamond as an interlayer dielectric in a multichip system permits a significant increase in the amount of power that can be dissipated by the system. The diamond does not obstruct the system's metalization, so that routing density can be increased and interconnection length may be decreased, enhancing host chip operation.

Abstract: A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit.

Abstract: There is interposed a buffer film composed of IIa group fluoride and having characteristics of orientation to a surface direction (111), in which mismatching in lattice constant with a crystal element of a semiconductor substrate is large and mismatching in lattice constant with IV-VI group compound ferroelectric substance is small, between the semiconductor substrate having a surface direction (100) and a ferroelectric gate film comprising the IV-VI group compound ferroelectric substance and having characteristics of polarization to the surface direction (111). Since the buffer film is an orientation film in the direction of (111) without influenced by a crystal element of the semiconductor substrate serving as a base material, the ferroelectric gate film can be oriented in the direction of (111) which is the same as the direction of polarization of the ferroelectric substance.

Abstract: Disclosed herein is a semiconductor pressure sensor which can improve a withstand voltage across piezoresistance and interconnection layers and a semiconductor substrate. In this semiconductor pressure sensor, a plurality of dot seeds, which are regions for serving as seed crystals for growing monocrystals, are arranged to enclose the piezoresistance, and the interconnection layer is formed to pass through a clearance between adjacent ones of the dot seeds.

Abstract: A non-volatile semiconductor memory providing a semiconductor substrate including source and drain diffusion regions and a gate electrode, and an insulating film which is at least provided on the semiconductor substrate just below the gate electrode and has a smaller dielectric breakdown strength on the source side than on the drain side, wherein the insulating film is comprised of a laminated film having a multilayer structure on the drain side and a single-layer film or multilayer film which is broken down at a smaller voltage on the source side than on the drain side, and a predetermined voltage is applied to break down the single-layer film or multilayer film on the source side, so that data can electrically be written only once.

Abstract: A thin film transistor is used as a load transistor in a memory cell in a SRAM. A load thin film transistor is arranged on an interlayer insulating layer on the surface of a silicon substrate. A silicon layer in which source/drain regions of the thin film transistor are formed is covered with an oxidation preventing film. An interlayer insulating layer which is to be subject to high temperature reflow processing is formed on the surface of the oxidation preventing film. The oxidation preventing film is formed of polycrystalline silicon, amorphous silicon, silicon nitride, or the like and formed on the silicon layer in the thin film transistor directly or through an insulating layer to cover the surface of the silicon layer.

Abstract: The present invention is mainly characterized by providing an even surface of an interlayer insulating film for insulating and isolating an upper interconnection and a lower interconnection from each other. A lower interconnection layer is provided on a semiconductor substrate, having a pattern of stepped portions. A silicon type insulating film is provided on the semiconductor substrate so as to cover the lower interconnection layer. A silicon ladder resin film is filled in recessed portions of the surface of the silicon type insulating film for making even the surface of the silicon type insulating film. An upper interconnection layer electrically connected to the lower interconnection layer through a via hole is provided on the silicon type insulating film. The silicon ladder resin film has the structural formula: ##STR1## where R.sub.1 is at least one of a phenyl group and a lower alkyl group, R.sub.2 is at least one of a hydrogen atom and a lower alkyl group, and n is an integer of 20 to 1000.

Abstract: A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.

Abstract: A semiconductor device comprises a semiconductor substrate, a first insulation film formed on the semiconductor substrate, a metal film for forming a bonding pad on the first insulation film, and a second insulation film which is formed between the first insulation film and the bonding pad and which is stiffer than the first insulation film.

Abstract: A gate insulating layer, which is formed on a channel region of a semiconductor substrate and interposed between the semiconductor substrate and a gate electrode, consists of a first part and a second part adjoining each other. The first part includes an oxide lower layer and a nitride upper layer, and a second part includes a nitride lower layer and an oxide upper layer.

Abstract: A semiconductor device having a protective insulating film is disclosed. This semiconductor device includes a semiconductor substrate, and an interconnection pattern provided on said semiconductor substrate and electrically connected with said elements. A silicon-oxy-nitride film is provided on said semiconductor substrate so as to cover said interconnection pattern. The silicon-oxy-nitride film is deposited in accordance with a chemical vapor deposition Method using plasma, using a mixture gas including organic silane and a nitriding gas and has therefore superior step coverage. The silicon-oxy-nitride film has a superior barrier characteristic to moisture coming in from the outside. A semiconductor device superior in reliability such as moisture resistance is thus obtained.

Abstract: A light-emitting diode having a structural arrangement that permits efficient external emission of light emitted from the peripheral wraparound portion of the diffusion region.

Abstract: A semiconductor device includes a first substrate made of a semiconductor, a first insulator layer which is formed on the first substrate, second substrate made of a semiconductor and formed on the first insulator layer, a trench which extends from a top surface of the second substrate to at least a part of the first insulator layer, and a second insulator layer which substantially defines a side wall of the trench.

Abstract: A CCD imager wherein signal charge can be transferred at a high speed and smears can be minimized without employing a complicated wiring configuration. The CCD imager comprises a transfer electrode formed from a semiconductor layer, a light intercepting film formed from a first layer metal film on the transfer electrode, and a shunt wiring film formed from a second layer metal film on the first layer metal film. The transfer electrode and the shunt wiring film are electrically connected to each other by way of the light intercepting film. Also an improved CCD imager of the frame interline type is disclosed wherein a storage section is improved in light intercepting performance to prevent possible occurrence of smears at the storage section with a simplified configuration of wiring in the storage section.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a field insulation film formed on a surface of the semiconductor substrate by a selective thermal oxidation process employing an oxidation-resistant mask whereby first and second groups of openings are formed therein for exposing the substrate at predetermined locations respectively corresponding to first and second active regions and relative to which first and second groups of contact holes are to be formed.

Abstract: An integrated circuit inductor is disclosed which can be fabricated by adding simple follow-on steps to standard fabrication line processes. In a preferred embodiment, standard CMOS technology is used to fabricate a multi-turn coil having its axis normal to the layers of oxide, polysilicon, and metal which form the coil. For a coil 100 microns on a side, an inductance on the order of 10 nH can be achieved. By including a magnetic core in the design using the disclosed procedure, this value can be increased to as high as 0.1 mH. Thus, inductor values ranging from 0.001 mH-0.1 mH can be physically implemented as integrated, highly-miniaturized CMOS designs for analog operation in the range of approximately 1-100 MHz.

Abstract: A silicon wafer comprising a substrate of single crystal silicon, a silicon oxide film 1 to 8 .ANG. in thickness formed on one surface of said substrate, and a polysilicon layer formed on said silicon oxide film and possessing an excellent gettering ability, is prepared by oxidizing single crystal silicon, thereby forming a silicon oxide film 1 to 8 .ANG. in thickness on said surface, and exposing said silicon oxide film to a gaseous silane at an elevated temperature, thereby forming a polysilicon layer on said silicon oxide film.