Multiple Layers Patents (Class 257/635)
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Patent number: 5874783Abstract: A semiconductor device includes connector leads which have an offset portion supported by the primary surface of a semiconductor chip on which electronics circuitry is formed into an integrated circuit. The offset portion is disposed near the contact pads for connecting the electronics circuitry. The remaining portion of the connector leads far from the contact pads is spaced from the primary surface by an adhesive strip of electrically insulative material. Bonding wires connect the connector leads to the contact pads. The total thickness of the package is reduced to accomplish a thinner and flatter semiconductor device.Type: GrantFiled: July 25, 1997Date of Patent: February 23, 1999Assignee: Oki Electric Industry Co., Ltd.Inventor: Etsuo Yamada
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Patent number: 5874777Abstract: There is provided a semiconductor device high in speed and in reliability by formation of interlayer dielectric films capable of rapidly transmitting heat as generated at wiring lines and yet less in capacitance.The semiconductor device of the present invention has multi-layered low-resistance wiring lines such as metal layers as stacked or laminated on a top surface and/or a bottom surface of a conductive substrate with a first dielectric material being sandwiched between adjacent ones thereof, featured in that said first dielectric material between said low-resistance wiring layers has a through-hole formed therein, and that said through-hole comprises a hole (through-hole: TH) filled with at least a conductive material, and a hole (dummy hole; DH) filed with a second dielectric material having thermal conductivity greater than that of said first dielectric material.Type: GrantFiled: December 2, 1996Date of Patent: February 23, 1999Assignee: Tadahiro OhmiInventors: Tadahiro Ohmi, Kazuo Tsubouchi, Toshiyuki Takewaki
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Patent number: 5864172Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.Type: GrantFiled: August 13, 1996Date of Patent: January 26, 1999Assignee: LSI Logic CorporationInventors: Ashok K. Kapoor, Nicholas F. Pasch
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Patent number: 5850102Abstract: This invention is related to a metallization of Cu.The semiconductor device comprises a first insulating layer having a groove in a surface thereof, a second insulating layer on a surface of the groove, made of a material having a low density of crystal defects in comparison with that of the first insulating layer, and a wiring layer buried in the groove, surrounded by the second insulating layer.Type: GrantFiled: April 2, 1997Date of Patent: December 15, 1998Assignee: Kabushiki Kaisha ToshibaInventor: Tadashi Matsuno
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Patent number: 5847444Abstract: A semiconductor device has a memory cell area which contains a component having a height and a peripheral circuit area free of a component having a height. The first area includes a interlayer insulating film comprising a first interlayer film as an uppermost insulating film. The second area includes an interlayer insulating film comprising the first interlayer film and a second interlayer film disposed directly on the first interlayer film and having a chemical mechanical polishing rate greater than the first interlayer film. The interlayer insulating film in the memory cell area has a surface higher than the interlayer insulating film in the peripheral circuit area.Type: GrantFiled: August 30, 1996Date of Patent: December 8, 1998Assignee: NEC CorporationInventor: Yasushi Yamazaki
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Patent number: 5847460Abstract: A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening.Type: GrantFiled: December 19, 1995Date of Patent: December 8, 1998Assignee: STMicroelectronics, Inc.Inventors: Fu-Tai Liou, Mehdi Zamanian
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Patent number: 5841186Abstract: Composite TiO.sub.2 /Ta.sub.2 O.sub.5 films by in-situ sequential CVD deposition are presented for a storage capacitor of a three-dimensional cell in DRAM applications. The capacitor with the Ta.sub.2 O.sub.5 /TiO.sub.2 /Ta.sub.2 O.sub.5 alternating layer structure has comparable leakage current density and higher capacitance per unit area as compared to a capacitor with Ta.sub.2 O.sub.5 and TiO.sub.2 single layer structures.Type: GrantFiled: August 19, 1997Date of Patent: November 24, 1998Assignee: United Microelectronics Corp.Inventors: Shi-Chung Sun, Tsai-Fu Chen
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Patent number: 5825078Abstract: This invention relates to integrated circuits which are protected from the environment. Such circuits are hermetically sealed by applying additional ceramic layers to the primary passivation.Type: GrantFiled: September 23, 1992Date of Patent: October 20, 1998Assignee: Dow Corning CorporationInventor: Keith Winton Michael
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Patent number: 5821582Abstract: Embodiments according to the present invention provide tamper resistant structures which make it more difficult to reverse engineer integrated circuits. In one embodiment, a tamper resistant structure on a passivation layer leaves portions of the passivation layer exposed. Mechanical or chemical removal of the tamper resistant structure damages exposed portions of the passivation layer and makes reverse engineering difficult. Other embodiments of the tamper resistant structure include patterned and unpatterned structures containing hard materials, chemically resistant materials, amalgams, fibrous materials, and/or meshes attached to a passivation layer. Tamper resistant structures can also be provided between layers of the active circuitry.Type: GrantFiled: June 7, 1995Date of Patent: October 13, 1998Assignee: National Semiconductor Corp.Inventor: Keith E. Daum
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Patent number: 5811872Abstract: A semiconductor device includes an interlevel film constituted by a first dielectrics film containing dangling bonds and a bonded group of Si and hydrogen, and a second dielectrics film formed on the first dielectrics film.Type: GrantFiled: January 31, 1996Date of Patent: September 22, 1998Assignee: Nippon Telegraph and Telephone CorporationInventors: Katsuyuki Machida, Katsumi Murase, Nobuhiro Shimoyama, Toshiaki Tsuchiya, Junichi Takahashi, Kazushige Minegishi, Yasuo Takahashi, Hideo Namatsu, Kazuo Imai
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Patent number: 5808366Abstract: High speed integrated circuits are designed and fabricated by taking into account the capacitive loading on the integrated circuit by the integrated circuit potting material. Line drivers may be sized to drive conductive lines as capacitively loaded by the potting material. Repeaters may be provided along long lines, to drive the lines as capacitively loaded by the potting material. Intelligent drivers may sense the load due to the potting material and drive the lines as capacitively loaded by the potting material. The thickness of the passivating layer on the outer conductive lines may also be increased so as to prevent the potting material from extending between the conductive lines. High speed potted integrated circuits may thereby be provided.Type: GrantFiled: August 9, 1996Date of Patent: September 15, 1998Assignee: Samsung Electronics Co., Ltd.Inventor: Minkyu Song
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Patent number: 5804869Abstract: A semiconductor structure (10) uses a clamp (16) disposed at an edge (27) of a dielectric structure (14) in a semiconductor device. The clamp substantially reduces the separation or peeling of the dielectric structure or layer away from the underlying semiconductor material (20,24). The clamp also provides the benefit of protecting the interface between the dielectric layer and the underlying semiconductor material from chemical or moisture attack, either during later processing or after final manufacture. Such chemical or moisture attack and internal film stress are factors leading to separation of the dielectric film from the underlying semiconductor material. The clamp is useful, for example, in preventing separation of silicon nitride or oxide passivation from gallium arsenide substrates in power rectifier diodes.Type: GrantFiled: March 31, 1997Date of Patent: September 8, 1998Assignee: Motorola, Inc.Inventors: Peyman Hadizad, Ali Salih, John Robert Bender, John David Moran
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Patent number: 5789805Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer.Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the is surface of the insulating layer, in order to use a portion of the multilayer wing substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.Type: GrantFiled: November 18, 1996Date of Patent: August 4, 1998Assignee: Hitachi, Ltd.Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
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Patent number: 5786624Abstract: A semiconductor device and method having a low-permittivity material between closely-spaced leads in order to decrease unwanted capacitance, while having a more structurally strong dielectric between widely-spaced leads where capacitance is not as critical. A metal layer 14 is deposited on a substrate 12 of a semiconductor wafer 10, where the metal layer 14 has a first region 15 and a second region 17. An insulating layer 39 is deposited on the metal layer, and the insulating layer 39 is patterned with a conductor pattern of widely-spaced leads and closely-spaced leads. Widely-spaced leads 16 are formed in the first region 15 of the metal layer 14. At least adjacent portions of closely-spaced leads 18 are formed in the second region 17 of the metal layer 14. A low-permittivity material 34 is deposited between adjacent portions of the closely-spaced leads 18. A structural dielectric layer 26 is deposited between at least the widely-spaced leads.Type: GrantFiled: February 28, 1997Date of Patent: July 28, 1998Assignee: Texas Instruments IncorporatedInventors: Robert H. Havemann, Richard A. Stoltz
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Patent number: 5757064Abstract: A structure for a semiconductor device includes a plurality of memory cell areas, a multilayer interconnection structure including an interfacial insulating film and connecting the plurality of memory cell areas, the multilayer interconnection structure being insulated and planarized by the interfacial insulating film, and peripheral circuits adjacent to the plurality of memory cell areas, the peripheral circuits intersecting at a portion, wherein the multilayer interconnection structure includes an inflow-preventing layer for preventing an inflow of the interfacial insulating film at the portion where the peripheral circuits intersect.Type: GrantFiled: June 13, 1996Date of Patent: May 26, 1998Assignee: LG Semicon Co., Ltd.Inventor: Ki Gak Hong
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Patent number: 5753967Abstract: Submicron contacts/vias and trenches are provided in a dielectric layer by forming an opening having an initial dimension and reducing the initial dimension by depositing a second dielectric material in the opening.Type: GrantFiled: February 13, 1997Date of Patent: May 19, 1998Assignee: Advanced Micro Devices, Inc.Inventor: Ming-Ren Lin
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Patent number: 5753934Abstract: A multilayer thin film of the invention has an oxide thin film formed on a semiconductor single crystal substrate, and the oxide thin film includes at least one epitaxial thin film composed mainly of zirconium oxide or zirconium oxide stabilized with a rare earth metal element (inclusive of scandium and yttrium). Included is an oriented thin film formed on the oxide thin film from a dielectric material of perovskite or tungsten bronze type with its c-plane unidirectionally oriented parallel to the substrate surface. Consequently, there are provided a perovskite oxide thin film of (001) orientation, a substrate for an electronic device comprising the thin film, and a method for preparing the thin film.Type: GrantFiled: September 7, 1995Date of Patent: May 19, 1998Assignee: TOK CorporationInventors: Yoshihiko Yano, Takao Noguchi
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Patent number: 5738942Abstract: Provided is a process for producing a semiconductor silicon wafer by which an intrinsic gettering effect can be improved and at the same time the top side can be made free from faults. A silicon ingot is produced and sliced to obtain silicon wafers. Then, a polycrystal silicon depositing film is formed on one side of a silicon wafer, which is subjected to a heat treatment in an inert gas, a reducing gas or a mixture thereof to discharge oxygen from the vicinity of the other side. Alternatively, after discharging oxygen from the silicon wafer by a heat treatment, a polycrystal silicon depositing film may be formed on one side of the silicon wafer.Type: GrantFiled: December 29, 1995Date of Patent: April 14, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Atsuko Kubota, Masakatu Kojima, Norihiko Tsuchiya, Shuichi Samata, Masanori Numano, Yoshihiro Ueno
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Patent number: 5739579Abstract: A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filed with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.Type: GrantFiled: September 10, 1996Date of Patent: April 14, 1998Assignee: Intel CorporationInventors: Chien Chiang, David B. Fraser
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Patent number: 5734188Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.Type: GrantFiled: July 1, 1996Date of Patent: March 31, 1998Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
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Patent number: 5717232Abstract: A semiconductor device has an active layer formed on a semiconductor substrate with different types of junctions, a source region, a drain region, a T-shaped gate electrode in which the cross-sectional area of the upper surface is larger than that of the lower surface, a first dielectric layer covering at least the exposed surface of the active layer, and the gate electrode, and a second dielectric layer enclosing the first dielectric layer. In the device, when the specific inductive capacities of the first and second dielectric layers are .epsilon.(1) and .epsilon.(2) respectively .epsilon.(1)<.epsilon.(2) and the water absorption ratio of the first dielectric layer is greater than the water absorption ratio of the second dielectric layer.Type: GrantFiled: April 16, 1996Date of Patent: February 10, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiko Inoue, Souichi Imamura, Masanori Ochi, Shigehiro Hosoi, Toru Suga, Takashi Kimura
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Patent number: 5698894Abstract: A passivation structure is formed using two passivation layers and a protective overcoat layer using two masking steps. The first passivation layer is formed over the wafer and openings are provided to expose portions of the pads for testing the device and fusible links. After testing and laser repair, a second passivation layer is formed over the wafer followed a deposit of the protective overcoat. The protective overcoat is patterned and etched, exposing the pads. The remaining portions of the protective overcoat are used as a mask to remove portions of the second passivation layer overlying the pads. Leads are then attached to pads and the devices are encapsulated for packaging.Type: GrantFiled: October 28, 1996Date of Patent: December 16, 1997Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Frank Randolph Bryant, Abha Rani Singh
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Patent number: 5679982Abstract: A method of forming a barrier layer for preventing the diffusion of a metal interconnect through an interlayer dielectric of an integrated circuit and to act as an etch stop. A thin metal layer is formed on the interlayer dielectric and then oxidized to form a metal-oxide barrier layer.Type: GrantFiled: August 13, 1996Date of Patent: October 21, 1997Assignee: Intel CorporationInventor: Donald S. Gardner
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Patent number: 5672907Abstract: A semiconductor device in which the elution quantity of boron and phosphorus from a BPSG film in a process of washing a wafer is controlled low so as to realize sufficient flattening and in which a reflow processing temperature is lowered by increasing concentrations of boron and phosphorus in the BPSG film. A first BPSG film in which the boron concentration is 3.5 wt % to 4.5 wt % and the phosphorus concentration is 5.5 wt % to 6.5 wt % is formed through a polysilicon wiring layer on a semiconductor substrate by a CVD method using an inorganic material source such as SiH.sub.4, B.sub.2 H.sub.6, PH.sub.3, O.sub.2 or an organic material source such as TEOS, TMOP, TMB, or O.sub.3. A gas flow rate is then changed so as to form a second BPSG film having a boron concentration of 2.0 wt % to 3.0 wt % and a phosphorus concentration of 5.5 wt % to 6.5 wt %.Type: GrantFiled: March 19, 1996Date of Patent: September 30, 1997Assignee: Nippon Steel CorporationInventor: Yasuo Kasagi
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Patent number: 5665995Abstract: A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 .ANG.. Glass insulation having a thickness of about 3000 .ANG. or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 .ANG., precede activation of the impurity ions by annealing the device at less than or equal to about 520.degree. C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm.sup.2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.Type: GrantFiled: April 27, 1995Date of Patent: September 9, 1997Assignee: United Microelectronics CorporationInventors: Chen-Chiu Hsue, Shing-Ren Shev, Kuan-Cheng Su, Chen-Hui Chung
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Patent number: 5656826Abstract: An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during the same patterning process.Type: GrantFiled: March 28, 1995Date of Patent: August 12, 1997Assignee: Seiko Epson CorporationInventors: Toshiyuki Misawa, Hiroyuki Oshima
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Patent number: 5656852Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to fore a top surface with rounded comers on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.Type: GrantFiled: June 7, 1995Date of Patent: August 12, 1997Assignee: Texas Instruments IncorporatedInventors: Yasushiro Nishioka, Scott R. Summerfelt, Kyung-ho Park, Pijush Bhattacharya
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Patent number: 5646440Abstract: A semiconductor device having a base or main body on which conductive interconnects are formed. At least the surface of the base is insulative. A first dielectric film is formed so as to cover the conductive interconnects. A second dielectric film having a relative dielectric constant smaller than that of the first dielectric film is formed at least between the conductive interconnects. The thickness of the second dielectric film between the conductive interconnects is greater than the height of the conductive interconnects by 10-100% in the directions of the height and depth. Films made of a material of a low dielectric constant are formed over and under the conductive interconnects via the first dielectric film or equivalent films.Type: GrantFiled: September 27, 1995Date of Patent: July 8, 1997Assignee: Sony CorporationInventor: Toshiaki Hasegawa
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Patent number: 5631484Abstract: A method for forming a semiconductor device includes forming insulated gate regions (122,222) on a substrate (26) using a first photo-masking step, forming a base region (47) through an opening (143) between the insulated gate regions (122,222), and forming a source region (152) within the base region (47). Next, a protective layer (61) is formed and selectively patterned using a second photo-masking step to form an opening (62) within the first opening (143) and an opening (63) above one of the insulated gate regions (122). Next, a portion (66) of the substrate (26) and a portion (67) of the insulated gate region (122) are removed. Ohmic contacts (74,76) are then formed and patterned using a third photo-masking step. Additionally, a termination structure (81) is described.Type: GrantFiled: December 26, 1995Date of Patent: May 20, 1997Assignee: Motorola, Inc.Inventors: Hak-Yam Tsoi, Pak Tam, Edouard D. de Fresart
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Patent number: 5621241Abstract: A semiconductor device and process for making the same are disclosed which uses a dielectric stack to improve fabrication throughput, gap-fill, planarity, and within-wafer uniformity. A gap-fill dielectric layer 34 (which preferably contains an integral seed layer) is first deposited over conductors 22, 24, and 26. Layer 34 is preferably a high density plasma (HDP) silicon dioxide deposition which planarizes high aspect ratio conductors such as 24, 26 but does not necessarily planarize low aspect ratio conductors such as 22. A dielectric polish layer 40, which preferably polishes faster than the gap-fill layer may be deposited over layer 34. The polish layer may be formed, for example, by plasma chemical vapor deposition of TEOS. Finally, a chemical-mechanical polishing process is used to planarize the dielectric stack in a manner which requires a minimal polishing time and produces a highly planarized structure.Type: GrantFiled: June 7, 1995Date of Patent: April 15, 1997Assignee: Texas Instruments IncorporatedInventor: Manoj K. Jain
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Patent number: 5614761Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.Type: GrantFiled: September 5, 1995Date of Patent: March 25, 1997Assignee: Hitachi, Ltd.Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
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Patent number: 5598027Abstract: Disclosed herein is a semiconductor device, which can effectively prevent a lower insulating layer from formation of a recess resulting from etching during formation of a groove for connecting interconnection layers with each other. In this semiconductor device, a first etching prevention film is formed on a first interlayer insulating film, so that a second interlayer insulating film is formed on the first etching prevention film.Type: GrantFiled: December 21, 1995Date of Patent: January 28, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masazumi Matsuura
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Patent number: 5596218Abstract: A CMOS device is provided having a high concentration of nitrogen atoms at the SiO.sub.2 /Si interface reducing hot carrier effects associated with operating shorter devices at voltage levels typically used with longer devices. In one embodiment, the process for providing the CMOS device resistant to hot carrier effects makes use of a sacrificial oxide layer through which the nitrogen atoms are implanted and is then removed. Following removal of the sacrificial oxide layer, a gate oxide is grown giving a CMOS device having high nitrogen concentration at the SiO.sub.2 /Si interface. In an alternate embodiment, nitrogen atoms are implanted through the final gate oxide using an implantation energy which does not damage the oxide layer.Type: GrantFiled: October 18, 1993Date of Patent: January 21, 1997Assignee: Digital Equipment CorporationInventors: Hamid R. Soleimani, Brian Doyle, Ara Philipossian
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Patent number: 5585662Abstract: A breakable fuse element is incorporated in a semiconductor integrated circuit device, and is overlain by a multi-level insulating film structure having the lowest insulating film covering the breakable fuse element and a multi-level insulating sub-structure over the lowest insulating film, wherein an etching stopper is inserted between the lowest insulating film and the multi-level insulating film sub-structure so that an etching for a laser hole is exactly terminated at the etching stopper, thereby exactly controlling the remaining thickness over the breakable fuse element.Type: GrantFiled: June 21, 1994Date of Patent: December 17, 1996Assignee: NEC CorporationInventor: Hisao Ogawa
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Patent number: 5585663Abstract: An electrically programmable fuse buried under quartz and layers of polyimide with a specific structure to enhance its "thermal" capabilities. The fuse is designed to "blow" and cool off quickly so as not to cause damage to areas above and surrounding the fuse. A passivation layer is added above the fuse to act as a heat sink and absorb and redistribute the heat generated from one localized area to a broader and cooler area. The materials used for the fuse and the heat sink are selected to be compatible with both oxide and polyimide personalization schemes. Modeling of the fuse enables optimizing the characteristics of the fuse, particularly to transmit to the surface of the passivation layer the thermal wave created during programming of the fuse.Type: GrantFiled: August 4, 1995Date of Patent: December 17, 1996Assignee: International Business Machines CorporationInventors: Raschid J. Bezama, Dominic J. Schepis, Krishna Seshan
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Patent number: 5583369Abstract: Thin-film semiconductor devices such as TFTs (thin-film transistors) and methods of fabricating the same. TFTs are formed on an insulating substrate. First, a substantially amorphous semiconductor coating is formed on the substrate. A protective coating transparent to laser radiation is formed on the semiconductor coating. The laminate is irradiated with laser radiation to improve the crystallinity of the semiconductor coating. Then, the protective coating is removed to expose the surface of the semiconductor coating. A coating for forming a gate-insulating film is formed. Subsequently, gate electrodes are formed. Another method relates to fabrication of semiconductor devices such as TFTs on an insulating substrate. After forming a first coating consisting mainly of aluminum nitride, a second coating consisting principally of silicon oxide is formed. Semiconductor devices such as TFTs or semiconductor circuits are built on the second coating serving as a base layer.Type: GrantFiled: March 12, 1996Date of Patent: December 10, 1996Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hongyong Zhang, Yasuhiko Takemura
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Patent number: 5554884Abstract: A multilevel metallization is deposited on a microelectronic device base structure (40). The process includes depositing a glassy dielectric layer (48) of a thickness that is from about two to about three times as thick as the topography thickness (D) of the base structure (40). The glassy dielectric layer (48) is heated to a temperature above its glass transition temperature to flow the glassy dielectric layer (48). The glassy dielectric layer (48) is thinned to a preselected thickness, and a first patterned metallization layer (54) is deposited. The process further includes depositing an interlevel dielectric layer (58), dry etching the interlevel dielectric layer (58) to thin the interlevel dielectric layer (58) and, optionally, depositing additional interlevel dielectric layer (58') material to achieve a preselected thickness. A second patterned metallization layer (64) is deposited over the interlevel dielectric layer ( 58/58').Type: GrantFiled: January 27, 1995Date of Patent: September 10, 1996Assignee: Hughes Aircraft CompanyInventor: Warren F. McArthur
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Patent number: 5530294Abstract: A contact of a semiconductor device has an interlayer-insulating film sandwiched between upper and lower conductive line patterns, a conductive pad for electrically connecting the upper and lower conductive line patterns via a contact hole formed in the interlayer-insulating film to expose the lower conductive line pattern to the upper conductive line pattern, and a barrier material pattern formed on the upper conductive line pattern and conductive pad to partially overlap the conductive pad with the upper conductive line pattern, so that the lower and upper conductive line patterns on both sides of the interlayer-insulating film partially overlap with each other without damaging the lower conductive line pattern, thereby improving packing density of the semiconductor device. Also, a manufacturing method of the contact is provided.Type: GrantFiled: April 14, 1995Date of Patent: June 25, 1996Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Jae K. Kim
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Patent number: 5521409Abstract: A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002), typically of substantially uniform thickness, lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. In this case, the second polycrystalline segment extends over a scribe-line section of the termination area so as to be scribed during a scribing operation.Type: GrantFiled: December 22, 1994Date of Patent: May 28, 1996Assignee: Siliconix IncorporatedInventors: Fwu-Iuan Hshieh, Mike Chang, Jun W. Chen, King Owyang, Dorman C. Pitzer, Jan Van Der Linde
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Patent number: 5521424Abstract: The semiconductor device has a multilayer structure wherein a substantially pure silicon dioxide film containing substantially no fluorine atom and a silicon dioxide film containing fluorine atoms are sequentially laminated on a substrate. Etching rate of a silicon dioxide film depends on a fluorine concentration in the film, so that a suitable etch selectivity of the silicon dioxide film containing fluorine atoms from the substantially pure silicon dioxide film can be obtained to form an oxide trench used for a trench interconnection and a via-hole used for a via-plug. The oxide film containing fluorine atoms has as good a quality as the silicon dioxide film not containing impurities has, thereby obtaining a superior characteristic of the semiconductor device. Addition of fluorine atoms reduces a specific permittivity to thereby obtain a higher speed.Type: GrantFiled: December 22, 1994Date of Patent: May 28, 1996Assignee: NEC CorporationInventors: Kazuyoshi Ueno, Tetsuya Homma
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Patent number: 5517060Abstract: In a semiconductor device including at least two parallel conductive layers electrically isolated from each other and at least two parallel backing conductive layers opposing the two parallel conductive layers and electrically connected thereto via contact holes, a thickness of an insulating layer beneath one of the backing conductive layers is different from a thickness of an insulating layer beneath other adjacent backing conductive layers.Type: GrantFiled: August 2, 1994Date of Patent: May 14, 1996Assignee: NEC CorporationInventor: Makoto Kobayashi
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Patent number: 5506443Abstract: A multilayer insulating film of a semiconductor device, where the distributed quantity of carbon or fluorine is maximized at the interface between insulating films. The concentration of carbon present at the interface is 1.times.10.sup.20 atoms/cm.sup.3 or more.Type: GrantFiled: October 17, 1994Date of Patent: April 9, 1996Assignee: Fujitsu LimitedInventors: Yuji Furumura, Masahiko Doki, Hidetoshi Nishio
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Patent number: 5485035Abstract: A method for planarization of an integrated circuit. After a first conducting layer is deposited and patterned, a first insulating layer is deposited over the device. A planarizing layer is then deposited over the integrated circuit and etched back. Portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the device. A second insulating layer is then deposited over the integrated circuit, followed by a third insulating layer. A contact via is formed through the layers to expose a portion of the first conducting layer. A second conducting layer can now be deposited and patterned on the device to make electrical contact with the first conducting layer.Type: GrantFiled: December 28, 1993Date of Patent: January 16, 1996Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Yih-Shung Lin, Kuei-Wu Huang, Lun-Tseng Lu
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Patent number: 5477074Abstract: A CMOS integrated circuit uses self-aligned transistors combined with local planarization in the vicinity of the transistors so as allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer and underlying oxide layer are removed only in the area of the buried contact, while an overlying metal or polysilicon conductive layer contacts the upper surface of certain of the transistor gate structures, the topside insulating layer of which has been removed for this purpose.Type: GrantFiled: August 22, 1994Date of Patent: December 19, 1995Assignee: Paradigm Technology, Inc.Inventor: Ting-Pwu Yen
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Structure for microelectronic device incorporating low resistivity straps between conductive regions
Patent number: 5475266Abstract: A microelectronic device (10) provides decreased use of bar area to form contacts between a conductive strap (24) or interconnect and subsequent levels. The conductive strap comprises a conducting layer (130) and an overlying semiconducting layer (132). Connection to subsequent levels is made generally overlying substrate conductive areas such as a gate (14) and/or a moat (16). Connection to conductive sublayer (130) is accomplished by doping an overlying semiconductor sublayer (132). Any counter-doping of substrate conductive areas is blocked by an overlying well of dopant-masking (33) or sufficiently thick semiconducting (32) material.Type: GrantFiled: November 18, 1994Date of Patent: December 12, 1995Assignee: Texas Instruments IncorporatedInventor: Mark S. Rodder -
Patent number: 5468992Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wire bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer element. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, thereby making it possible to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.Type: GrantFiled: February 28, 1992Date of Patent: November 21, 1995Assignee: Hitachi, Ltd.Inventors: Nobuyasu Kanekawa, Hirokazu Ihara, Masatsugu Akiyama, Kiyoshi Kawabata, Hisayoshi Yamanaka, Tetsuya Okishima
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Patent number: 5468990Abstract: Embodiments according to the present invention provide tamper resistant structures which make it more difficult to reverse engineer integrated circuits. In one embodiment, a tamper resistant structure on a passivation layer leaves portions of the passivation layer exposed. Mechanical or chemical removal of the tamper resistant structure damages exposed portions of the passivation layer and makes reverse engineering difficult. Other embodiments of the tamper resistant structure include patterned and unpatterned structures containing hard materials, chemically resistant materials, amalgams, fibrous materials, and/or meshes attached to a passivation layer. Tamper resistant structures can also be provided between layers of the active circuitry.Type: GrantFiled: July 22, 1993Date of Patent: November 21, 1995Assignee: National Semiconductor Corp.Inventor: Keith E. Daum
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Patent number: 5465003Abstract: A new planarized device isolation structure within a semiconductor substrate is described. The device isolation structure comprises narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide, wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein the shallow trench is filled with a field oxide. The top surface of the narrow and wide device isolation regions and the semiconductor substrate is planarized.Type: GrantFiled: December 1, 1994Date of Patent: November 7, 1995Assignee: United Microelectronics CorporationInventors: Water Lur, Anna Su, Neng H. Shen
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Patent number: 5455453Abstract: A plastic package type semiconductor device is composed of a rolled metal substrate made of copper or copper alloy and an insulating film formed on the surface of the substrate. The film may be a single-layer film made of silicon oxynitride or a composite film formed by laminating a silicon oxide layer and a silicon oxynitride layer (or a silicon nitride layer). A semiconductor element is mounted on the film or on the exposed surface of the substrate. Other passive elements are provided on the film. After connecting these elements with bonding wires, the entire device is sealed in a resin molding. This device is thus free of cracks due to difference in thermal expansion between the film and the substrate, or peeling due to moisture absorption.Type: GrantFiled: July 1, 1992Date of Patent: October 3, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keizo Harada, Takao Maeda, Takatoshi Takikawa, Shunsuke Ban, Shosaku Yamanaka
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Patent number: 5451810Abstract: A method of forming a metal-to-metal antifuse. An antifuse stack 32 is formed comprising a first metal layer 16, an antifuse dielectric layer, and an etchstop layer. The etchstop layer may, for example, comprise an oxide layer 24 and an amorphous silicon layer 28. An antifuse via 44 is etched through an interlevel dielectric layer 36 to the antifuse stack 32. Next, a portion of the etchstop layer at the bottom of via 44 is removed. Finally, a second layer of metal 48 is deposited to fill antifuse via 44 and etched to form the desired interconnections.Type: GrantFiled: December 14, 1993Date of Patent: September 19, 1995Assignee: Texas Instruments IncorporatedInventors: Howard L. Tigelaar, George Misium