Abstract: Semiconductor devices and methods for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate, covering the substrate and device component. The contact dielectric layer includes a lower contact dielectric layer, an intermediate contact dielectric etch stop layer formed on the lower contact dielectric layer, and an upper contact dielectric layer formed on the intermediate contact dielectric etch stop layer. A contact opening is formed through the contact dielectric layer. The contact opening has an upper contact sidewall profile in the upper contact dielectric layer and a lower tapered contact sidewall profile in the lower contact dielectric layer. The tapered sidewall profile prevents shorting with the device component.

Abstract: A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate.

Abstract: A triple patterning method is provided. The method includes providing a substrate having a first region and a second region; and forming a first material layer. The method also includes forming a second material layer; and forming a plurality of core patterns on the second material layer in the first region. Further, the method includes forming sidewall spacers on side surfaces of the core patterns; and forming first patterns on the first material layer. Further, the method includes forming a third material layer on the first material layer and the first patterns; and forming second patterns on the third material layer in the first region and third patterns on the third material layer in the second region. Further, the method also includes forming fourth patterns; and forming triple patterns on the substrate in the first region and fifth patterns on the substrate in the second region.

Abstract: Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.

Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.

Abstract: A method of fabricating an optoelectronic integrated circuit substrate includes defining a photonic device region on a first substrate, the photonic device region having a photonic device formed thereon, forming a trench in the photonic device region on a top surface of the first substrate, the trench having a first depth, filling the trench with a dielectric, bonding a second substrate on the first substrate to cover the trench, and thinning the second substrate to a first thickness.

Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

Abstract: A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.

Abstract: A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.

Abstract: Methods of forming an insulative element are described, including forming a first metal oxide material having a first dielectric constant, forming a second metal oxide material having a second dielectric constant different from the first, and heating at least portions of the structure to crystallize at least a portion of at least one of the first dielectric material and the second dielectric material. Methods of forming a capacitor are described, including forming a first electrode, forming a dielectric material with a first oxide and a second oxide over the first electrode, and forming a second electrode over the dielectric material. Structures including dielectric materials are also described.

Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.

Abstract: The invention relates to a semiconductor apparatus and a method of fabrication for a semiconductor apparatus, whereby the semiconductor apparatus includes a semiconductor layer and a passivation layer arranged on a surface of the semiconductor layer and serving for passivating the semiconductor layer surface, whereby the passivation layer comprises a chemically passivating passivation sublayer and a field-effect-passivating passivation sublayer, which are arranged one above the other on the semiconductor layer surface.

Abstract: The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).

Abstract: A semiconductor chip (1) is flip-chip mounted on a circuit board (4) with an underfill resin (6) interposed between the semiconductor chip (1) and the circuit board (4) and a container covering the semiconductor chip (1) is bonded on the circuit board (4). At this point, the semiconductor chip (1) positioned with the underfill resin (6) interposed between the circuit board (4) and the semiconductor chip (1) is pressed and heated by a pressure-bonding tool (8); meanwhile, the surface of the underfill resin (6) protruding around the semiconductor chip (1) is pressed by the pressure-bonding tool (8) through a film (13) on which a surface unevenness is formed in a periodically repeating pattern, so that a surface unevenness (16a) is formed. The inner surface of the container covering the semiconductor chip (1) is bonded to the surface unevenness (16a) on the surface of the underfill resin.

Abstract: Provided are electrode-connecting structures or semiconductor devices, including a lower device including a lower substrate, a lower insulating layer formed on the lower substrate, and a lower electrode structure formed in the lower insulating layer, wherein the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer, and an upper device including an upper substrate, an upper insulating layer formed under the upper substrate, and an upper electrode structure formed in the upper insulating layer, wherein the upper electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer under a bottom surface thereof and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode is in direct contact with the upper metal electrode.

Abstract: A interconnect structure includes a conductive layer formed in a dielectric layer. An adhesion layer is formed between the dielectric layer and a substrate. The adhesion layer has a carbon content ratio greater than a carbon content ratio of the dielectric layer.

Abstract: Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.

Abstract: A resist underlayer composition, including a solvent, and an organosilane condensation polymerization product of hydrolyzed products produced from a compound represented by Chemical Formula 1, a compound represented by Chemical Formula 2, and a compound represented by Chemical Formula 3.

Abstract: A method of fabricating a passivation layer and a passivation layer for an electronic device. The passivation layer includes at least one passivation film layer and at least one nanoparticle layer. A first film layer is formed of an insulating matrix, such as aluminum oxide (Al2O3) and a first layer of a noble metal nanoparticle layer, such as a platinum nanoparticle layer, is deposited on the first film layer. Additional layers are formed of alternating film layers and nanoparticle layers. The resulting passivation layer provides a thin and robust passivation layer of high film quality to protect electronic devices, components, and systems from the disruptive environmental conditions.

Abstract: A semiconductor structure includes a substrate, a conductive feature over the substrate, a conductive plug structure contacting a portion of an upper surface of the conductive feature, a first etch stop layer over another portion of the upper surface of the conductive feature, and a second etch stop layer over the first etch stop layer. The first etch stop layer is a doped etch stop layer. The first etch stop layer is to function as an etch stop layer during a predetermined etching process for etching the second etch stop layer.

Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure having a first surface and a second surface. A first polymer having a high thermal conductivity and a high electrical resistivity is disposed on the first surface of the semiconductor stack structure. An exemplary method includes providing the semiconductor stack structure with the second surface in direct contact with a wafer handle. A next step involves removing the wafer handle to expose the second surface of the semiconductor stack structure. A following step includes disposing a second polymer having high thermal conductivity and high electrical resistivity directly onto the second surface of the semiconductor stack structure. Additional methods apply silicon nitride layers on the first surface and second surface of the semiconductor stack structure before disposing the first polymer and second polymer to realize the semiconductor device.

Abstract: A germanium-containing semiconductor surface is prepared for formation of a dielectric overlayer (e.g., a thin layer of high-k gate dielectric) by (1) removal of native oxide, for example by wet cleaning, (2) additional cleaning with hydrogen species, (3) in-situ formation of a controlled monolayer of GeO2, and (4) in-situ deposition of the dielectric overlayer to prevent uncontrolled regrowth of native oxide. The monolayer of GeO2 promotes uniform nucleation of the dielectric overlayer, but it too thin to appreciably impact the effective oxide thickness of the dielectric overlayer.

Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure attached to a wafer handle having at least one aperture that extends through the wafer handle to an exposed portion of the semiconductor stack structure. A thermally conductive and electrically resistive polymer substantially fills the at least one aperture and contacts the exposed portion of the semiconductor stack structure. One method for manufacturing the semiconductor device includes forming patterned apertures in the wafer handle to expose a portion of the semiconductor stack structure. The patterned apertures may or may not be aligned with sections of RF circuitry making up the semiconductor stack structure. A following step includes contacting the exposed portion of the semiconductor stack structure with a polymer and substantially filling the patterned apertures with the polymer, wherein the polymer is thermally conductive and electrically resistive.

Abstract: A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at least a surface of the passivation facing away from the wafer; and a mask layer disposed over at least a surface of the protection layer facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation, and wherein the mask layer includes a material that is selectively etchable to the material of the protection layer.

Abstract: The present application provides a p-type semiconductor device and a method for manufacturing the same. The structure of the device comprises: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack which is positioned on the channel region comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned on the channel region and the gate electrode is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the element Al is distributed in at least one of the upper surface, the bottom surface of the gate dielectric layer and the bottom surface of the gate electrode. The embodiments of the present invention are applicable for manufacturing MOSFET.

Abstract: Methods and systems for a distributed leaky wave antenna (LWA) are disclosed and may include communicating RF signals at one or more frequencies via distributed LWAs in a wireless communication device. The distributed LWAs may be integrated in one or more multi-layer support structures. The RF signals may be communicated at the one or more frequencies via a plurality of cavity heights in the distributed LWAs or via a plurality of sections of the distributed LWAs with different partially reflective surfaces. The distributed LWAs may be configured to transmit the RF signals at a desired angle from a surface of the multi-layer support structures. The distributed LWAs may include microstrip or coplanar waveguides where the plurality of cavity heights of the one or more distributed LWAs may be configured based on distances between conductive lines in the waveguides.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

Abstract: Film thickness variations are prevented in a plurality of single crystal semiconductor films separated at a fragile layer reliably and transferred to a base substrate.

Abstract: An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio.

Abstract: This description relates to a method of making a semiconductor device including forming an inter-level dielectric (ILD) layer over a substrate and forming a layer set over the ILD layer. The method further includes etching the layer set to form a tapered opening in the layer set and etching the ILD layer using the layer set as a mask to form an opening in the ILD layer. The opening in the ILD layer has a line width roughness (LWR) of less than 3 nanometers (nm). This description also relates to a semiconductor device including an inter-level dielectric (ILD) layer over a substrate; and a layer set over the ILD layer. The layer set has a tapered opening within the layer set. Etching the layer set comprises forming the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from 85-degrees to 90-degrees.

Abstract: A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer.

Abstract: Methods of forming a semiconductor device are provided. The methods include, for example, forming a low-k dielectric having a continuous planar surface, and, after forming the low-k dielectric, subjecting the continuous planar surface of the low-k dielectric to an ethylene plasma enhanced chemical vapor deposition (PECVD) treatment.

Abstract: A method of modifying a fluorinated polymer surface comprising the steps of depositing a first layer on at least a portion of the fluorinated polymer surface, the first layer comprising a first polymer, the first polymer being a substantially perfluorinated aromatic polymer; and depositing a second layer on at least a portion of the first layer, the second layer comprising a second polymer, the second polymer being an aromatic polymer having a lower degree of fluorination than said first polymer, whereby the second layer provides a surface on to which a substance having a lower degree of fluorination than the first polymer, e.g. a non-fluorinated substance is depositable.

Abstract: Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlOx) material relative to silicon oxide (SiOx) are provided.

Abstract: A manufacturing method for an organic electroluminescent device that includes an effectively optical area including display pixels for display and a dummy area surrounding the effectively optical area, the dummy area including dummy pixels not for display is provided. The manufacturing method includes coating a first composite material on a first portion in the effectively optical area, the first portion corresponding to one of the display pixels, and coating a second composite material separately from the coating of the first composite material, the second composite material being coated on a second portion of the dummy area, the second portion corresponding to one of the dummy pixels, the first composite material including a first organic electroluminescent material that is dissolved or dispersed in a solvent and the second composite material including a second organic electroluminescent material that is dissolved or dispersed in a solvent.

Abstract: The present invention describes a method including: providing a substrate; stacking interlevel dielectric layers over said substrate, and separating said interlevel dielectric layers with a dielectric separator layer.

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract: An electronic element includes a substrate; a patterned first electrically conductive layer on the substrate; a patterned second electrically conductive layer on the substrate; and a dielectric stack on the substrate. A portion of the first electrically conductive layer and a portion of the second electrically conductive layer overlap each other such that an overlap region is present. At least a portion of the dielectric stack is positioned in the overlap region between the patterned first electrically conductive layer and the patterned second electrically conductive layer. The dielectric stack includes a first inorganic thin film dielectric material layer and a second inorganic thin film dielectric material layer. The first inorganic thin film dielectric material layer and the second inorganic thin film dielectric material layer have the same material composition.

Abstract: A semiconductor device includes a semiconductor substrate, an insulator film that is arranged above the semiconductor substrate, a first passivation film that is arranged above the insulator film, a second passivation film that is arranged above the first passivation film, a stress relaxation layer that is arranged above the second passivation film, an organic coated film that is arranged above the stress relaxation layer, and a resin layer that is arranged above the organic coated film, wherein a Young's modulus of the stress relaxation layer is smaller than a Young's modulus of the organic coated film, and is smaller than a Young's modulus of the second passivation film.

Abstract: Various embodiments provide semiconductor devices including high-K dielectric layer(s) and fabrication methods. An exemplary high-K dielectric layer can be formed by providing a semiconductor substrate including a first region and a second region, and forming a first silicon oxide layer on the semiconductor substrate in the first region. The semiconductor substrate can then be placed in an atomic layer deposition (ALD) chamber to repeatedly perform a selective ALD process. The selective ALD process can include an etching process and/or a purging process in the ALD chamber. By repeatedly performing the selective ALD process, a first high-K dielectric layer can be selectively formed on the first silicon oxide layer in the first region, exposing the semiconductor substrate in the second region.

Abstract: To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconductor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.

Abstract: Systems and methods are presented for filling an opening with material of a high integrity. A material having properties in a first physical state suitable for formation of a hard mask layer and in a second physical state having properties facilitating removal of the former hard mask layer is utilized. Utilizing the material as a mask layer and subsequently removing the material enables a number of mask layers to be minimized in a subsequent filling operation (e.g., metallization). Material amenable to being in a first physical state and a second physical state is an optically reactive material. The optically reactive dielectric can comprise an element or compound which can act as an agent/catalyst in the optical conversion process along with any element or compound which can act as an accelerator for the optical reaction. Conversion can be brought about by exposure to electromagnetic radiation and/or application of thermal energy.

Abstract: A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to substantially transmit therethrough radiation within a different predetermined wavelength range. Additional methods of forming a semiconductor device structure are described. Semiconductor device structures are also described.

Abstract: An anti spacer process, which comprises: (a) providing a resist layer including a non-uniform shape; (b) coating a target layer above the resist layer; (c) providing anti spacer trenches (spa) between the target layer and the resist layer; and (d) connecting at least part of the anti spacer trenches (spa) together to isolate a first part of the target layer and a second part of the target layer.

Abstract: There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer.

Abstract: The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.

Abstract: A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.

Abstract: An embodiment of the disclosure provides a semiconductor device. The semiconductor device includes a plurality of metallization layers comprising a topmost metallization layer. The topmost metallization layer has two metal features having a thickness T1 and being separated by a gap. A composite passivation layer comprises a HDP CVD oxide layer under a nitride layer. The composite passivation layer is disposed over the metal features and partially fills the gap. The composite passivation layer has a thickness T2 about 20% to 50% of the thickness T1.

Abstract: A semiconductor of which a substance such as a semiconductor photocatalyst is uniformly coated on the surface thereof with a graphitic carbon film and a method of fabricating the same are disclosed. According to the inventive method, a graphitic carbon film having a thickness of 1 nm or less is uniformly formed on the surface of the semiconductor by performing hydrothermal synthesis and pyrolysis on glucose, so as to keep the original structure crystallinity of the semiconductor photocatalyst to be a support of the carbon film.