Abstract: The present invention is contemplated for providing a resistance switching device having a very small device size of approximately 20 nm×20 nm in its entirety, by taking advantage of a small diameter of a multilayered carbon nanotube or a multilayered carbon nanofiber per se, via a simpler manner that does not require any molecule inclusion step, with an excellent electric conductivity. Provided is a two-terminal resistance switching device, which has multilayered carbon nanofibers or multilayered carbon nanotubes disposed with a nano-scale gap width therebetween.

Abstract: Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.

Abstract: Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric.

Abstract: A semiconductor light emitting device package includes a base unit including a main body having electrical insulation properties and at least one pair of first and second through electrodes formed in the main body in a thickness direction thereof and formed of a semiconductor material, and a light emitting structure disposed on the base unit and including first and second conductivity type semiconductor layers and an active layer interposed there between. The manufacturing process thereof may be simplified, whereby a reduction in manufacturing costs and time may be achieved.

Abstract: A nonvolatile semiconductor memory device has a first wire, a second wire, and a memory cell electrically coupled to the first wire at one end and to the second wire at the other end. The memory cell has a resistance change layer to store information by changing a resistance value and a first electrode and a second electrode coupled to both ends of the resistance change layer and not containing a precious metal. The first electrode includes an outside electrode and an interface electrode formed between the outside electrode and the resistance change layer. The thickness of the interface electrode is less than the thickness of the outside electrode. The resistivity of the interface electrode is higher than the resistivity of the outside electrode. The resistance value of the first electrode is lower than the resistance value of the resistance change layer in a low resistance state.

Abstract: A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer. The hydrophobic polymer layer may prevent or reduce adsorption of impurities to transferred graphene, and a passivation layer may also prevent or reduce adsorption of impurities to a heat-treated graphene channel layer.

Abstract: Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.

Abstract: A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer. The hydrophobic polymer layer may prevent or reduce adsorption of impurities to transferred graphene, and a passivation layer may also prevent or reduce adsorption of impurities to a heat-treated graphene channel layer.

Abstract: Herein, provided are heavily doped colloidal semiconductor nanocrystals and a process for introducing an impurity to semiconductor nanoparticles, providing control of band gap, Fermi energy and presence of charge carriers. The method is demonstrated using InAs colloidal nanocrystals, which are initially undoped, and are metal-doped (Cu, Ag, Au) by adding a metal salt solution.

Abstract: A semiconductor device has a semiconductor body including a source region, a channel region, and a drain region, which are sequentially arranged in a longitudinal direction and are doped with the same type of impurity, a gate electrode including metal, and a gate dielectric layer interposed between the semiconductor body and the gate electrode.

Abstract: Methods for forming graphite-based structures, in which a substrate is patterned to form a plurality of elements on the substrate, are provided. A trench separates a first element from an adjacent element in the plurality. The surface of the first element and the surface of the trench (i) are respectively characterized by different first and second elevations and (ii) are separated by a side wall of the first element. Orthogonal projections of the surface of the first element and the surface of the trench onto a common plane are contiguous or overlapping. In the method, a first graphene layer on the entire first surface and a second graphene layer on the entire second surface are concurrently generated. The second graphene layer has a thickness that is less than a difference between the first and second elevations. Thus, a graphite-based structure having isolated first and second graphene layers is formed.

Abstract: A computer-implemented method for encryption and decryption using quantum computational model is disclosed. Such a method includes providing a model of a lattice having a system of non-abelian anyons disposed thereon. From the lattice model, a first quantum state associated with the lattice is determined. Movement of non-abelian anyons within the lattice is modeled to model formation of first and second quantum braids in the space-time of the lattice. The first quantum braid corresponds to first text. The second quantum braid corresponds to second text. A second quantum state associated with the lattice is determined from the lattice model after formation of the first and second quantum braids has been modeled. The second quantum state corresponds to second text that is different from the first text.

Abstract: A memory system is disclosed. The system comprises a memory layer between a first layer and a second layer, wherein the first layer and the second layer are configured to apply an electrical bias to the memory layer. In some embodiments the memory layer comprises nanodots made of a material selected from the group consisting of peptides and amino acids.

Abstract: An apparatus applies a carrier fluid to a semiconductor substrate. The carrier fluid carries nanoparticles. The positions of a plurality of particles in the carrier fluid are manipulated by applying an electric field, removing the carrier fluid from the substrate so as to leave the nanoparticles on the substrate, and sintering the nanoparticles to form a region.

Abstract: Silicon nanocrystal inks and films, and methods of making and using silicon nanocrystal inks and films, are disclosed herein. In certain embodiments the nanocrystal inks and films include halide-terminated (e.g., chloride-terminated) and/or halide and hydrogen-terminated nanocrystals of silicon or alloys thereof. Silicon nanocrystal inks and films can be used, for example, to prepare semiconductor devices.

Abstract: Provided are a compound semiconductor device and a manufacturing method thereof. A substrate and a graphene oxide layer are provided on the substrate. A first compound semiconductor layer is provided on the graphene oxide layer. The first compound semiconductor layer is selectively grown from the substrate exposed by the graphene oxide.

Abstract: A method of forming a nanowire structure is disclosed. The method comprises applying on a surface of carrier liquid a layer of a liquid composition which comprises a surfactant and a plurality of nanostructures each having a core and a shell, and heating at least one of the carrier liquid and the liquid composition to a temperature selected such that the nanostructures are segregated from the surfactant and assemble into a nanowire structure on the surface.

Abstract: A nanowire device includes a nanowire having differently functionalized segments. Each of the segments is configured to interact with a species to modulate the conductance of a segment. The nanowire is grown from a single catalyst and the segments include a first segment at a non-linear angle from a second segment.

Abstract: This invention provides a vertical organic transistor that can realize large current modulation and a reduction in production cost, and a method for manufacturing the vertical organic transistor. The vertical organic transistor comprises an upper electrode, a lower electrode, an organic semiconductor provided between both the electrodes, and an intermediate electrode provided within the organic semiconductor, the intermediate electrode being a layered continuous body comprising a continuous insulating metal compound and particulate metals distributed within the insulating metal compound.

Abstract: The present invention is related to ternary metal transition metal non-oxide nano-particle compositions, methods for preparing the nano-particles, and applications relating in particular to the use of said nano-particles in dispersions, electrodes and capacitors. The nano-particle compositions of the present invention can include a precursor which includes at least one material selected from the group consisting of alkoxides, carboxylates and halides of transition metals, the material including transition metal(s) selected from the group consisting of vanadium, niobium, tantalum, tungsten and molybdenum.

Abstract: An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.

Abstract: Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD (chemical vapor deposition) processes, layers comprising one or more electropositive metals, and semiconductor devices comprising layers comprising one or more electropositive metals. In embodiments of the invention, the layers are thin or ultrathin (films that are less than 100 {acute over (?)} thick) and or conformal films. Additionally provided are transistor devices, metal interconnects, and computing devices comprising metal layers comprising one or more electropositive metals.

Abstract: Semiconductor nano pressure sensor devices having graphene membrane suspended over cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

Abstract: An electronic component includes a first and a second electrode. A layer of nanoparticles is disposed between the first and second electrodes. The layer of nanoparticles includes an electrically conducting compound of a metal and an element of Main Group VI of the Periodic Table. A dimension of a majority of the nanoparticles ranges from 0.1 to 10 times a screening length of the electrically conductive compound. A dielectric layer has at least one common interface with at least a part of the nanoparticles.

Abstract: A nanoscale variable resistor including a metal nanowire as an active element, a dielectric, and a gate. By selective application of a gate voltage, stochastic transitions between different conducting states, and even length, of the nanowire can be induced and with a switching time as fast as picoseconds. With an appropriate choice of dielectric, the transconductance of the device, which may also be considered an “electromechanical transistor,” is shown to significantly exceed the conductance quantum G0=2e2/h.

Abstract: A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition.

Abstract: Sensors for detecting IR radiation, UV radiation, X-Rays, light, gas, and chemicals. The sensors herein incorporate freestanding carbon nanostructures, such as single-walled carbon nanotubes (“SWCNT”), atomically thin carbon sheets having a thickness of about between 1 atom and about 5 atoms (“graphene”), and combinations thereof. The freestanding carbon nanostructures are suspended above a substrate by a plurality of conductors, each conductor electrically connected to the carbon nanostructure. In one method of manufacture, a resonance chamber is formed under the carbon nanostructure by etching of the substrate, yielding a sensor wherein the resonance chamber is bounded by at least the substrate and the carbon nanostructure.

Abstract: According to example embodiments, a white light-emitting diode may be configured to emit white light without a phosphor. According to example embodiments, a white light-emitting diode may include a first semiconductor layer that includes a plurality of hexagonal-pyramid shape nanostructures that protrude upwards from an upper surface of the first semiconductor layer, at least two multi-quantum well layers that are sequentially stacked on the hexagonal-pyramid shape nanostructures; and a second semiconductor layer on the multi-quantum well layers. The at least two multi-quantum well layers may be configured to generate lights having different wavelengths, and white light may be generated by mixing the lights having different wavelengths.

Abstract: A photovoltaic device is provided. It comprises at least two electrical contacts, p type dopants and n type dopants. It also comprises a bulk region and nanowires in an aligned array which contact the bulk region. All nanowires in the array have one predominant type of dopant, n or p, and at least a portion of the bulk region also comprises that predominant type of dopant. The portion of the bulk region comprising the predominant type of dopant typically contacts the nanowire array. The photovoltaic devices' p-n junction would then be found in the bulk region. The photovoltaic devices would commonly comprise silicon.

Abstract: High quantum yield InP nanocrystals are used in the bio-technology, bio-medical, and photovoltaic, specifically IV, III-V and III-VI nanocrystal technological applications. InP nanocrystals typically require post-generation HF treatment. Combining microwave methodologies with the presence of a fluorinated ionic liquid allows Fluorine ion etching without the hazards accompanying HF. Growing the InP nanocrystals in the presence of the ionic liquid allows in-situ etching to be achieved. The optimization of the PL QY is achieved by balancing growth and etching rates in the reaction.

Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.

Abstract: This quantum dot structure has a matrix layer and a plurality of crystalline quantum dots provided spaced within the matrix layer. The quantum dots are provided at positions that differ in the direction of thickness of the matrix layer.

Abstract: A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion.

Abstract: Some embodiments include switches that have a graphene structure connected to a pair of spaced-apart electrodes. The switches may further include first and second electrically conductive structures on opposing sides of the graphene structure from one another. The first structure may extend from one of the electrodes, and the second structure may extend from the other of the electrodes. Some embodiments include the above-described switches utilized as select devices in memory devices. Some embodiments include methods of selecting memory cells.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: A method of manufacturing carbon cylindrical structures, as represented by carbon nanotubes, by growing them on a substrate using a chemical vapor deposition (CVD) method, comprising the steps of implanting metal ions to the substrate surface and then growing the carbon cylindrical structures using the metal ions as a catalyst. A method of manufacturing carbon nanotubes comprising a step of using nano-carbon material as seed material for growing carbon nanotubes is also disclosed. A biopolymer detection device comprising vibration inducing part for inducing vibration, binding part capable of resonating with the vibration induced by the vibration inducing part and capable of binding or interacting with a target biopolymer, and detection part for detecting whether or not the binding part have bound or interacted with the target biopolymer, is also disclosed.

Abstract: A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.

Abstract: A bond type flip-chip light-emitting structure and method of manufacturing the same. Firstly, form a positive electrode and a negative electrode on an epitaxy layer. Next, deposit an insulation layer on parts of the positive electrode and negative electrode, to expose respectively a positive electrode via hole and a negative electrode via hole. Then, form a bonded metal layer on the insulation layer, the positive electrode via hole, and the negative electrode via hole, so that the positive electrode and the negative electrode are on a same plane by means of the bonded metal layer. Finally, on a substrate, bond the first metal layer and the second metal layer onto the corresponding first bonded metal unit and the second bonded metal unit of the bonded metal layer, to form into shape, thus realizing a bond type flip-chip light-emitting structure.

Abstract: Methods for improving the temperature performance of AlInGaP based light emitters. Nitrogen is added to the quantum wells in small quantities. Nitrogen is added in a range of about 0.5 percent to 2 percent. The addition of nitrogen increases the conduction band offset and increases the separation of the indirect conduction band. To keep the emission wavelength in a particular range, the concentration of In in the quantum wells may be decreased or the concentration of Al in the quantum wells may be increased. The net result is an increase in the conduction band offset and an increase in the separation of the indirect conduction band.

Abstract: An optical device which can operate as a single photon emitter 1, comprising a three dimensional optical cavity 7 which spatially confines a photon to the order of the photon wavelength in all three dimensions. The cavity 7 is configured to define preferred emission direction for photons entering the cavity. A photon can be supplied to the cavity using a quantum dot 5. Strong coupling can occur between the cavity 7 and the quantum dot 5 which causes the formation of two hybridised modes. Switching on an off the coupling by irradiating the device with radiation having an energy equal to that of one of the hybridised modes allows the device to act as an optical switch.

Abstract: A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region.

Abstract: Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided.

Abstract: The present disclosure involves an apparatus. The apparatus includes a photonic die structure that includes a plurality of layers. A current blocking layer is embedded in one of the plurality of layers. The current blocking layer is a doped layer. The present disclosure also involves a method of fabricating a light-emitting diode (LED). As a part of the method, an LED is provided. The LED includes a plurality of layers. A patterned mask is then formed over the LED. The patterned mask contains an opening. A dopant is introduced through the opening to a layer of the LED through either an ion implantation process or a thermal diffusion process. As a result of the dopant being introduced, a doped current blocking component is formed to be embedded within the layer of the LED.

Abstract: Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate.

Abstract: A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair. First and second electrically conductive structures are laterally outward of the graphene structure and on opposing sides of the graphene structure from one another. Ferroelectric material is laterally between the graphene structure and at least one of the first and second electrically conductive structures. The first and second electrically conductive structures are configured to provide the switch into “on” and “off” states by application of an electric field across the graphene structure and the ferroelectric material. Other embodiments are disclosed, including components of integrated circuitry which may not be switches.

Abstract: The invention relates to nanowires which consist of or comprise semiconductor materials and are used for applications in photovoltaics and electronics and to a method for the production thereof. The nanowires are characterized in that they are obtained by a novel method using novel precursors. The precursors represent compounds, or mixtures of compounds, each having at least one direct Si—Si and/or Ge—Si and/or Ge—Ge bond, the substituents of which consist of halogen and/or hydrogen, and in the composition of which the atomic ratio of substituent:metalloid atoms is at least 1:1.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: Disclosed herein is a nanowire including silicon rich oxide and a method for producing the same. The nanowire exhibits excellent electrically conducting properties and optical characteristics, and therefore is effectively used in a variety of applications including, for example, solar cells, sensors, photodetectors, light emitting diodes, laser diodes, EL devices, PL devices, CL devices, FETs, CTFs, surface plasmon waveguides, MOS capacitors and the like.

Abstract: Nanorod and nanowire compositions are disclosed comprising copper indium selenide, copper indium gallium selenide, copper indium sulfide, or a combination thereof. Also disclosed are photovoltaic devices comprising the nanorod and/or nanowire compositions. Also disclosed are methods for producing the nanorod and nanowire compositions, and photovoltaic devices described herein.