Abstract: Disclosed is an interposer including a polyhedral body having first and second surfaces facing each other, a plurality of electric terminals formed on the first surface; and a plurality of vias extending through the first and second surfaces. In addition, a semiconductor package includes a printed circuit board having a plurality of electric contacts formed on an upper surface and an interposer having first and second surfaces facing each other, vias extending through the first and second surfaces, and first electric terminals formed on the first surface. The interposer is seated on the printed circuit board so that the vias correspond to the electric contacts.

Abstract: A method for fabricating a plurality of wafer level chip scale packages is revealed. A bumped wafer is laminated with a mold plate with a protection film placed thereon to partially embed the bumps of the wafer into the protection film and to form an underfill gap between the wafer and the protection film. By a first sawing step, the wafer fixed by the protection film is singulated into a plurality of chips having sides between the active surface and the back surface and also a filling gap is formed between the sides. Then, an encapsulant is formed on the protection film where the encapsulant fills the underfill gap through the filling gap to completely encapsulate the chips and the non-embedded portions of the bumps. By separating the encapsulant from the protection film and a second sawing step, the mold plate and the protection film are removed, and the encapsulant is singulated into a plurality of individual wafer level chip scale packages.

Abstract: A method for manufacturing a light-emitting case includes forming a PLED (Polymer Light Emitting Diode) device, disposing the PLED device into a mold, and utilizing the mold to sheathe the PLED device with transparent plastic material in an injection-molding manner. Since the mold has a cavity corresponding to a predetermined shape, the formed transparent plastic material has a geometric appearance corresponding to the predetermined shape.

Abstract: A method for manufacturing a light emitting device, includes: forming a first multilayer body including a first substrate, a first semiconductor layer provided on the first substrate and having a light emitting layer, and a first metal layer provided on the first semiconductor layer; forming a second multilayer body including a second substrate having a thermal expansion coefficient different from a thermal expansion coefficient of the first substrate, and a second metal layer provided on the second substrate; a first bonding step configured to heat the first metal layer and the second metal layer being in contact with each other; removing the first substrate after the first bonding step; and a second bonding step configured to perform, after the removing, heating at a temperature higher than a temperature of the first bonding step.

Abstract: In a CVD apparatus (111), a reforming process is performed on a porous low dielectric constant film containing silicon, by heating a semiconductor wafer W by a heater, introducing 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS), and performing heat treatment without applying a high frequency voltage. Then, in the same CVD apparatus (111), an insulation film having high density and hardness is formed on the porous low dielectric constant film, by heating the semiconductor wafer W, introducing TMCTS, and generating a plasma of a gas containing TMCTS while applying a high frequency voltage.

Abstract: A manufacturing method of a semiconductor device includes preparing a first semiconductor substrate having a first integrated circuit formed therein and including a plurality of first through substrate vias, and a second semiconductor substrate having a second integrated circuit formed therein and including a plurality of second through substrate vias, forming a solid-electrolytic layer on an upper surface of the first semiconductor substrate, mounting the second semiconductor substrate on the solid-electrolytic layer such that a lower surface of the second semiconductor substrate comes into contact with the solid-electrolytic layer, and applying a voltage between the plurality of first through substrate vias and the plurality of second through substrate vias, to form in the solid-electrolytic layer a plurality of connection electrodes, which are respectively connecting the plurality of second through substrate vias adjacent to the plurality of first through substrate vias to the plurality of first through su

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract: A method of forming a magnetoelectronic device includes forming a dielectric material (114) surrounding a magnetic bit (112), etching the dielectric material (114) to define an opening (122) over the magnetic bit (112) without exposing the magnetic bit (112), the opening (122) having a sidewall, depositing a blanket layer (132) of cladding material over the dielectric material (118), including over the sidewall, removing by a sputtering process the blanket layer (132) in the bottom of the opening (122) and the dielectric material (124) over the magnetic bit (112), and forming a conductive material (146) within the opening (122) to form a bit line (154). This process reduces errors caused by process irregularities such as edges of the bits (112) protruding and thereby causing defects in the cladding layer (132) formed thereover.

Abstract: A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.

Abstract: A magnetic tunnel junction storage element for a spin transfer torque magnetoresistive random access memory (STT-MRAM) bit cell includes a bottom electrode layer, a pinned layer adjacent to the bottom electrode layer, a dielectric layer encapsulating a portion of the bottom electrode layer and the pinned layer, the dielectric layer including sidewalls that define a hole adjacent to a portion of the pinned layer, a tunneling barrier adjacent to the pinned layer, a free layer adjacent to the tunneling barrier, and a top electrode adjacent to the free layer, wherein a width of the bottom electrode layer and/or the pinned barrier in a first direction is greater than a width of a contact area between the pinned layer and the tunneling barrier in the first direction. Also a method of forming an STT-MRAM bit cell.

Abstract: One embodiment of the present invention is a thin film transistor including a gate electrode formed on an insulating substrate, a gate insulator formed on the gate electrode, a drain electrode and a source electrode formed on the gate insulator, an oxide semiconductor pattern formed between the drain electrode and the source electrode, and a sealing layer formed on the oxide semiconductor pattern.

Abstract: A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.

Abstract: A semiconductor device 1 has a metallic base substrate 2 for heat-dissipating, a wiring board 3, a MOSFET 4 as a semiconductor element, externally leading terminals 5A, 5B, 5C, a casing 6 formed of a synthetic resin, a fixing resin 7, and a gel-like resin layer 8. On the metallic base substrate 2, the casing 6 is disposed to surround one ends of the externally leading terminals 5A, 5B, 5C and the MOSFET 4. The other ends of the externally leading terminals 5A, 5B, 5C are externally protruded from the casing 6, and terminal body portions 51A, 51B, 51C for coupling them are inserted in through hole portions 61A, 61B, 61c of the casing 6. The terminal body portions 51A, 51B, 51C and the through hole portions 61A, 61B, 61c are fixed with the fixing resin 7, and the gel-like resin layer 8 is formed at the lower part of the casing 6. A space 9 is formed between the gel-like resin layer 8 and the casing 6.

Abstract: The present invention discloses an electrostatic chuck sucking and supporting a substrate with an electrostatic force and an OLED manufacturing apparatus having the same. The electrostatic chuck includes an insulating plate having at least one opening penetrating a center thereof, a pair of electrodes mounted on the insulating plate, a first controller applying a voltage to the pair of electrodes, and an electrostatic charge removing unit disposed near the insulating plate and emitting ions into the at least one opening to remove electrostatic charges distributed around a side of the insulating plate.

Abstract: A MRAM structure is described that has a dedicated data storage layer formed between first and second electrodes and a dedicated data sensing layer between second and third electrodes to enable separate read and write functions. A diode between the storage layer and first electrode allows a heating current to flow between first and second electrodes to switch the data storage layer while a field is applied. A second diode between the sensing layer and third electrode enables a sensing current to flow only between second and third electrodes during a read process. Data storage and sensing layers and the three electrodes may be arranged in a vertical stack or the sensing layer, second diode, and third electrode may be shifted between adjacent stacks each containing first and second electrodes, a storage layer, and first diode. Second electrode and the sensing layer may be continuous elements through multiple MRAMs.

Abstract: A MEMS device is described that has a body with a component bonded to the body. The body has a main surface and a side surface adjacent to the main surface and smaller than the main surface. The body is formed of a material and the side surface is formed of the material and the body is in a crystalline structure different from the side surface. The body includes an outlet in the side surface and the component includes an aperture in fluid connection with the outlet.

Abstract: By providing test features of increased thickness in a test structure for performing an x-ray diffraction measurement for evaluating the crystalline characteristics, such as the contents of germanium, an increased accuracy may be achieved, since the patterned SOI layer may be used as an efficient reference for the required data analysis.

Abstract: The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared by the following steps. A single-crystalline MgO (001) substrate 11 is prepared. An epitaxial Fe(001) lower electrode (a first electrode) 17 with the thickness of 50 nm is grown on a MgO(001) seed layer 15 at room temperature, followed by annealing under ultrahigh vacuum (2×10?8 Pa) and at 350° C. A MgO(001) barrier layer 21 with the thickness of 2 nm is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) with the thickness of 10 nm is then formed on the MgO(001) barrier layer 21 at room temperature. This is successively followed by the deposition of a Co layer 21 with the thickness of 10 nm on the Fe(001) upper electrode (the second electrode) 23.

Abstract: A charge-free method of forming a nanostructure at low temperatures on a substrate. A substrate that is reactive with one of atomic oxygen and nitrogen is provided. A flux of neutral atoms of least one of oxygen and nitrogen is generated within a laser-sustained-discharge plasma source and a collimated beam of energetic neutral atoms and molecules is directed from the plasma source onto a surface of the substrate to form the nanostructure. The energetic neutral atoms and molecules in the beam have an average kinetic energy in a range from about 1 eV to about 5 eV.

Abstract: A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a plurality of semiconductor chip areas 2; an electrode pad 5 formed along the edge of the semiconductor chip area 2; and a metal-containing accessory pattern 4 disposed in the scribe lines. In the second scribe lines 32, the accessory pattern 4 is absent in at least the outermost surface in an area adjacent to the edge having the electrode pad 5 in the chip area 2.

Abstract: A surface emitting laser device is disclosed that is able to selectively add a sufficiently large loss to a high order transverse mode so as to efficiently suppress a high order transverse mode oscillation and to oscillate at high output in a single fundamental transverse mode. The surface emitting laser device includes a first resonance region that includes an active layer and spacer layers, two distributed Bragg reflectors that sandwich the resonance region, and a current confinement structure that defines a current injection region for the active layer. At least one of the distributed Bragg reflectors includes a second resonance region arranged in the current injection region excluding a predetermined region surrounding a center of the current injection region.

Abstract: A system for cooling a semiconductor includes a heat sink in thermal contact with the semiconductor, a thermal interface material (TIM) layer disposed between the heat sink and the semiconductor, and a picture frame support disposed between a substrate of the semiconductor and the heat sink, wherein the picture frame support encloses at least a portion of the semiconductor in a plane between the substrate and the heat sink, and wherein the picture frame support has a height that is greater than a height of the semiconductor.

Abstract: To arrange diffusion-inhibitory films 5a, 5b, and 5c for inhibiting the diffusion of a wiring material absent in a region on or above a light receiving unit 2, the diffusion-inhibitory films 5a, 5b, and 5c formed on a region above the light receiving unit 2 are selectively removed. Alternatively, the diffusion-inhibitory films are arranged only on top surfaces of wirings 4a, 4b, and 4c, and only a passivation film 12 and interlayer insulating films 3a, 3b, and 3c are arranged in the region on or above the light receiving unit 2. Thus, with less interface between different insulation films and less reflection of incident light in an incident region, the incident light 13 highly efficiently passes through these insulating films and comes into the light receiving unit 2. The light receiving unit 2 can thereby receive a sufficient quantity of the incident light 13.

Abstract: There are provided a magnetic memory device and a method of forming the magnetic memory device. The method of forming the magnetic memory device includes sequentially forming a first magnetic conductor, a tunnel barrier layer, and a second magnetic conductor on a substrate, forming a mask pattern on the second magnetic conductor, performing a primary etching of the second magnetic conductor by using the mask pattern as an etching mask, forming at least one spacer on sidewalls of the second magnetic conductor formed by the primary etching, and performing a secondary etching of the first magnetic conductor by using the mask pattern and the at least one spacers as an etching mask.

Abstract: A light-emission output of a flash lamp for performing a light-irradiation heat treatment on a substrate in which impurities are implanted is increased up to a target value L1 over a period of time from 1 to 100 milliseconds, is kept for 5 to 100 milliseconds within a fluctuation range of plus or minus 30% from the target value L1, and is then attenuated from the target value L1 to zero over a period of time from 1 to 100 milliseconds. That is, compared with conventional flash lamp annealing, the light-emission output of the flash lamp is increased more gradually, is kept to be constant for a certain period of time, and is then decreased more gradually. As a result, a total heat amount of a surface of the substrate increases compared with the conventional case, but a surface temperature thereof rises more gradually and then drops more gradually compared with the conventional case.

Abstract: According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.

Abstract: A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.

Abstract: An MTJ MRAM cell and its method of formation are described. The cell includes a composite free layer having the general form (Ni88Fe12)1-xCo100x—Ni92Fe8 with x between 0.05 and 0.1 that provides low magnetization and negative magnetostriction. The magnetostriction can be tuned to a low value by a multilayer capping layer that includes a positive magnetostriction layer of NiFeHf(15%). When this cell forms an MRAM array, it contributes to a TMR?26%, a TMR/Rp—cov?15.5 and a high AQF (array quality factor) for write operations.

Abstract: In some embodiments, a method of forming a photovoltaic cell includes (1) forming a cleave plane in a donor body so as to define a lamina to be bonded to a receiver element and exfoliated from the donor body; (2) prior to bonding, pre-heating the donor body without the receiver element to a temperature of greater than about 200° C. for a first time period that is less than a time period required for exfoliation of the lamina from the donor body; (3) cooling the donor body after pre-heating the donor body; (4) bonding the donor body to the receiver element; and (5) heating the bonded donor body and receiver element for a second time period so as to complete the exfoliation of the lamina from the donor body. Numerous other aspects are provided.

Abstract: A method of forming a semiconductor sensor in one embodiment includes providing a substrate, forming a reflective layer on the substrate, forming a sacrificial layer on the reflective layer, forming an absorber layer with a thickness of less than about 50 nm on the sacrificial layer, forming an absorber in the absorber layer integrally with at least one suspension leg, and removing the sacrificial layer.

Abstract: A method of forming one or more features during semiconductor device fabrication can comprise exposing a photosensitive layer to a first pattern at an exposure energy which is insufficient to fully expose the photosensitive layer, then exposing the photosensitive layer to a second pattern at an exposure energy which is insufficient to fully expose the photosensitive layer At an intersection of the first and second patterns, the energy does received during the first and second exposure is sufficient to fully expose the photosensitive layer.

Abstract: A semiconductor device is described. A channel area is arranged in a semiconductor substrate between a first contact area and a second contact area. A first programmable structure includes a first control structure. The first programmable structure is arranged such that a conductivity of a first section of the channel area depends on a voltage applicable to the first control structure of the first programmable structure and on an information value stored in the first programmable structure. A second programmable structure includes a second control structure. The second programmable structure is arranged such that a conductivity of a second section of the channel area depends on a voltage applicable to the second control structure of the second programmable structure and on an information value stored in the second programmable structure. The first section and the second section of the channel area are electrically connected in series between the first contact area and the second contact area.

Abstract: A process for forming a Schottky barrier to silicon to a barrier height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop the first film. The two films are then exposed to anneal steps at suitable temperatures to cause their interdiffusion and an ultimate formation of Ni2Si and Pt2Si contacts to the silicon surface. The final silicide has a barrier height between that of the Pt and Ni, and will depend on the initial thicknesses of the Pt and Ni films and annealing temperature and time. Oxygen is injected into the system to form and SiO2 passivation layer to improve the self aligned process.

Abstract: A method of fabricating a pixel structure includes first forming a first, a second, and a third dielectric layers over an active device and a substrate. Etching rates of the first and the third dielectric layers are lower than an etching rate of the second dielectric layer. A contact opening exposing a portion of the active device is formed in the third, the second, and the first dielectric layers. The third and the second dielectric layers are patterned to form a number of stacked structures. An electrode material layer is formed and fills the contact opening. The electrode material layer located on the stacked structures and the electrode material layer located on the first dielectric layer are separated. The stacked structures and the electrode material layer thereon are simultaneously removed to define a pixel electrode and to form at least an alignment slit in the pixel electrode.

Abstract: A method for fabricating a semiconductor device comprises forming a deposition structure including a first substrate, an insulating layer and a second substrate of a SOI substrate; etching the second substrate located in a boundary of cell and core regions and a peripheral region to form a line-type trench; filling an isolating film in the trench; removing the second substrate and the insulating layer of the peripheral region; performing a selective epitaxial growth (SEG) process using the first substrate exposed in the peripheral region to form an epitaxial layer; and performing a chemical mechanical polishing (CMP) process on the epitaxial layer. As a result, the method has a floating body effect to shorten a developing period and improve a process yield.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: A broad bandwidth light source including: a solid state light emitting device that generates short wavelength light; and quantum dot material and phosphor material that are each irradiated by some of the short wavelength light. The short wavelength light has a spectrum with a first peak wavelength shorter than about 500 nm. The quantum dot material absorbs some of the short wavelength light and reemits it as long wavelength light having a spectrum with a second peak wavelength longer than about 600 nm. The phosphor material absorbs some of the short wavelength light and reemits it as mid wavelength light having a spectrum with a peak wavelength between the first and second peak wavelength. The light source is configured such that some of each light (short, mid, and long wavelength) is emitted coincidentally as a light having a chromaticity value near the blackbody locus and a color rendering index greater than 80.

Abstract: By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.

Abstract: A method for manufacturing a phase change memory includes forming a phase change memory cell by forming a phase change layer between two switching layers. The phase change layer is separated from thermal heat sinks, such as the bitline or wordline, by the switching layers.

Abstract: A phase change memory device having a reduced contact area and a method for manufacturing the same is presented. The phase change random access memory device includes a bottom electrode contact pattern layer, and at least one phase change pattern layer formed on a sidewall of the bottom electrode contact pattern layer. The contact areas are minimized by being between the narrow width of the bottom electrode contact pattern layer, i.e., at the sidewall, and the phase change pattern layers. As a result the minimized contact area is proportional to the thickness of the bottom electrode contact pattern layer.

Abstract: By making an ovonic threshold switch using a carbon interfacial layer having a thickness of less than or equal to ten percent of the thickness of the associated electrode, cycle endurance may be improved. In some embodiments, a glue layer may be used between the carbon and the chalcogenide of the ovonic threshold switch. The glue layer may be effective to improve adherence between carbon and chalcogenide.

Abstract: An image sensor and method for manufacturing the same are provided. The image sensor can include a semiconductor substrate, a metal interconnection layer, a light-receiving unit, a lens-type upper electrode, and a color filter. The semiconductor substrate can include a circuit region. The metal interconnection layer can include a metal interconnection and an interlayer dielectric. The light-receiving unit can be a photodiode disposed on the metal interconnection layer. The lens-type upper electrode can be disposed on the light-receiving unit and formed in a convex lens shape. The color filter can be disposed on the lens-type upper electrode.

Abstract: To provide a semiconductor device with high performance and low cost and a manufacturing method thereof. A first region including a separated (cleavage) single-crystal semiconductor layer and a second region including a non-single-crystal semiconductor layer are provided over a substrate. It is preferable that laser beam irradiation be performed to the separated (cleavage) single-crystal semiconductor layer in an inert atmosphere, and laser beam irradiation be performed to the non-single-crystal semiconductor layer in an air atmosphere at least once.

Abstract: A semiconductor device includes: a semiconductor element having a light receiving region or a light emitting region on which a transparent member is attached, and a plurality of electrode pads; a substrate on which the semiconductor element is provided; and a resin covering the semiconductor element and side surfaces of the transparent member. The first area corresponding to part of an upper surface of the semiconductor element, which part is covered with the resin is smaller than the second area corresponding to parts of a lower surface of the semiconductor element and a lower surface of the substrate, which parts are covered with the resin.

Abstract: A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

Abstract: A light emitting device is provided, including a resin which can be manufactured according to a simple process and deliver a desired scattering property. The light emitting device is manufactured according to a step for mixing two or more types of immiscible liquid materials to obtain a composition containing at least two types of materials phase-separated in a sea-island structure, and a step for arranging the composition in proximity to an LED chip, curing the composition with the sea-island structure being maintained, thereby forming an encapsulation resin. Accordingly, it is possible to form an island region which serves as a scattering center, according to a simple step of mixing materials.

Abstract: After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).

Abstract: An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.

Abstract: Apparatus and methods for forming optoelectronic devices such as an array of light emitting diodes or photovoltaic cells in one embodiment a roll-to-roll process in which a uniquely configured roller having a raised spiral coating surface is aligned with a plurality of first electrodes disposed on an angle on a substrate for coating a plurality of spaced-apart angled coated strips of optoelectronic materials along the cross-web direction of the substrate.

Abstract: A power semiconductor module includes a housing, a substrate carrier with a circuit thereon and electrical connection elements extending therefrom. The carrier has a cutout between its inner surface (facing the interior of the module) and its outer surface. The cutout is smaller at the inner surface than at the outer surface. The housing has an extension that reaches into the cutout and may be deformed to form a riveted connection. The method comprises: forming a housing with at least one extension which extends towards the exterior of the module, wherein the extension projects through the cutout and beyond the outer surface of the carrier; and deforming the end of the extension so that it widens and forms a riveted connection and at the same time lies below the outer surface of the carrier.