Abstract: A phase change memory device is presented that has a lower electrode contact that has a gradient resistance profile ranging from a lower resistive lower end to a higher resistive upper end. The phase change memory device includes a semiconductor substrate, a lower electrode contact, and a phase change pattern. The semiconductor substrate has a switching device. The lower electrode contact is formed on the switching device and has a specific resistance which gradually increases from a lower part to an upper part of the lower electrode contact. The phase change pattern layer is formed on the lower electrode contact.

Abstract: Provided are the methods of evaluating thermal treatment. In the methods, a wafer comprising a silicon substrate having an oxygen concentration of approximately equal to or less than 1.0×1018 atoms/cm3 and a silicon epitaxial layer on at least one surface of the substrate is employed.

Abstract: A semiconductor package has first and second semiconductor die mounted to a substrate. The first semiconductor die includes a first inductor coil electrically coupled to the substrate. The second semiconductor die is mounted over the first semiconductor die. The second semiconductor die includes a second inductor coil electrically coupled to the substrate. A center of the second inductor coil has a vertical and lateral separation with respect to a center of the first inductor coil which are each selectable to minimize mutual inductive coupling between the first and second inductor coils. A spacer is disposed between the first and second semiconductor die to adjust the vertical separation. The center of the second inductor is positioned laterally within the second semiconductor die with respect to the center of the first inductor to adjust the lateral separation. The mutual inductive coupling decreases with increasing vertical and lateral separation.

Abstract: A semiconductor light-emitting transistor device, including: a bipolar pnp transistor structure having a p-type collector, an n-type base, and a p-type emitter; a first tunnel junction coupled with the collector, and a second tunnel junction coupled with the emitter; and a collector contact coupled with the first tunnel junction, an emitter contact coupled with the second tunnel junction, and a base contact coupled with the base; whereby, signals applied with respect to the collector, base, and emitter contacts causes light emission from the base by radiative recombination in the base.

Abstract: To provide an elemental technique for improving the emission intensity of deep ultraviolet light from a light emitting layer made of an AlGaInN-based material, in particular, an AlGaN-based material. First, an AlN layer is grown on a sapphire surface. The AlN layer is grown under a NH3-rich condition. The TMAl pulsed supply sequence includes growing an AlGaN layer for 10 seconds, interrupting the growth for 5 seconds to remove NH3, and then introducing TMAl at a flow rate of 1 sccm for 5 seconds. After that, the growth is interrupted again for 5 seconds. Defining this sequence as one growth cycle, five growth cycles are carried out. By such growth, an AlGaN layer having a polarity of richness in Al can be obtained. The above sequence is described only for illustrative purposes, and various variations are possible. In general, the Al polarity can be achieved by a process of repeating both growth interruption and supply of an Al source.

Abstract: A semiconductor device is made by providing a metal substrate for supporting the semiconductor device. Solder bumps are connected to the substrate. In one embodiment, a conductive material is deposited over the substrate and is reflowed to form the solder bumps. A semiconductor die is mounted to the substrate using a die attach adhesive. The semiconductor die has a plurality of contact pads formed over a surface of the semiconductor die. An encapsulant material is deposited over the solder bumps and the semiconductor die. The encapsulant is etched to expose the contact pads of the semiconductor die. A first redistribution layer (RDL) is formed over the encapsulant to connect each contact pad of the semiconductor die to one of the solder bumps. The substrate is removed to expose the die attach adhesive and a bottom surface of the solder bumps.

Abstract: An in-plane switching mode transflective liquid crystal display device includes: first and second substrates; a gate line and a data line on an inner surface of the first substrate, the gate line and the data line crossing each other to define a pixel region; a common line parallel to the gate line; a thin film transistor connected to the gate and data lines; a first passivation layer over the thin film transistor; a reflecting layer over the first passivation layer; a second passivation layer over the reflecting layer; a pixel electrode over the second passivation layer; a third passivation layer over the pixel electrode; a common electrode over the third passivation layer, the common electrode connected to the common line, the common electrode including a plurality of first openings along a first direction in the transmissive area and a plurality of second openings along a second direction different from the first direction in the reflective area; a color filter layer on an inner surface of the second subst

Abstract: Provided is a thermal head (1) including: a substrate body (12) constituted through bonding a flat supporting substrate (13) and a flat upper substrate (11), which are made of a glass material onto each other in a stacked state; a heating resistor (14) formed on a surface of the upper substrate (11); and a protective film (18) that partially covers the surface of the upper substrate (11) including the heating resistor (14) and protects the heating resistor (14), in which a heat-insulating concave portion (32) and thickness-measuring concave portions (34), which are open to a bonding surface between the supporting substrate and the upper substrate (11) and form cavities are provided in the supporting substrate (13), the heat-insulating concave portion (32) is formed at a position opposed to the heating resistor (14), and the thickness-measuring concave portions (34) is formed in a region that is prevented from being covered with the protective film (18).

Abstract: One embodiment of the present invention is a thin film transistor having a gate electrode formed on an insulating substrate, a gate wire connected to the gate electrode, a capacitor electrode, a capacitor wire connected to the capacitor electrode, a gate insulator formed on the gate electrode, an oxide semiconductor pattern formed on the gate insulator, a sealing layer formed on the oxide semiconductor pattern, a drain electrode and a source electrode formed on the sealing layer, a drain wire connected to the drain electrode and a pixel electrode connected to the source electrode, the drain wire and the pixel electrode being in the same layer as the drain electrode and the source electrode.

Abstract: Methods for treating a substrate in preparation for a subsequent process are presented, the method including: receiving the substrate, the substrate comprising conductive regions and dielectric regions; and applying an oxidizing agent to the substrate in a manner so that the dielectric regions are oxidized to become increasingly hydrophilic to enable access to the conductive regions in the subsequent process, wherein the dielectric region is treated to a depth in the range of approximately 1 to 5 atomic layers. In some embodiments, methods further include processing the substrate, wherein processing the conductive regions are selectively enhanced. In some embodiments, the oxidizing agent includes atmospheric pressure plasma and UV radiation.

Abstract: A magnetic element having a ferromagnetic pinned layer, a ferromagnetic free layer, a non-magnetic spacer layer therebetween, and a porous non-electrically conducting current confinement layer between the free layer and the pinned layer. The current confinement layer forms an interface either between the free layer and the non-magnetic spacer layer or the pinned layer and the non-magnetic spacer layer.

Abstract: An electronic component has at least two semiconductor devices, a contact clip and a leadframe with a device carrier portion and a plurality of leads. The contact clip extends between the first side of at least two semiconductor devices and at least one lead of the leadframe to electrically connect a load electrode of the at least two semiconductor devices to at least one lead.

Abstract: A substrate processing system processes a plurality of substrates in a single-substrate processing mode by a plurality of processes and provided with a plurality of modules respectively for carrying out processes. When a defect is found in a substrate, a defective processing unit that caused the defect can be easily found out. The substrate processing system and a substrate processing method to be carried out by the substrate processing system can suppress the reduction of throughput when a large number of substrates are to be processed. The substrate processing system is provided with a plurality of modules for processing a plurality of substrates (W) in a single-substrate processing mode by a plurality of processes and includes a substrate carrying means (A4) for carrying a substrate (W) from a sending module to a receiving module, and a control means (6) for controlling the substrate carrying means (A4) on the basis of one of at least two carrying modes each assigning receiving modules to sending modules.

Abstract: A back contact solar cell comprises a first dopant diffusion part and a second dopant diffusion part formed on a rear surface of an n-type semiconductor wafer with a predetermined distance formed therebetween by a diffusion prevention part for ensuring no contact with each other and suppressing the diffusion of dopant; and an electrode configured of an anode and a cathode each connected to the first dopant diffusion part and the second dopant diffusion part. According to the present invention, the back contact solar cell is capable of preventing light loss and improving its efficiency by forming an electrode to be positioned on a rear surface of a semiconductor wafer through a simple process and by simultaneously implementing an anode electrode and a cathode electrode on the semiconductor wafer without having a grid electrode restricting incidence of sunlight.

Abstract: Methods and apparatuses for a batch processing system with in-line interfaces are provided to batch processing substrates in an in-line processing facility. In an embodiment, the batch processing system comprises carrier assembling and carrier disassembling stations interfacing the in-line path and the batch processing stations.

Abstract: A sealed joint structure of device includes a buffer bump layer, conductive joint portions and a sealed joint portion. The buffer bump layer disposed between a device and a substrate includes first parts and a second part surrounding the first parts. Each of the conductive joint portions includes a first electrode covering each of the first parts and a second electrode on the substrate, and each of the first electrodes is electrically connected to the second electrode. The sealed joint portion includes a joint ring located on the substrate and is jointed with the second part to form a hermetic space between the device and the substrate.

Abstract: A CMOS image sensor and a fabricating method for a semiconductor device are disclosed. Embodiments provide a CMOS image sensor having an improved structure using a light reflection system, with a fabricating method thereof to simplify the fabrication process and maximize a light receiving area. Embodiments may be applied to a semiconductor device having a lamination structure.

Abstract: A method of manufacture of an integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.

Abstract: An electronic device may have a display. The display may have active components such as display pixels formed on a display substrate layer. The display substrate layer may be formed from a glass substrate layer. Thin-film transistors and other components for the display pixels may be formed on the glass substrate. An encapsulation glass layer may be bonded to the glass substrate using a ring-shaped bond structure. The ring-shaped bond structure may extend around the periphery of the encapsulation glass layer and the substrate glass layer. The bond structure may be formed from a glass frit, a solid glass ring, integral raised glass portions of the glass layers, meltable metal alloys, or other bond materials. Chemical and physical processing operations may be used to temper the glass layers, to perform annealing operations, to preheat the glass layers, and to promote adhesion.

Abstract: A donor film for a laser induced thermal imaging method capable of improving the optical efficiency of an emission layer, a light emitting device using the same, and a method of manufacturing the light emitting device are provided. The donor film for a laser induced thermal imaging method includes a base substrate, a light to heat conversion layer (LTHC) provided on the base substrate and having a pattern with a predetermined step difference, and a transfer layer provided on the LTHC. It is possible to improve the optical efficiency of the emission layer by patterning the transfer layer using the LTHC having the pattern with a predetermined step difference.

Abstract: A memory cell as described herein includes a conductive contact and a memory element comprising programmable resistance memory material overlying the conductive contact. An insulator element extends from the conductive contact into the memory element, the insulator element having proximal and distal ends and an inside surface defining an interior. The proximal end is adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end. The memory element is within the interior extending downwardly from the distal end to contact a top surface of the bottom electrode at a first contact surface. A top electrode can be separated from the distal end of the insulator element by the memory element and contact the memory element at a second contact surface having a surface area greater than that of the first contact surface.

Abstract: A CMOS image sensor and a method for manufacturing the same are provided. The CMOS image sensor enlarges an area of a real image and prevents interference between adjacent pixels by forming a plurality of microlenses on a convex surface and forming a light blocking layer in the space between each of color filters. The CMOS image sensor can include photodiodes, a first planarization layer, R, G, B color filter layers, a second planarization layer having holes filled with a light blocking layer, and a plurality of microlenses.

Abstract: A light emitting device includes: a substrate; an LED chip provided on a main surface of the substrate; and a printed resistor element connected in parallel with the LED chip, the printed resistor element being provided in at least one of regions (i) on the main surface of the substrate, (ii) on a back surface of the substrate, and (iii) inside the substrate. According to the arrangement, it is possible to provide: a light emitting device which can emit light having preferable luminance without a reduction in optical output by suppressing light shielding and light absorption of light emitted from the LED toward the outside; and a method for manufacturing the light emitting device.

Abstract: An integrated circuit (IC) die includes two bonding pads, that share a common logical function, such as signal input or signal output, separated by the width of the die, and preferably on opposite sides of the die. System-in-package devices are produced by steps including directly electrically connecting one or the other bonding pad to bonding pads of other, functionally different IC dies, with the bonding pads of the other IC dies, to which are connected bonding pads of common logical function of the IC dies of the present invention, being functionally identical but geometrically different. Multichip package devices are produced by stacking the IC dies of the present invention with other IC dies and directly electrically connecting one or the other bonding pad to different bonding pads of the other IC dies.

Abstract: A thin film transistor array of a horizontal electronic field applying type enhances brightness. The thin film transistor array includes a gate line and common line separated from the gate line; a data line crossing with the gate line to define pixel region and insulated from the gate line by a gate insulating film; a TFT connected to the gate line and the data line in the pixel region; a pixel electrode on a passivation film overlapping with the common line in the pixel region and connected to the TFT; and a common electrode on the passivation film opposed to the pixel electrode in the pixel region and connected to the common line, wherein the width of the pixel electrode at the overlapping portion between the common line and the pixel electrode is narrower than the width of the common line, and the edge of one side of the pixel electrode adjacent to the common electrode is formed on the inside of the edge of one side of the common line adjacent to the common electrode.

Abstract: A radio-frequency integrated circuit chip package has at least one integrated antenna. The package includes at least one generally planar ground plane formed with at least one slot therein. A first substrate structure has an outer surface and an inner surface. The at least one generally planar ground plane is formed on the outer surface of the first substrate structure. At least one feed line is spaced inwardly from the ground plane and parallel thereto. The at least one feed line has an inner surface and an outer surface and is a transmission line formed on the inner surface of the first substrate structure with the outer surface of the at least one feed line adjacent the inner surface of the first substrate structure. At least one radio frequency chip is coupled to the feed line and the ground plane. A second substrate structure, spaced inwardly from the feed line, defines a chip-receiving cavity. The chip is located in the chip-receiving cavity.

Abstract: A substrate processing system includes a processing unit, a substrate loading unit, a substrate unloading unit, and a carrying unit. A carrying device has a constitution in which a suction portion suctioning and holding a substrate is rotatable about an arm portion provided in a base portion and the substrate is rotated in the state where the substrate is held by a holding portion. A coating device has a constitution in which a liquid material is ejected from a nozzle to both surfaces of the substrate rotating in an upright state.

Abstract: A near-field light generating element accommodated in a groove of an encasing layer has an outer surface that includes a first end face including a near-field light generating part, a second end face opposite to the first end face, and a coupling portion that couples the first and second end faces. The coupling portion includes a top surface, and first and second side surfaces that decrease in distance from each other with increasing distance from the top surface. The first end face includes a first side located at an end of the first side surface, and a second side located at an end of the second side surface. Each of the first and second sides includes an upper part and a lower part continuous with each other. An angle formed between the respective lower parts of the first and second sides is smaller than that formed between the respective upper parts of the first and second sides.

Abstract: A semiconductor device includes a semiconductor element, a first heat sink, a second heat sink, and a resin member. The semiconductor element has first and second surfaces. The first heat sink has a first heat radiation surface and a first end surface. The first end surface is coupled with the first surface. The second heat sink has a second heat radiation surface, the second end surface being opposite the second heat radiation surface, and a depressed section depressed toward the second heat radiation surface. The second surface of the semiconductor element is coupled with a bottom surface of the depressed section. The resin member is disposed in the depressed section and seals the semiconductor element, the first heat sink, and the second heat sink in such a manner that the first heat radiation surface is exposed outside the resin member.

Abstract: An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor.

Abstract: An image sensor and a fabricating method thereof are provided. The image sensor includes a plurality of pixels disposed in an active region and dummy pixels disposed in a peripheral region. An interlayer dielectric layer has a first thickness in the active region and a second thickness thinner than the first thickness in the peripheral region. Color filters are disposed in the active region, and a light blocking member is disposed in the peripheral region. There is substantially no step difference between the color filters and the light blocking member.

Abstract: A MEMS device comprising a flexible membrane that is free to move in response to pressure differences generated by sound waves. A first electrode mechanically coupled to the flexible membrane, and together form a first capacitive plate. A second electrode mechanically coupled to a generally rigid structural layer or back-plate, which together form a second capacitive plate. A back-volume is provided below the membrane. A first cavity located directly below the membrane. Interposed between the first and second electrodes is a second cavity. A plurality of bleed holes connected the first cavity and the second cavity. Acoustic holes are arranged in the back-plate so as to allow free movement of air molecules, such that the sound waves can enter the second cavity. The first and second cavities in association with the back-volume allow the membrane to move in response to the sound waves entering via the acoustic holes in the back-plate.

Abstract: A backlight for a color LCD includes white light LEDs formed using a blue LED die with a layer of red and green phosphors over it. The attenuation by the LCD layers of the blue light component of the white light is typically greater as the blue wavelength becomes shorter. In order to achieve a uniform blue color component across the surface of an LCD screen and achieve uniform light output from one LCD to another, the blue light leakage of the phosphor layer is tailored to the dominant or peak wavelength of the blue LED die. Therefore, the white points of the various white light LEDs in a backlight should not match when blue LED dies having different dominant or peak wavelengths are used in the backlight. The different leakage amounts through the tailored phosphor layers offset the attenuation vs. wavelength of the LCD layers.

Abstract: In aspects of the present invention, a method is disclosed to form a lamina having opposing first and second surfaces. Heavily doped contact regions extend from the first surface to the second surface. Generally the lamina is formed by affixing a semiconductor donor body to a receiver element, then cleaving the lamina from the semiconductor donor body wherein the lamina remains affixed to the receiver element. In the present invention, the heavily doped contact regions are formed by doping the semiconductor donor body before cleaving of the lamina. A photovoltaic cell comprising the lamina is then fabricated. By forming the heavily doped contact regions before bonding to the receiver element and cleaving, post-bonding high-temperature steps can be avoided, which may be advantageous.

Abstract: Disclosed are a stacked semiconductor package and a method for manufacturing the same. The method for manufacturing a stacked semiconductor package includes preparing a substrate formed with a seed metal layer; laminating semiconductor chips having via holes aligned with one another on the seed metal layer to form a semiconductor chip module; and growing a conductive layer inside of the via holes using the seed metal layer to form a conductive growth layer inside of the via holes.

Abstract: A step of forming wiring using first solution ejection means for ejecting a conductive material, a step of forming a resist mask on the wiring using second solution ejection means, and a step of etching the wiring using an atmospheric-pressure plasma device having linear plasma generation means or an atmospheric-pressure plasma device having a plurality of linearly-arranged plasma-generation-means using the resist mask as a mask are included.

Abstract: Methods of forming spin torque microelectronic devices are described. Those methods may include forming a free FM layer on a substrate, forming a non-magnetic layer on the free FM layer, forming at least three input pillars on the non-magnetic layer, and forming an output pillar on the non-magnetic layer to form a majority gate device.

Abstract: Magnetoresistive structures, devices, memories, and methods for forming the same are presented. For example, a magnetoresistive structure includes a ferromagnetic layer, a ferrimagnetic layer coupled to the ferromagnetic layer, a pinned layer and a nonmagnetic spacer layer. A free side of the magnetoresistive structure comprises the ferromagnetic layer and the ferrimagnetic layer. The nonmagnetic spacer layer is at least partly between the free side and the pinned layer. A saturation magnetization of the ferromagnetic layer opposes a saturation magnetization of the ferrimagnetic layer. The nonmagnetic spacer layer may include a tunnel barrier layer, such as one composed of magnesium oxide (MgO), or a nonmagnetic metal layer.

Abstract: A substrate transfer apparatus, for transferring a substrate from a first module to a second module, includes a moving base having a Y-motion axis for moving the moving base in Y-direction, and a substrate holding member mounted to the moving base via X-motion axis so as to move relative to the moving base to be in an advanced position and a retracted position relative to the moving base. The X-motion axis operates when the Y-motion axis is operating, if the X-motion axis must be parallel to the Y-motion axis when transferring the substrate from the substrate holding member to the second module.

Abstract: This sheet production apparatus comprises a vessel defining a channel configured to hold a melt. The melt is configured to flow from a first point to a second point of the channel. A cooling plate is disposed proximate the melt and is configured to form a sheet on the melt. A spillway is disposed at the second point of the channel. This spillway is configured to separate the sheet from the melt.

Abstract: It is an object to provide a fixing jig which can unmovably suction a chip group produced by segmenting a semiconductor wafer into pieces, and can suction one chip by detaching the chip selectively and reliably from the chip group. A fixing jig 3 is composed of a jig base 30 and an contact layer 31. A concave part 2 is formed on one side of the jig base 30. The concave part 2 is sectioned into small chambers 15 by a partition 12 having a height almost equivalent to that of a sidewall 35. The contact layer 31 is disposed on the upper edge of the sidewall 35 and the partition 12 for covering the concave part 2. A through hole 17 that is communicated with the outside is formed in each small chamber 15.

Abstract: A transport method for disk-shaped semiconductor wafer workpieces has a horizontally movable transport arm with two elongated carrying elements at one end, for receiving the workpiece. A cassette which includes a comb structure at each side for receiving several workpieces, is inserted free of contact between two adjacent combs with workpieces therein for vertically lifting a workpiece. The carrying elements are disposed such that during a cassette engagement they are each positioned substantially adjacent and parallel to the comb structure along a comb, and in this region along and between two adjacent comb planes on one side of the cassette, a scanning beam is provided for workpiece acquisition. The scanning beam is relatively height-positionable with respect to the cassette and is tilted about a small angle with respect to the horizontal workpiece plane.

Abstract: A substrate processing system includes a first load lock, a process chamber having a first opening to allow an exchange of a substrate between the first load lock and the first process chamber, first rollers in the process chamber; and second rollers in the first load lock, wherein the first rollers and the second rollers are configured to transport a substrate thereon through the first opening between the first load lock and the process chamber. At least some of the first rollers and the second rollers are idler rollers.

Abstract: The invention discloses a method to store digital information through use of spin torque transfer in a device that has a very low critical current. This is achieved by adding a spin filtering layer whose direction of magnetization is fixed to be parallel to the device's pinned layer.

Abstract: An apparatus and method uses a first Faraday cage portion and a second Faraday cage portion to provide a Faraday cage enclosure surrounding at least one circuit device.

Abstract: A substrate storage facility comprises a multilevel shelf, on which a plurality of cassettes with airtight covers accommodating a plurality of substrates can be placed; a substrate transport portion, moveably positioned on the front-face side of the multilevel shelf, which opens and closes the airtight covers of the cassettes with airtight covers placed on the multilevel shelf, and which transports the substrates between cassettes with airtight covers; and, a cassette transport portion, moveably positioned on the rear-face side of the multilevel shelf, which carries cassettes with airtight covers into and out of all the cassette placement positions of the multilevel shelf. By means of this substrate storage facility, interchange processing of substrates accommodated in cassettes, as well as carrying in and out of cassettes when appropriate, can be performed.

Abstract: A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer.

Abstract: Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting layer comprises a first conductive type semiconductor layer, an active layer on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the active layer. The active layer comprises a quantum well layer, a quantum barrier layer, and a dual barrier layer.

Abstract: In a method for handling a wafer case having attachable and detachable grips, the method comprising the step of handling the wafer case e in an automatic transfer line while the attachable and detachable grips are detached from the wafer case and holding parts allowing an automatic transfer unit to hold the wafer case are attached to portions of the wafer case from which the attachable and detachable grips have been detached. The holding parts allow an automatic transfer unit to hold the wafer case.

Abstract: A semiconductor device having a microcomputer chip and a plurality of high-speed memory chips and capable of making wiring lines of the memory chips equal in length is disclosed. The semiconductor device comprises a first wiring substrate, a microcomputer chip mounted over the first wiring substrate, a second wiring substrate disposed over the microcomputer chip, a plurality of first solder bumps for connecting the first and second wiring substrates with each other, and a plurality of second solder bumps as external terminals formed over a back surface of the wiring substrate. A first memory chip and a second memory chip, as high-speed memory chips, are stacked within the second wiring substrate, wiring of the first memory chip and that of the second memory chip are made equal in length within the second wiring substrate, and a completed package structure having the second wiring substrate is mounted over a completed package structure having the first wiring substrate.