Abstract: A temperature sensor structure for a semiconductor device. One embodiment provides a semiconductor substrate including the semiconductor device. A dissipation region of the semiconductor device is adjacent to a main surface of the semiconductor substrate. A first layer arrangement is disposed on the main surface of the semiconductor substrate adjacent to the dissipation region of the semiconductor device. A second layer arrangement is disposed on the first layer arrangement with an insulation layer for galvanic separation therebetween. The first and second layer arrangements and the insulation layer form a layer structure on the main surface above the dissipation region. A circuit element is disposed in the second layer arrangement, the circuit element having a temperature-dependent characteristic and being coupled thermally to the dissipation region.

Abstract: A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.

Abstract: Two opposing substrate layers each having one or more recesses filled with magnetic material guide the flow of flux through a coil in a MEMS device layer to provide for closed-loop operation. Flux flows from one pole piece through the coil to a second pole piece. A method of making using lithographic etching techniques is also provided.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a shielding channel through a substrate first side and a substrate second side; mounting a first shielding interconnect to the shielding channel; mounting an integrated circuit over the substrate and adjacent to the first shielding interconnect; attaching a silicon interposer, having an integral-conductive-shield and a via, to the first shielding interconnect with the integral-conductive-shield over the integrated circuit; grounding the shielding channel at the substrate second side; and forming an encapsulation over the substrate covering the integrated circuit and the first shielding interconnect.

Abstract: To provide a magnetic memory device that can suppress the reduction of function of a magnetic memory element, and a manufacturing method thereof. A magnetic memory device includes a magnetic memory element capable of holding data based on a magnetized state thereof, and a digit line and a bit line which are capable of changing the magnetized state of the magnetic memory element by a magnetic field generated. The magnetic memory element is disposed above the digit line and the bit line at an intersection part of the digit line and the bit line. The digit line has a first width at the intersection part, and the bit line has a second width at the intersection part. The first width is larger than a third width of the magnetic memory element, and the second width is smaller than a fourth width of the magnetic memory element.

Abstract: A semiconductor device comprising a semiconductor module that has a joint surface, a first fitting portion and a second fitting portion provided on the joint surface, the second fitting portion having a shape different from the first fitting portion; and a radiating fin that has a joint surface, a third fitting portion and a fourth fitting portion provided on the joint surface, the fourth fitting portion having a shape different from the third fitting portion; the semiconductor module is bonded to the radiating fin so that the first fitting portion is fitting into the third fitting portion or the third fitting portion is fitting into the first fitting portion, and the second fitting portion is fitting into the fourth fitting portion or the fourth fitting portion is fitting into the second fitting portion.

Abstract: A light-emitting device includes: a substrate; a light-emitting element is mounted on a first surface of the substrate; at least one uneven heat dissipation pattern is formed on at least one surface of the substrate; and an electrode covers at least a portion of the at least one uneven heat dissipation pattern and is connected to the light-emitting element.

Abstract: An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.

Abstract: An electromechanical systems device includes a plurality of supports disposed over a substrate and a deformable reflective layer disposed over the plurality of supports. The deformable reflective layer includes a plurality of substantially parallel columns extending in a first direction. Each column has one or more slots extending in a second direction generally perpendicular to the first direction. The slots can be created at boundary edges of sub-portions of the columns so as to partially mechanically separate the sub-portions without electrically disconnecting them. A method of fabricating an electromechanical device includes depositing an electrically conductive deformable reflective layer over a substrate, removing one or more portions of the deformable layer to form a plurality of electrically isolated columns, and forming at least one crosswise slot in at least one of the columns.

Abstract: One embodiment of the present invention includes a memory element having a composite free layer including a first free sub-layer formed on top of the bottom electrode, a nano-current-channel (NCC) layer formed on top of the first free sub-layer, and a second free sub-layer formed on top of the NCC layer, wherein when switching current is applied to the memory element, in a direction that is substantially perpendicular to the layers of the memory element, local magnetic moments of the NCC layer switch the state of the memory element.

Abstract: There is provided a bank structure which partitions off a pattern formation region in which a functional liquid is to be disposed and flow. The pattern formation region includes a first pattern formation region, and a second pattern formation region which is continuously connected to the first pattern formation region and which has a larger width than the first pattern formation region. The second pattern formation region is provided with at least one partition bank which partitions off the second pattern formation region to regulate the flow direction of the functional liquid. A partition width substantially orthogonal to the flow direction of the functional liquid which is regulated by the partition bank is less than ±20% of the width of the first pattern formation region.

Abstract: A semiconductor device includes a first semiconductor chip that is mounted face-down on a substrate, a second semiconductor chip that is mounted face-up on the first semiconductor chip, and a dummy chip that is interposed between the first semiconductor chip and the second semiconductor chip. The dummy chip is made from a homogenous material comprising silicon or an alloy containing an atomic percentage majority of silicon.

Abstract: Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

Abstract: A semiconductor light emitting element, comprises: an active layer; a first electrode and second electrode that inject current to the active layer; a semiconductor layer between the active layer and the first electrode; and a dielectric layer that is provided on the semiconductor layer and through which light from the active layer passes; wherein the first electrode is provided on the semiconductor layer, has an opening through which light from the active layer passes, and comprises a first electrode layer that comes in contact with and is provided on the semiconductor layer, and a second electrode layer that is provided on the first electrode layer, with the first electrode layer having less reactivity with the semiconductor layer than the second electrode layer; and the dielectric layer is provided inside the opening such that the end section on the opening side of the first electrode layer extends from the top of the semiconductor layer to the top of the dielectric layer.

Abstract: Disclosed is a producing method of a semiconductor device comprising a step of forming a tunnel insulating film of a flash device comprising a first nitridation step of forming a first silicon oxynitride film by nitriding a silicon oxide film formed on a semiconductor silicon base by one of plasma nitridation and thermal nitridation, the plasma nitridation carrying out nitridation process by using a gas activated by plasma discharging a first gas including a first compound which has at least a nitrogen atom in a chemical formula thereof, and the thermal nitridation carrying out nitridation process using heat by using a second gas including a second compound which has at least a nitrogen atom in a chemical formula thereof, and a second nitridation step of forming a second silicon oxynitride film by nitriding the first silicon oxynitride film by the other of the plasma nitridation and the thermal nitridation.

Abstract: A method of fabricating a semiconductor device is provided. First, a first electrode is formed over a first region of a substrate. Then, a dielectric layer covering the first electrode is formed over the substrate. After that, a plurality of openings is formed on the first region of the substrate. Thereafter, a conductive layer covering the dielectric layer and the openings is formed over the substrate. Then, the conductive layer in the bottom of the openings is removed to form second electrodes. After that, the dielectric layer between the second electrode and the first electrode is removed.

Abstract: Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Abstract: For fabricating an image sensor, an isolation structure is formed to define a first active region of a semiconductor substrate. A first transistor and a second transistor of a unit pixel are formed in the first active region. In addition, a threshold voltage lowering region is formed in a portion of the semiconductor substrate near a portion of the isolation structure abutting the second transistor in the first active region. The threshold voltage lowering region causes the second transistor to have a respective threshold voltage magnitude that is lower than for the first transistor. The threshold voltage lowering region is formed simultaneously with a passivation region in a second active region having a photodiode formed therein.

Abstract: A magnetoresistive memory cell includes a magnetic tunnel junction element; and a selection transistor, wherein the selection transistor includes a first conductive type semiconductor layer, a gate electrode formed on the first conductive type semiconductor layer with a gate insulation film interposed between the first conductive type semiconductor layer and the gate electrode, and second conductive type first and second diffusion regions formed in the first conductive type semiconductor such that the first and second diffusion regions are spaced apart from each other. The magnetic tunnel junction element includes a free magnetization layer, a fixed magnetization layer, and a tunnel barrier layer interposed between the free magnetization layer and the fixed magnetization layer, and the free magnetization layer of the magnetic tunnel junction element is electrically connected to any one of the first and second diffusion regions of the selection transistor.

Abstract: The invention relates to a reconfigurable magnetic logic-circuit array having at least two magnetoresistive elements, each composed of at least two magnetic layers, which are separated from one another by an intermediate layer, in each instance, whereby one of the magnetic layers, as a reference layer, does not substantially change its magnetization under the influence of external magnetic fields, and the other magnetic layer, as a free layer, changes its magnetization perceptibly under the influence of external magnetic fields, and having at least one conductor for signal ports, with which conductor, when current is flowing, a first magnetic field can be generated that flips the magnetization of the free layers, and having a device for on-demand generation of a second variable magnetic field, which also influences the magnetoresistive elements.

Abstract: Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A portion of a fin of the non-planar pull-up transistor is electrically connected to a portion of a fin of the non-planar pull-down transistor by an assist-bar. The methods involve forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor and between gate electrodes, and widening a width of the assist-fin to form the assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar.

Abstract: A pn-junction compound semiconductor light-emitting device is provided, which comprises a stacked structure including a light-emitting layer composed of an n-type or a p-type aluminum gallium indium phosphide and a light-permeable substrate for supporting the stacked structure, and the stacked structure and the light-permeable substrate being joined together, wherein the stacked structure includes an n-type or a p-type conductor layer, the conductor layer and the substrate are joined together, and the conductor layer is composed of a Group III-V compound semiconductor containing boron.

Abstract: An in-plane switching mode liquid crystal display (LCD) device, which reduces loss in transmittance and improves reflectance, and a method for fabricating the same are disclosed. The in-plane switching mode LCD device includes gate and data lines orthogonally crossing each other on a first substrate to define pixel regions having reflection portions and transmission portions; thin film transistors formed at the crossing of the gate and data lines; common electrodes formed at the transmission portions of the pixel regions; reflection electrodes formed at the reflection portions of the pixel regions; pixel electrodes formed parallel with the common electrodes at the transmission portions and formed above the reflection electrodes at the reflection portions; a second substrate facing and attached to the first substrate; a liquid crystal layer interposed between the first and second substrates; and first and second polarizing films respectively attached to outer surfaces of the first and second substrates.

Abstract: A device structure with preformed ring includes a sensor chip and a ring disposed and surrounded on periphery of sensitive area of an active surface thereof. The device structure with preformed ring may batchly bind and electrically connect to a carrier by a way of two-dimension array, and then a packaging process is performed. During the packaging process, the top portion of the ring can be used to against the inner side of a packaging mold, so as to stop the packaging material covering the device at outside of the ring and stick with the ring. Therefore, an opening is formed on the sensitive area surface of the device. Depending on the ring, the extra process for eliminating the packaging material on the sensitive area surface can be avoided in the conventional process.

Abstract: A semiconductor device and methods of forming same are disclosed having multiple die redistribution layer. After fabrication of semiconductor die on a wafer and prior to singulation from the wafer, adjacent semiconductor die are paired together and a redistribution layer may be formed across the die pair. The redistribution layer may be used to redistribute at least a portion of the bond pads from the first die in the pair to a second die in the pair. One die in each pair will be a working die and the other die in each pair will be a dummy die. The function of the integrated circuit beneath the redistribution layer on the dummy die is at least partially sacrificed.

Abstract: Disclosed is a nonvolatile magnetic memory cell, comprising: a) a switchable magnetic element; b) a word line and a bit line to energize the switchable magnetic element; and c) a magnetic field boosting material positioned adjacent to at least one of the word line and the bit line to boost a magnetic field generated by current flowing therein.

Abstract: Disclosed is a Magnetic Tunnel Junction (MTJ) stack usable in a nonvolatile magnetic memory array of MTJ stacks, the MTJ stack comprising: a) a fixed ferromagnetic layer having its magnetic moment fixed in a preferred direction in the presence of an applied magnetic field caused by a current; b) an insulating tunnel barrier layer in contact with the fixed ferromagnetic layer; and c) a free ferromagnetic layer in contact with the insulating tunnel barrier layer, the free ferromagnetic layer comprising a synthetic anti-ferromagnet (SAF) stack comprising i) at least three ferromagnetic layers arranged anti-ferromagnetically relative to the next, and ii) at least two coupling layers, wherein the at least three ferromagnetic layers are separated by the at least two coupling layers.

Abstract: A light emitting device package and a lighting system are provided. According to one embodiment, a functional substrate; at least one light emitting element bonded onto the functional substrate; and at least one design-in thermal detection unit built onto the functional substrate are provided, wherein the design-in thermal detection unit is proximate to the light emitting element, and wherein the design-in thermal detection unit is configured to detect the temperature and transmit a temperature signal. The design-in thermal detection unit may be an NTC thermistor based on a semiconductor substrate. A control system may be included to detect temperature and make any necessary current adjustments in order to maintain consistent performance of the light emitting element.

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract: A semiconductor device has an element encapsulated in a resin mold. Metal leads protruding from the resin mold are solder plated except at the lead-tip end surfaces, and the exposed lead-tip end surfaces have an area less than half the cross-sectional area of the protruding metal leads. The semiconductor device is manufactured using a lead frame in which the metal leads are connected to a frame by plating bars having a thickness smaller than half the thickness of the metal leads. In another embodiment, the metal leads are connected to the frame by plating bars that extend sideways from the metal leads, and the end tips of the metal leads are entirely covered with plating to improve soldering wettability.

Abstract: The aim the disclosed process is to ensure maximum precision both at the level of the manufacturing of an electronic assembly from a chip with small dimensions as well as the level of the placement of such an assembly on an insulating substrate. This aim is achieved by a placement process on a support, called substrate, of at least one electronic assembly consisting of a chip including at least one electric contact on one of its faces, said contact being connected to a segment of conductive track, and said placement being carried out by means of a placement device holding and positioning said assembly on the substrate, comprising the following steps: formation of a segment of conductive track having a predetermined outline, transfer of the track segment onto the placement device, seizing of the chip with the placement device carrying the track segment in such a way that said track segment is placed on at least one contact of the chip.

Abstract: A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon.

Abstract: A top emission inverted OLED device is disclosed.

Abstract: A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).

Abstract: A radiation sensor includes an integrated circuit radiation sensor chip (1A) including first (7) and second (8) thermopile junctions connected in series to form a thermopile (7,8) within a dielectric stack (3). The first thermopile junction (7) is insulated from a substrate (2) of the chip. A resistive heater (6) in the dielectric stack for heating the first thermopile junction is coupled to a calibration circuit (67) for calibrating responsivity of the thermopile (7,8). The calibration circuit causes a current flow in the heater and multiplies the current by a resulting voltage across the heater to determine power dissipation. A resulting thermoelectric voltage (Vout) of the thermopile (7,8) is divided by the power to provide the responsivity of the sensor.

Abstract: A solar radiation collection system includes a first photovoltaic cell, a second photovoltaic cell, and an optical medium, the optical medium. The optical medium has a first zone configured to transmit radiation incident on the first zone to the first cell, a second zone disposed adjacent a side of the first zone, and a first dichroic surface configured to reflect a first portion of radiation incident on the second zone such that the reflected radiation is directed toward the first cell by internal reflection and to transmit a second portion of radiation incident on the second zone to the second cell.

Abstract: A radiation sensor (27) includes a radiation sensor chip (1) including first (7) and second (8) thermopile junctions connected to form a thermopile (7,8). The first thermopile junction is disposed in a floating portion of a dielectric membrane (3) thermally insulated from a silicon substrate (2) of the chip, and the second thermopile junction is disposed in the dielectric membrane directly adjacent to the substrate. Bump conductors (28) are bonded to corresponding bonding pads (28A) coupled to the thermopile (7,8) to physically and electrically connect the chip to conductors on a printed circuit board (23). The silicon substrate transmits infrared radiation to the thermopile while blocking visible light.

Abstract: A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate, the first metal layer providing local interconnection to the SRAM unit cell, a second metal layer formed over the first metal layer, the second metal layer including: a bit line and a complementary bit line each having a first thickness and a Vcc line disposed between the bit line and the complementary bit line, and a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness.

Abstract: The present invention includes a liquid crystal display device with an oxide film having high adhesiveness to a semiconductor layer or a pixel electrode to thereby prevent oxidation of a wiring material or the like, and includes a source electrode and a drain electrode having high conductivity, and a manufacturing method therefor. In one embodiment of the present invention, a liquid crystal display device has a TFT electrode of a TFT substrate, wherein a source electrode or a drain electrode includes a layer of mainly copper and an oxide covering an outer part of the layer. Further, in the present invention, the semiconductor layer or the pixel electrode and said source electrode or the drain electrode are in ohmic contact in the TFT electrode.

Abstract: An organic transistor includes a source electrode and a drain electrode, and an organic semiconductor layer disposed across between the source electrode and the drain electrode. The organic semiconductor layer includes a first semiconductor portion in a region where a gate electrode and the source electrode oppose each other, a second semiconductor portion in a region where the gate electrode and the drain electrode oppose each other, and a third semiconductor portion between the first semiconductor portion and the second semiconductor portion. The first semiconductor portion, the second semiconductor portion, and the third semiconductor portion satisfy the relationships W1<W3 and W2<W3, wherein W1 represents the average thickness of the first semiconductor portion, W2 represents the average thickness of the second semiconductor portion, and W3 represents the average thickness of the third semiconductor portion.

Abstract: An image sensor including a first epitaxial layer formed over a semiconductor substrate; first photodiodes formed spaced apart in the first epitaxial layer; a first isolation region electrically isolating the first photodiodes from each other; a second epitaxial layer formed over the first epitaxial layer; second photodiodes formed spaced apart in the second epitaxial layer; and a second isolation region electrically isolating the second photodiodes from each other.

Abstract: A three-dimensional (3D) semiconductor structure with high density and method of fabricating the same are disclosed. The 3D semiconductor structure comprises at least a first memory cell and a second memory cell stacked on the first memory cell. The first memory cell comprises a first conductive line and a second conductive line. The second memory cell comprises another first conductive line opposite to the first conductive line of the first memory cell, and the second conductive line formed between said two first conductive lines of the first and second memory cells. The first and second memory cells share the second conductive line when the 3D semiconductor structure is programming and erasing, and each of the first and second memory cells has a diode.

Abstract: Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction.

Abstract: Disclosed is an apparatus for wet treatment of a plate-like article, which includes: a spin chuck for holding and rotating the plate-like article including an element for holding the plate-like article at the plate-like article's edge and a gas supply element for directing gas towards the side of the plate-like article, which faces the spin chuck, wherein the gas supply element includes a gas nozzle rotating with the spin chuck, for providing a gas cushion between the plate-like article and the spin chuck; a fluid supply element for directing fluid onto the side of the plate-like article, which is facing the spin chuck, through a non-rotatable fluid nozzle.

Abstract: A semiconductor power module includes an insulated substrate mounting with a plurality of power semiconductor devices and a heat sink for radiating a heat generated from the plurality of power semiconductor devices, wherein the heat sink is integrally molded with a plurality of radiation fins on one surface of a planate base by forging work such that a metallic material filled into a female die of a predetermined shape is pressed by a male die of a predetermined shape, and the heat sink and the insulated substrate are bonded in metallic bonding with another surface opposite of one surface on which the radiation fins are formed with the base of the heat sink.

Abstract: A photoelectric composite wiring module includes a circuit substrate, an optical device, an LSI having a driver and an amplifier for the optical device, and a thin film wiring layer having an electrical wiring. The optical device is connected with the LSI by means of the electrical wiring. The optical device is formed on the circuit substrate and optically coupled to an optical waveguide formed in the circuit substrate. The thin film wiring layer is formed on the optical device to ensure that the optical device is electrically connected with the electrical wiring of the thin film wiring layer. The LSI is mounted on and electrically connected with the thin film wiring layer.

Abstract: A foldable microcircuit is initially a planar semiconductor wafer on which circuitry has been formed. The wafer is segmented into a plurality of tiles, and a plurality of hinge mechanisms are coupled between adjacent pairs of tiles such that the segmented wafer can be folded into a desired non-planar configuration having a high fill-factor and small gaps between tiles. The hinge mechanisms can comprise an organic material deposited on the wafer such that it provides mechanical coupling between adjacent tiles, with metal interconnections between tiles formed directly over the organic hinges, or routed between adjacent tiles via compliant bridges. Alternatively, the interconnection traces between tiles can serve as part or all of a hinge mechanism. The foldable microcircuit can be, for example, a CMOS circuit, with the segmented tiles folded to form, for example, a semi-spherical structure arranged to provide a wide FOV photodetector array.

Abstract: A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a series of alternating dummy lines that are connected through dummy vias. The dummy lines are offset from dummy lines in adjacent metal layers. Additionally, the dummy lines and dummy vias in the upper layers of the scribe line may be formed with larger dimensions than the dummy lines and dummy vias located in the lower layers.

Abstract: A solid-state imaging device includes: an imaging area in which light receiving portions are disposed; an interconnect layer disposed on the light receiving portions, the interconnect layer including metal interconnects having openings and first insulating films; inner-layer lenses formed over the interconnect layer in one-to-one relationship with the light receiving portions; a transparent second insulating film formed on the interconnect layer and the inner-layer lenses; top lenses formed on the second insulating film in one-to-one relationship with the light receiving portions, an upper face of each of the top lenses being a convexly curved face; and a transparent film on the top lenses, the transparent film being formed of a material having a refractive index smaller than a refractive index of the top lenses. In this way, a focal point of at least part of incident light can be situated above a semiconductor substrate.

Abstract: A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.