Abstract: The invention provides a semiconductor device with high reliability and smaller size and a method of manufacturing the same. A light emitting element as a device element is formed on the front surface of a semiconductor substrate, for example. In detail, an N-type semiconductor layer, a P-type semiconductor layer and pad electrodes are formed on the front surface of the semiconductor substrate. A device element receiving light from the light emitting element (e.g. a photodiode element), for example, and pad electrodes are formed on the front surface of another semiconductor substrate. The semiconductor substrates are attached and integrated with an adhesive layer being interposed therebetween. Wiring layers electrically connected to the pad electrodes and wiring layers electrically connected to the other pad electrodes are formed on the side surface of the semiconductor substrate.

Abstract: We describe a reference cell structure for determining data storing cell resistances in an SMT (spin moment transfer) MTJ (magnetic tunneling junction) MRAM array by comparing data cell currents with those of the reference cell. Since the reference cell also utilizes spin moment transfer (SMT) magnetic tunneling junction (MTJ) cells, there would ordinarily be the danger that the act of reading the reference cell could change its magnetization orientations and be a source of error for subsequent comparisons. Therefore the present invention describes a new circuit arrangement for the reference cell that directs read currents through two SMT MTJ cells in opposite directions so that the transfer of spin moments cannot affect the relative magnetization directions of the cells.

Abstract: Process and apparatus for fabricating a magnetic device is provided. Magnetic and/or nonmagnetic layers i n the device are etched by a mixed gas of a hydrogen gas and an inert gas such as N2 with using a mask of non-organic material such as Ta. As results, in a studied example, a MTJ taper angle is nearly vertical.

Abstract: A system and method is disclosed that transfers carrier boards in a handler that supports the testing of electronic devices. A carrier board can be transferred from the transfer start position to one of the mid transfer positions and the transfer final position. Carrier boards, which are spaced apart from each other in a chamber, can be gathered adjacent to each other in the circulation direction of carrier board. The transfer speed and the total circulation speed of the carrier boards can be enhanced. The transfer speed of carrier board can be easily controlled according to the test conditions.

Abstract: A touch sensor (touch panel) which can be formed over the same substrate as a display portion is provided. Alternatively, a touch sensor (touch panel) which does not cause degradation in the quality of an image displayed on a display portion is provided. The touch panel includes a light-emitting element and a microstructure in which a pair of electrodes facing each other is isolated with an insulating material. As the insulating material, an elastic material or a material having a hole is used so that a filler layer formed using the insulating material can be deformed when a movable portion operates. It is preferable to use a material which is softened or hardened by certain treatment (e.g., heat treatment or chemical treatment) after formation.

Abstract: A transceiver having a light source die, a photodetector die and a substrate is disclosed. The substrate has a first well in which the light source die is mounted and a second well in which the photodetector die is mounted. The substrate has a reflective surface which blocks light leaving the light source from reaching the photodetector unless the light is reflected by an object external to the transceiver. The reflecting surface of the second well in the substrate is shaped to concentrate light received from outside the transceiver onto the photodetector, and in one aspect of the invention it comprises a non-imaging optical element. The light source is powered by applying a potential between first and second contacts on the light source die. A signal is generated between first and second contacts on the photodetector die in response to illumination of the photodetector die.

Abstract: A display device including a first substrate, a first subpixel electrode, a second subpixel electrode corresponding to the first substrate, a second substrate and a common electrode formed on the second substrate is provided. The first subpixel electrode and the second subpixel electrode are formed on the first substrate. The second subpixel electrode is spaced apart from the first subpixel electrode. The common electrode has a first cutout and a second cutout. The first cutout is disposed over the first subpixel electrode and the second cutout is disposed over the second subpixel electrode. At least a portion of the first cutout has a first width and at least a portion of the second cutout has a second width different from the first width. The first width is larger than the second width in one embodiment. This structure enhances the aperture ratio and the brightness of the display device. Failures such as a residual image, stain or fingerprint may be reduced and the picture quality is improved.

Abstract: A method for fabricating a semiconductor device, includes forming a porous dielectric film above a substrate using a porous insulating material, forming an opening in the porous dielectric film, repairing film quality of the porous dielectric film on a surface of the opening by feeding a predetermined gas replacing a Si—OH group to the opening, and performing pore sealing of the surface of the opening using the same predetermined gas as that used for film quality repairs after repairing the film quality.

Abstract: A method of device growth and p-contact processing that produces improved performance for non-polar III-nitride light emitting diodes and laser diodes. Key components using a low defect density substrate or template, thick quantum wells, a low temperature p-type III-nitride growth technique, and a transparent conducting oxide for the electrodes.

Abstract: A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only.

Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.

Abstract: AN LED chip package body provides an LED chip with a pad-installed surface, a plurality of pads disposed on the pad-installed surface and a rear surface formed opposite the pad-installed surface. The LED chip package body further has a light-reflecting coating disposed on the pad-installed surface of the LED chip and a plurality of pad-exposed holes for exposure of the corresponding pads of the LED chip. The LED chip package body further comprises a light-transparent element disposed on the rear surface of the LED chip and a plurality of conductive projecting blocks. Each of the conductive projecting blocks is disposed on the corresponding pad of the LED chip.

Abstract: A storage system and methods for operating a storage system are disclosed. The storage system includes a storage system assembly positioned at a height that is greater than a height of a tool used for loading and unloading substrates to be processed. The storage system locally stores one or more containers of substrates. The storage system assembly includes a plurality of storage shelves, and each of the plurality of storage shelves have shelf plates with shelf features for supporting a container. Each of the plurality of storage shelves are coupled to a chain to enable horizontal movement and each is further coupled to a rail to enable guiding to one or more positions. A motor is coupled to a drive sprocket for moving the chain, such that each of the plurality of storage shelves move together along the rail to the one or more positions. The rail has at least some sections that are linear and some sections that are nonlinear and the sections are arranged in a loop.

Abstract: To provide a chip supply pallet preventing destruction of a chip and preventing a reduction in a productivity from being brought about in exchanging a wafer sheet, the chip supply pallet includes a first member 33 having a tension ring 51 brought into contact with a wafer sheet from a lower side, and a fixing member 54 of fixing a ring frame holding the wafer sheet on an inner side on a lower side of the wafer sheet brought into contact with the tension ring 51, and a second member 34 having a fixed portion for fixing to a predetermined position of a chip supply apparatus and a held portion 36 of being held when the chip interchanging pallet 3 is transferred, and the first member 33 is configured to be able to rotationally displace relative to the second member 34 fixed to the predetermined position of the chip supply apparatus.

Abstract: A storage system and methods for operating a storage system are disclosed. The storage system includes a storage system assembly positioned at a height that is greater than a height of a tool used for loading and unloading substrates to be processed. The storage system locally stores one or more containers of substrates. The storage system assembly includes a plurality of storage shelves, and each of the plurality of storage shelves have shelf plates with shelf features for supporting a container. Each of the plurality of storage shelves are coupled to a chain to enable horizontal movement and each is further coupled to a rail to enable guiding to one or more positions. A motor is coupled to a drive sprocket for moving the chain, such that each of the plurality of storage shelves move together along the rail to the one or more positions. The rail has at least some sections that are linear and some sections that are nonlinear and the sections are arranged in a loop.

Abstract: Adjacent to an opening portion in an FISM system is provided an enclosure that encloses the operation space of a door and has a second opening portion opposed to the opening portion. A curtain nozzle is provided above the upper edge of the opening portion in the upper portion in the enclosure. A purge gas is supplied from the curtain nozzle along a direction from the upper edge to the lower edge of the opening portion. In addition, a gas outlet through which the purge gas flows from the interior of the enclosure out into the exterior is provided on the wall of the enclosure to which the purge gas flowing in the above described direction is directed, whereby an increase in the partial pressure of oxidizing gases in the interior of the FOUP is prevented.

Abstract: A method is provided for picking up a chip 13 from a fixing jig 3 to which the chip 13 is fixed. The fixing jig 3 consists of a jig base 30 having a plurality of protrusions 36 on one side and a sidewall 35 having a height almost equivalent to that of the protrusion 36 at the outer circumference of the one side, and an contact layer 31 that is laminated on the surface of the jig base 30 having the protrusions 36 and that is bonded on the upper surface of the sidewall 35. A section space 37 is formed on the surface of the jig base 30 having the protrusions by the contact layer 31, the protrusions 36 and the sidewall 35, and at least one through hole 38 penetrating the outside and the section space 37 is provided in the jig base 30.

Abstract: A phase change random access memory for actively removing residual heat and a method of manufacturing the same are presented. The phase change random access memory includes a semiconductor substrate, a phase change pattern, a heating electrode and a cooling electrode. The phase change pattern is on the semiconductor substrate. The heating electrode is electrically coupled to the phase change pattern for heating the phase change pattern. The cooling electrode is electrically coupled to the phase change pattern for removing residual heat from the phase change pattern.

Abstract: In a technique connecting between bonding pads of semiconductor chips, contact between wires is prevented. A semiconductor device of the present embodiment is provided with a semiconductor chip 1 in which a plurality of bonding pads 3 are arranged in line, a semiconductor chip 2 in which a plurality of bonding pads 4 are arranged in line substantially parallel to the plurality of bonding pads 3, and a plurality of wires 7 which connect the bonding pads 3 to the bonding pads 4 respectively. At least one of the wires 7 is bended with respect to a reference straight line S which passes through the bonding pad 3 and the bonding pad 4 which are connected by the wire 7. The bended wire is extended out from the bonding pad 4 in a certain direction in which a distance between the bended wire and an adjacent wire which is adjacent to the bended wire is larger than a distance between the reference straight line of the bended wire and the reference straight line of the adjacent wire.

Abstract: A single-crystal semiconductor layer is provided in a large area over a large-sized glass substrate, whereby a large-scale SOI substrate is obtained. A single-crystal semiconductor substrate provided with an embrittlement layer and a dummy substrate are bonded to each other, and the single-crystal semiconductor substrate is separated at the embrittlement layer as a boundary by heat treatment to form a piece of single-crystal semiconductor over the dummy substrate. The dummy substrate is divided to form a piece of single-crystal semiconductor. The piece of single-crystal semiconductor is bonded to a supporting substrate, and the piece of single-crystal semiconductor is separated from the dummy substrate. Then, a plurality of pieces of single-crystal semiconductor are arranged and transferred to the large-sized glass substrate.

Abstract: An image sensor and fabricating method thereof which reduces a light intensity differential between a pixel center and a pixel edge and prevents crosstalk. The image sensor can include a plurality of convex lens provided within a passivation layer and in vertical alignment with a corresponding photodiode, each convex lens including a color filter; having a predetermined color array, and a plurality of microlens provided over the passivation layer and in vertical alignment with a corresponding color filer.

Abstract: An LED chip package structure with high-efficiency light-emitting effect includes a substrate unit, a light-emitting unit, a package colloid unit, and a frame unit. The light-emitting unit has a plurality of LED chips electrically arranged on the substrate unit. The package colloid unit has a longitudinal package colloid covering the LED chips, and the longitudinal package colloid has a cambered colloid surface and a light-emitting colloid surface respectively formed on its top surface and a lateral surface thereof. The frame unit that is a frame layer covering the substrate unit and disposed around a lateral side of the longitudinal package colloid for exposing the light-emitting colloid surface of the longitudinal package colloid.

Abstract: A system for delivering a desired mass of gas, including a chamber, a first valve controlling flow into the chamber, a second valve controlling flow out of the chamber, a pressure transducer connected to the chamber, an input device for providing a desired mass to be delivered, and a controller connected to the valves, the pressure transducer and the input device. The controller is programmed to receive the desired mass from the input device, close the second valve and open the first valve, receive chamber pressure measurements from the pressure transducer, and close the inlet valve when pressure within the chamber reaches a predetermined level. The controller is then programmed to wait a predetermined waiting period to allow the gas inside the chamber to approach a state of equilibrium, then open the outlet valve at time=t0, and close the outlet valve at time=t* when the mass of gas discharged equals the desired mass.

Abstract: A chip scale package (CSP) semiconductor device can include a semiconductor layer, circuitry on an active surface of the semiconductor layer, and a diamond layer on a back side of the semiconductor layer. The diamond layer can provide an efficient heat sink for the semiconductor layer, with a thermal conductivity which can be more than three times greater than the thermal conductivity of copper. Further, a hardness of the diamond layer (up to about 10 times stronger than silicon) can provide effective protection against damage to the exposed semiconductor layer, for example during manufacturing, handling, and use of the CSP device. Thus a thin protective diamond layer can be used, which can result in a very thin CSP package design.

Abstract: Disclosed is a device for handling devices, such as reticles, in a semiconductor manufacturing environment. In one illustrative embodiment, the device includes a body, a plurality of spaced-apart grippers and a plurality of magnets for producing a magnetic force to secure a semiconducting substrate or reticle between the spaced-apart grippers. In one illustrative embodiment, the method includes providing a pick comprised of a plurality of spaced-apart grippers and generating a magnetic force to grasp a semiconducting substrate or a reticle between the grippers.

Abstract: A method of manufacture of an integrated circuit communication system including providing a semiconductor wafer; and fabricating a cross-over current mirror driver on the semiconductor wafer for generating a crossing point at a reference voltage.

Abstract: A magnetic element having a ferromagnetic pinned layer, a ferromagnetic free layer, a non-magnetic spacer layer therebetween, and a porous non-electrically conducting current confinement layer between the free layer and the pinned layer. The current confinement layer forms an interface either between the free layer and the non-magnetic spacer layer or the pinned layer and the non-magnetic spacer layer.

Abstract: An image sensor with a plurality of photodiodes that each is adjacent to a first region constructed from a first type of material and comprises a second region constructed from a second type of material. Located between second regions of adjacent photodiodes is a barrier region. The photodiodes are reverse biased to create depletion regions within the substrate. The barrier region limits the lateral growth of the depletion regions and inhibits depletion merger between adjacent photodiodes.

Abstract: A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.

Abstract: A light source and method for making the same are disclosed. The light source includes a base member and a lead structure. The lead structure is attached to the base member such that the lead structure extends beyond the base member and has an opening for accessing a surface of the base member. A die containing a light emitting semiconductor device is bonded to the surface of the base member. The die is electrically connected to the lead structure and overlaid with a transparent material. An electrically insulating layer is bonded between the lead structure and the base member, the electrically insulating layer having an opening for accessing the surface of the base member. The electrically insulating layer can be an adhesive for bonding the lead structure to the base member.

Abstract: A system for handling wafers comprising: at least one unload station; at least one intermediate station designed to hold the wafers at an angle; a processing station; and a transfer device configured to move the wafers between the stations. The intermediate station may be configured to receive the wafers in a back-to-back arrangement. An apparatus for handling wafers comprising: on one side, a vacuum gripper configured to grip individual wafers; and, on the other side, a gravity gripper configured to support one or more wafers when positioned beneath the wafers and lifted. A method for handling wafers, comprising: unloading wafers; transferring the wafers to an intermediate station; transferring the wafers from the intermediate station to a processing station; treating the wafers; unloading the wafers from the processing station; and reloading the wafers in a carrier, wherein the wafers are unloaded, transferred and reloaded by a transfer device.

Abstract: A display substrate includes a base substrate and first, second and third color filters. The first, second and third color filters are disposed on the base substrate adjacent to each other and convert incident light into color light. At least one of the first, second and third color filters includes pigment particles which are regularly arranged to have refractive index anisotropy.

Abstract: An apparatus has a crystalline organic semiconducting region that includes polyaromatic molecules. A source electrode and a drain electrode of a field-effect transistor are both in contact with the crystalline organic semiconducting region. A gate electrode of the field-effect transistor is located to affect the conductivity of the crystalline organic semiconducting region between the source and drain electrodes. A dielectric layer of a first dielectric that is substantially impermeable to oxygen is in contact with the crystalline organic semiconducting region. The crystalline organic semiconducting region is located between the dielectric layer and a substrate. The gate electrode is located on the dielectric layer. A portion of the crystalline organic semiconducting region is in contact with a second dielectric via an opening in the dielectric layer. A physical interface is located between the second dielectric and the first dielectric.

Abstract: A semiconductor device having linear zigzag(s) for wire bonding is revealed, primarily comprising a chip, a plurality of leads made of a lead frame and a plurality of bonding wires electrically connecting the chip and the leads. At least one of the leads has a linear zigzag including a first finger and a second finger connected each other in a zigzag form. One end of one of the bonding wire is bonded to a bonding pad on the chip and the other end is selectively bonded to either the first finger or the second finger but not both in a manner that the wire-bonding direction of the bonding wire is parallel to or in a sharp angle with the direction of the connected fingers for easy wire bonding processes. Therefore, the semiconductor device can assemble chips with diverse dimensions or with diverse bonding pads layouts by flexible wire-bonding angles at linear zigzag to avoid electrical short between the adjacent leads.

Abstract: An image capturing apparatus has a plurality of solid-state image capturing devices each having light receiving sections laminated in a depth direction of a semiconductor substrate. The devices are sequentially arranged in a direction along a substrate surface. Incident light waves having wavelength bands corresponding to depths of respective light receiving sections are detected there and generate signal charges. Bands are associated with light receiving sections by the wavelength dependence of the optical absorption. Trench sections each reach from a light incident surface or an opposite substrate surface to respective light receiving sections that do not overlap each other in a plane view. Electric charge transfer sections transfer electric charges independently from the light receiving sections via side wall portions of their respective trenches to the light incident surface side or the opposite substrate surface side at the time of driving readout gate electrodes at each trench section.

Abstract: A dislocation-free sheet may be formed from a melt. A sheet of material with a first width is formed on a melt of the material using a cooling plate. This sheet has dislocations. The sheet is transported with respect to the cooling plate and the dislocations migrate to an edge of the sheet. The first width of the sheet is increased to a second width by the cooling plate. The sheet does not have dislocations at the second width. The cooling plate may have a shape with two different widths in one instance. The cooling plate may have segments that operate at different temperatures to increase the width of the sheet in another instance. The sheet may be pulled or flowed with respect to the cooling plate.

Abstract: A micromachine device processing method for dividing a functional wafer, which has micromachine devices formed in a plurality of regions demarcated by streets formed in a lattice pattern on a face of the functional wafer, along the streets into the individual micromachine devices, each micromachine device having a moving portion and an electrode, comprising: a cap wafer groove forming step of forming dividing grooves, which have a depth corresponding to a finished thickness of a cap wafer for protecting the face of the functional wafer, along regions in one surface of the cap wafer which correspond to areas of the electrodes of the micromachine devices; a cap wafer joining step of joining the one surface of the cap wafer subjected to the cap wafer groove forming step to the face of the functional wafer at peripheries of the moving portions; a cap wafer grinding step of grinding the other surface of the cap wafer joined to the face of the functional wafer to expose the dividing grooves to the outside; and a cu

Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

Abstract: Provided are an alignment key, a method for fabricating the alignment key, and a method for fabricating a thin film transistor substrate using the alignment key. The method for fabricating the alignment key includes forming a first metal layer on a base substrate, forming a first alignment key and a first mark portion of a second alignment key by selectively patterning the first metal layer, forming a dielectric on the first metal layer, forming a second metal layer on the dielectric, and forming a second mark portion of the second alignment key on the dielectric by selectively patterning the second metal layer.

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: The present disclosure provides a semiconductor memory device. The device includes a bottom electrode over a semiconductor substrate; an anti-ferromagnetic layer disposed over the bottom electrode; a pinned layer disposed over the anti-ferromagnetic layer; a barrier layer disposed over the pinned layer; a first ferromagnetic layer disposed over the barrier layer; a buffer layer disposed over the first ferromagnetic layer, the buffer layer including tantalum; a second ferromagnetic layer disposed over the buffer layer; and a top electrode disposed over the second ferromagnetic layer.

Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

Abstract: A method of forming a phase-change random access memory (PRAM) cell and PRAM arrangement, and embodiments of phase-change random access memory (PRAM) cells and PRAM arrangements are disclosed. A phase-change random access memory (PRAM) cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) coupled to the heater resistor, and a top electrode coupled to the phase change material. An active region between the heater resistor and the phase change material is defined by a thickness of the heater resistor.

Abstract: A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) formed over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material.

Abstract: An optical sensor device comprises a light source, a light detector, and an opaque light barrier including a first portion to block light from being transmitted directly from the source to the detector. A second portion of the light barrier extends from the first portion in a direction towards the light source, such that a portion of the second portion covers at least a portion of light emitting element(s) of the source, to reduce an amount of specular reflections, if a light transmissive cover plate were placed over the sensor. Additionally, a third portion of the barrier can extend from the first portion, in a direction towards to the detector, such that a portion of the third portion covers at least a portion of light detecting element(s) of the detector, to reduce an amount of specular reflections that would be detected by the detecting element(s) of the detector, if a light transmissive cover plate were placed over the sensor. Additionally, an off-centered lens can cover a portion of the light source.

Abstract: Insulating films (13, 14) are formed on the surface of a semiconductor wafer (30) on the side on which a plurality of devices are formed. Then, conductor layers (15, 16) are formed to cover opening portions from which electrode pads (12) of each device are exposed. Furthermore, a resist layer (R2) is formed to have opening portions from which terminal formation portions of the conductor layer are exposed, and metal posts (17) are formed on the terminal formation portions of the conductor layer (16) using the resist layer (R2) as a mask. Then, thinning of the semiconductor wafer (30) is performed to a predetermined thickness by grinding the back surface thereof. Thereafter, the resist layer (R2) is removed; an unnecessary portion (15) of the conductor layer is further removed; sealing with sealing resin is performed with the top portions of the metal posts (17) being exposed; metal bumps are bonded to the top portions of the metal posts (17); and the semiconductor wafer is divided into each device.

Abstract: A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an adjoining exposed area of the protective tape, the protective coating, protective tape, and wafer forming a protected wafer assembly, curing the frame-supported protective coating, cutting the protected wafer assembly from the protective tape surrounding the protective coating, wet processing the protected wafer assembly, laminating the protected wafer assembly with a second tape, dicing the wafer, and picking up the die from the protective tape.

Abstract: A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.

Abstract: An automatic or semiautomatic method of assembly of radiation digital imaging tiles to form a one or two dimensional imaging panel whereby the imaging tiles are provided with alignment mark(s), inherent or specific, and a mother board or substrate is also provide with alignment mark(s) and the imaging tiles are mounted on the mother board by means of mechanical pick and place mechanism, whereby the distances of corresponding alignment mark are set to predetermined values, programmed in the automatic machine.