Epitaxial Deposition Of Group Iii-v Compound (epo) Patents (Class 257/E21.108)
  • Patent number: 8450192
    Abstract: Growth methods for planar, non-polar, Group-III nitride films are described. The resulting films are suitable for subsequent device regrowth by a variety of growth techniques.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: May 28, 2013
    Assignees: The Regents of the University of California, Japan Science and Technology Center
    Inventors: Benjamin A. Haskell, Paul T. Fini, Shigemasa Matsuda, Michael D. Craven, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Publication number: 20130130481
    Abstract: Methods and apparatus for generating and delivering atomic hydrogen to the growth front during the deposition of a III-V film are provided. The apparatus adapts HWCVD technology to a system wherein the Group III precursor and the Group V precursor are delivered to the surface in isolated processing environments within the system. Multiple HWCVD units may be incorporated so that the atomic hydrogen parameters may be varied in a combinatorial manner for the development of III-V films.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Applicant: Intermolecular, Inc.
    Inventors: Thai Cheng Chua, Timothy Joseph Franklin, Philip Kraus
  • Patent number: 8440549
    Abstract: A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: May 14, 2013
    Assignees: Fujitsu Limited, Hitachi Cable Co., Ltd.
    Inventors: Kenji Imanishi, Toshihide Kikkawa, Takeshi Tanaka, Yoshihiko Moriya, Yohei Otoki
  • Patent number: 8435820
    Abstract: A circuit structure includes a substrate and a film over the substrate and including a plurality of portions allocated as a plurality of rows. Each of the plurality of rows of the plurality of portions includes a plurality of convex portions and a plurality of concave portions. In each of the plurality of rows, the plurality of convex portions and the plurality of concave portions are allocated in an alternating pattern.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: May 7, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ding-Yuan Chen
  • Patent number: 8420543
    Abstract: A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: April 16, 2013
    Assignee: National Chiao Tung University
    Inventors: Wei-I Lee, Yen-Hsien Yeh, Yin-Hao Wu, Tzu-Yi Yu
  • Publication number: 20130082278
    Abstract: A nitride semiconductor device and a method to produce the same are disclosed. The method includes steps of sequentially growing a channel layer and a first layer with bandgap energy Eg greater than that of channel layer; forming a gate replica on the first layer; selectively growing a second layer with Eg also greater than or equal to Eg of the channel layer; removing the gate replica to form a recess in the second layer; and forming the gate electrode in the recess and onto the first layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 4, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Sumitomo Electric Industries, Ltd.
  • Patent number: 8410511
    Abstract: High temperature semiconducting materials in a freestanding epitaxial chip enables the use of high temperature interconnect and bonding materials. Process materials can be used which cure, fire, braze, or melt at temperatures greater than 400 degrees C. These include, but are not limited to, brazing alloys, laser welding, high-temperature ceramics and glasses. High temperature interconnect and bonding materials can additionally exhibit an index of refraction intermediate to that of the freestanding epitaxial chip and its surrounding matrix. High index, low melting point glasses provide a hermetic seal of the semiconductor device and also index match the freestanding epitaxial chip thereby increasing extraction efficiency. In this manner, a variety of organic free semiconducting devices, such as solid-sate lighting sources, can be created which exhibit superior life, efficiency, and environmental stability.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: April 2, 2013
    Assignee: Goldeneye, Inc.
    Inventors: Scott M. Zimmerman, Karl W. Beeson, William R. Livesay
  • Patent number: 8410523
    Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, an emitter device can include monolithic quantum well (QW) lasers directly disposed on a SOI or silicon substrate for waveguide coupled integration. In another exemplary embodiment, a superlattice (SL) photodetector and its focal plane array can include a III-Sb active region formed over a large GaAs substrate using SLS technologies.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: April 2, 2013
    Inventors: Diana L. Huffaker, Larry R. Dawson, Ganesh Balakrishnan
  • Patent number: 8410524
    Abstract: Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor 11, a supporting substrate 13 is composed of AlN, AlGaN, or GaN, specifically. An AlYGa1?YN epitaxial layer 15 has a full-width-at-half maximum of (0002) plane XRD of 150 sec or less. A GaN epitaxial layer 17 is provided between the gallium nitride supporting substrate and the AlYGa1?YN epitaxial layer (0<Y?1). A Schottky electrode 19 is provided on the AlYGa1?YN epitaxial layer 15. The Schottky electrode 19 constitutes a gate electrode of the high electron mobility transistor 11. The source electrode 21 is provided on the gallium nitride epitaxial layer 15. The drain electrode 23 is provided on the gallium nitride epitaxial layer 15.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: April 2, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tatsuya Tanabe, Kouhei Miura, Makoto Kiyama, Takashi Sakurada
  • Publication number: 20130062734
    Abstract: Provided are a crystalline film in which variations in the crystal axis angle after separation from a substrate for epitaxial growth have been eliminated, and various devices in which the properties thereof have been improved by including the crystalline film. And the crystalline film has a thickness of 300 ?m or more and 10 mm or less and reformed region pattern is formed in an internal portion of the crystalline film.
    Type: Application
    Filed: March 4, 2011
    Publication date: March 14, 2013
    Applicants: DISCO CORPORATION, NAMIKI SEIMITSU HOUSEKI KABUSHIKI KAISHA
    Inventors: Hideo Aida, Natsuko Aota, Hitoshi Hoshino, Kenji Furuta, Tomosaburo Hamamoto, Keiji Honjo
  • Publication number: 20130052804
    Abstract: A method and apparatus for chemical vapor deposition and/or hydride vapor phase epitaxial deposition are provided. The apparatus generally include a lower bottom plate and an upper bottom plate defining a first plenum. The upper bottom plate and a mid-plate positioned above the upper bottom plate define a heat exchanging channel. The mid-plate and a top plate positioned above the mid-plate define a second plenum. A plurality of gas conduits extend from the second plenum through the heat exchanging channel and the first plenum. The method generally includes flowing a first gas through a first plenum into a processing region, and flowing a second gas through a second plenum into a processing region. A heat exchanging fluid is introduced to a heat exchanging channel disposed between the first plenum and the second plenum. The first gas and the second gas are then reacted to form a film on a substrate.
    Type: Application
    Filed: October 8, 2010
    Publication date: February 28, 2013
    Applicant: Applied Materials, Imn,
    Inventor: Eddy J. Song
  • Patent number: 8383439
    Abstract: The present invention provides an apparatus for manufacturing a group-III nitride semiconductor layer having high crystallinity. An embodiment of the present invention provides an apparatus for manufacturing a group-III nitride semiconductor layer on a substrate 11 using a sputtering method. The apparatus includes: a chamber 41; a target 47 that is arranged in the chamber 41 and includes a group-III element; a first plasma generating means 51 that generates a first plasma for sputtering the target 47 to supply raw material particles to the substrate 11; a second plasma generating means 52 that generates a second plasma including a nitrogen element; and a control means that controls the first plasma generating means 51 and the second plasma generating means 52 to alternately generate the first plasma and the second plasma in the chamber 41.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: February 26, 2013
    Assignee: Showa Denko K.K.
    Inventors: Yasunori Yokoyama, Takehiko Okabe, Hisayuki Miki
  • Patent number: 8368183
    Abstract: A nitride semiconductor device is provided that prevents development of cracks, that has nitride semiconductor thin films with uniform thicknesses and good growth surface flatness, and is thus consistent in characteristics, and that can be fabricated at a satisfactory yield. In this nitride semiconductor device, the nitride semiconductor thin films are grown on a substrate having an off-angle between a direction normal to the surface of ridges and the crystal direction <0001>. This helps either reduce or intentionally promote diffusion or movement of the atoms or molecules of a source material of the nitride semiconductor thin films through migration thereof. As a result, a nitride semiconductor growth layer with good surface flatness can be formed, and thus a nitride semiconductor device with satisfactory characteristics can be obtained.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: February 5, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Eiji Yamada, Takeshi Kamikawa, Masahiro Araki
  • Publication number: 20130012003
    Abstract: Atomic layer deposition (ALD) processes for forming thin films comprising GaN are provided. In some embodiments, ALD processes for forming doped GaN thin films are provided. The thin films may find use, for example, in light-emitting diodes.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 10, 2013
    Inventors: Suvi Haukka, Viljami J. Pore, Antti Niskanen
  • Patent number: 8349078
    Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 8, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Yu Saitoh, Kazuhide Sumiyoshi, Akihiro Hachigo, Makoto Kiyama, Seiji Nakahata
  • Patent number: 8349629
    Abstract: A semiconductor light-emitting element includes a first semiconductor layer having a first conduction type, a second semiconductor layer having a second conduction type, an active layer provided between the first and second semiconductor layers, a polarity inversion layer provided on the second semiconductor layer, and a third semiconductor layer having the second conduction type provided on the polarity inversion layer. Crystal orientations of the first through third semiconductor layers are inverted, with the polarity inversion layer serving as a boundary. The first and third semiconductor layers have uppermost surfaces made from polar faces having common constitutional elements. Hexagonal conical protrusions arising from a crystal structure are formed at outermost surfaces of the first and third semiconductor layers. The first through third semiconductor layers are made from a wurtzite-structure group III nitride semiconductor, and are layered along a C-axis direction of the crystal structure.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: January 8, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Yusuke Yokobayashi, Satoshi Tanaka, Masahiko Moteki
  • Patent number: 8349711
    Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: January 8, 2013
    Assignee: Kyma Technologies, Inc.
    Inventors: Edward A. Preble, Lianghong Liu, Andrew D. Hanser, N. Mark Williams, Xueping Xu
  • Patent number: 8334154
    Abstract: A method for producing quantum dots embedded in a matrix on a substrate includes the steps of: depositing a precursor on the substrate, the precursor including at least one first metal or a metal compound; contacting the deposited precursor and uncovered areas of the substrate with a gas-phase reagent including at least one second metal and/or a chalcogen; and initiating a chemical reaction between the precursor and the reagent by raising a temperature thereof simultaneously with or subsequent to the contacting so that the matrix consists exclusively of elements of the reagent.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: December 18, 2012
    Assignee: Helmholtz-Zentrum Berlin Fuer Materialien und Energie GmbH
    Inventors: David Fuertes Marón, Sebastian Lehmann, Sascha Sadewasser, Martha Christina Lux-Steiner
  • Patent number: 8329511
    Abstract: A nitride crystal or wafer with a removable surface layer comprises a high quality nitride base crystal, a release layer, and a high quality epitaxial layer. The release layer has a large optical absorption coefficient at wavelengths where the base crystal is substantially transparent and may be etched under conditions where the nitride base crystal and the high quality epitaxial layer are not. The high quality epitaxial layer may be removed from the nitride base crystal by laser liftoff or by chemical etching after deposition of at least one epitaxial device layer. The nitride crystal with a removable surface layer is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: December 11, 2012
    Assignee: Soraa, Inc.
    Inventor: Mark P. D'Evelyn
  • Publication number: 20120295418
    Abstract: Methods are disclosed for growing high crystal quality group III-nitride epitaxial layers with advanced multiple buffer layer techniques. In an embodiment, a method includes forming group III-nitride buffer layers that contain aluminum on suitable substrate in a processing chamber of a hydride vapor phase epitaxy processing system. A hydrogen halide or halogen gas is flowing into the growth zone during deposition of buffer layers to suppress homogeneous particle formation. Some combinations of low temperature buffers that contain aluminum (e.g., AlN, AlGaN) and high temperature buffers that contain aluminum (e.g., AlN, AlGaN) may be used to improve crystal quality and morphology of subsequently grown group III-nitride epitaxial layers. The buffer may be deposited on the substrate, or on the surface of another buffer. The additional buffer layers may be added as interlayers in group III-nitride layers (e.g., GaN, AlGaN, AlN).
    Type: Application
    Filed: May 10, 2012
    Publication date: November 22, 2012
    Inventors: Yuriy Melnik, Lu Chen, Hidehiro Kojiri
  • Patent number: 8294245
    Abstract: Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: October 23, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideaki Nakahata, Shinsuke Fujiwara, Takashi Sakurada, Yoshiyuki Yamamoto, Seiji Nakahata, Tomoki Uemura
  • Publication number: 20120258581
    Abstract: The metal-organic chemical vapor deposition (MOCVD) fabrication of group III-nitride materials using in-situ generated hydrazine or fragments there from is described. For example, a method of fabricating a group III-nitride material includes forming hydrazine in an in-situ process. The hydrazine, or fragments there from, is reacted with a group III precursor in a metal-organic chemical vapor deposition (MOCVD) chamber. From the reacting, a group III-nitride layer is formed above a substrate.
    Type: Application
    Filed: March 6, 2012
    Publication date: October 11, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Karl Brown, Kevin Griffin, David Bour, Olga Kryliouk
  • Patent number: 8283239
    Abstract: High quality free standing GaN is obtained using a new modification of the Epitaxial Lateral Overgrowth technology in which 3D islands or features are created only by tuning the growth parameters. Smoothing these islands (2D growth) is achieved thereafter by setting growth conditions producing enhanced lateral growth. The repetition of 3D-2D growth results in multiple bending of the threading dislocations thus producing thick layers or free standing GaN with threading dislocation density below 106 cm?2.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: October 9, 2012
    Assignee: Saint-Gobain Cristaux & Detecteurs
    Inventors: Bernard Beaumont, Jean-Pierre Faurie, Pierre Gibart, Therese Gibart, legal representative
  • Publication number: 20120248577
    Abstract: A method according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor layer from a gas containing gallium, a gas containing nitrogen, and a gas containing indium. The concentration of indium in the III-nitride semiconductor structure is greater than zero and less than 1020 cm?3. A structure according to embodiments of the invention includes a super lattice of alternating first and second III-nitride layers. The first layers are more highly doped than the second layers. The average dopant concentration in the super lattice is less than 1020 cm?3.
    Type: Application
    Filed: April 4, 2011
    Publication date: October 4, 2012
    Applicant: EPOWERSOFT INC.
    Inventors: Linda T. Romano, David P. Bour, Isik C. Kizilyalli, Hui Nie, Thomas R. Prunty
  • Publication number: 20120244686
    Abstract: An exemplary method for fabricating a semiconductor device includes the steps (a) growing a p-type gallium nitride-based compound semiconductor layer in a heated atmosphere; (b) cooling the p-type gallium nitride-based compound semiconductor layer; (c) forming three or more well layers before the step (a); and (d) forming an n-type semiconductor layer on a substrate before the step (c), wherein the step (c) includes growing each of the well layers to a thickness of 5 nm or more with the supply of the hydrogen gas to the reaction chamber cut off, and wherein the step (a) includes supplying hydrogen gas to the reaction chamber, and wherein the step (b) includes cooling the p-type gallium nitride-based compound semiconductor layer with the supply of the hydrogen gas to the reaction chamber cut off.
    Type: Application
    Filed: June 1, 2012
    Publication date: September 27, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Ryou KATO, Masaki FUJIKANE, Akira INOUE, Toshiya YOKOGAWA
  • Patent number: 8273592
    Abstract: The object of the present invention is to provide a method of manufacturing a Group-III nitride semiconductor light-emitting device that is highly productive and that enables production of a device having excellent light-emitting properties; a Group-III nitride semiconductor light-emitting device; and a lamp using the light emitting device.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: September 25, 2012
    Assignee: Showa Denko K.K.
    Inventors: Yasunori Yokoyama, Hisayuki Miki
  • Patent number: 8264006
    Abstract: A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: September 11, 2012
    Assignees: Fujitsu Limited, Hitachi Cable Co., Ltd.
    Inventors: Kenji Imanishi, Toshihide Kikkawa, Takeshi Tanaka, Yoshihiko Moriya, Yohei Otoki
  • Patent number: 8264005
    Abstract: A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: September 11, 2012
    Assignee: Fujitsu Limited
    Inventors: Kenji Imanishi, Toshihide Kikkawa, Takeshi Tanaka, Yoshihiko Moriya, Yohei Otoki
  • Patent number: 8258051
    Abstract: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).
    Type: Grant
    Filed: May 17, 2009
    Date of Patent: September 4, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8257993
    Abstract: Provided are a light emitting device and a method of fabricating the same. The light emitting device comprises: a first conductive semiconductor layer; an active layer comprising an InGaN well layer and a GaN barrier layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer. The GaN barrier layer comprises an AlGaN layer.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: September 4, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Dae Sung Kang, Hyo Kun Son
  • Patent number: 8252662
    Abstract: A method for manufacturing a plurality light emitting diodes includes providing a gallium nitride containing bulk crystalline substrate material configured in a non-polar or semi-polar crystallographic orientation, forming an etch stop layer, forming an n-type layer overlying the etch stop layer, forming an active region, a p-type layer, and forming a metallization. The method includes removing a thickness of material from the backside of the bulk gallium nitride containing substrate material. A plurality of individual LED devices are formed from at least a sandwich structure comprising portions of the metallization layer, the p-type layer, active layer, and the n-type layer. The LED devices are joined to a carrier structure.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: August 28, 2012
    Assignee: Soraa, Inc.
    Inventors: Christiane Poblenz, Mathew C. Schmidt, Daniel F. Feezell, James W. Raring, Rajat Sharma
  • Publication number: 20120184088
    Abstract: A method for selective deposition of semiconductor materials in semiconductor processing is disclosed. In some embodiments, the method includes providing a patterned substrate comprising a first region and a second region, where the first region comprises an exposed first semiconductor material and the second region comprise an exposed insulator material. The method further includes selectively providing a film of the second semiconductor material on the first semiconductor material of the first region by providing a precursor of a second semiconductor material, a carrier gas that is not reactive with chlorine compounds, and tin-tetrachloride (SnCl4). The tin-tetrachloride inhibits the deposition of the second semiconductor material on the insulator material of the second region.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 19, 2012
    Applicant: IMEC
    Inventors: Benjamin VINCENT, Roger LOO, Matty CAYMAX
  • Publication number: 20120178215
    Abstract: A nitride crystal or wafer with a removable surface layer comprises a high quality nitride base crystal, a release layer, and a high quality epitaxial layer. The release layer has a large optical absorption coefficient at wavelengths where the base crystal is substantially transparent and may be etched under conditions where the nitride base crystal and the high quality epitaxial layer are not. The high quality epitaxial layer may be removed from the nitride base crystal by laser liftoff or by chemical etching after deposition of at least one epitaxial device layer. The nitride crystal with a removable surface layer is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation.
    Type: Application
    Filed: March 20, 2012
    Publication date: July 12, 2012
    Applicant: Soraa, Inc.
    Inventor: Mark P. D'Evelyn
  • Patent number: 8216869
    Abstract: A manufacturing method of a group III nitride semiconductor includes the steps of: depositing a metal layer on an AlN template substrate or an AlN single crystal substrate formed by depositing an AlN single crystal layer with a thickness of not less than 0.1 ?m nor more than 10 ?m on a substrate made of either one of sapphire, SiC, and Si; forming a metal nitride layer having a plurality of substantially triangular-pyramid-shaped or triangular-trapezoid-shaped microcrystals by performing a heating nitridation process on the metal layer under a mixed gas atmosphere of ammonia; and depositing a group III nitride semiconductor layer on the metal nitride layer.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: July 10, 2012
    Assignee: Dowa Electronics Material Co., Ltd.
    Inventors: Takafumi Yao, Meoung-Whan Cho, Ryuichi Toba
  • Patent number: 8212288
    Abstract: A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which AlxGa1-xN single crystal layers (0.6?X?1.0) 21 containing carbon from 1×1018 atoms/cm3 to 1×1021 atoms/cm3 and AlyGa1-yN single crystal layers (0.1?y?0.5) 22 containing carbon from 1×1017 atoms/cm3 to 1×1021 atoms/cm3 are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×1017 atoms/cm3 or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the AlxGa1-xN single crystal layers 21 and that of the AlGa1-yN single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: July 3, 2012
    Assignee: Covalent Materials Corporation
    Inventors: Jun Komiyama, Kenichi Eriguchi, Hiroshi Oishi, Yoshihisa Abe, Akira Yoshida, Shunichi Suzuki
  • Patent number: 8202750
    Abstract: A method of manufacturing a semiconductor laser having an end face window structure, by growing over a substrate a nitride type Group III-V compound semiconductor layer including an active layer including a nitride type Group III-V compound semiconductor containing at least In and Ga, the method includes the steps of: forming a mask including an insulating film over the substrate, at least in the vicinity of the position of forming the end face window structure; and growing the nitride type Group III-V compound semiconductor layer including the active layer over a part, not covered with the mask, of the substrate.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: June 19, 2012
    Assignee: Sony Corporation
    Inventors: Masaru Kuramoto, Eiji Nakayama, Yoshitsugu Ohizumi
  • Patent number: 8193545
    Abstract: A nitride semiconductor light emitting device comprises a first nitride semiconductor layer, an active layer of a single or multiple quantum well structure formed on the first nitride semiconductor layer and including an InGaN well layer and a multilayer barrier layer, and a second nitride semiconductor layer formed on the active layer. A fabrication method of a nitride semiconductor light emitting device comprises: forming a buffer layer on a substrate, forming a GaN layer on the buffer layer, forming a first electrode layer on the GaN layer, forming an InxGa1?xN layer on the first electrode layer, forming on the first InxGa1?xN layer an active layer including an InGaN well layer and a multilayer barrier layer for emitting light, forming a p-GaN layer on the active layer, and forming a second electrode layer on the p-GaN layer.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: June 5, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee
  • Patent number: 8193016
    Abstract: A semiconductor laser device includes a substrate and a semiconductor layer formed on a surface of the substrate and having a waveguide extending in a first direction parallel to the surface, wherein the waveguide is formed on a region approaching a first side from a center of the semiconductor laser device in a second direction parallel to the surface and intersecting with the first direction, a first region separated from the waveguide on a side opposite to the first side of the waveguide and extending parallel to the first direction and a first recess portion separated from the waveguide on an extension of a facet of the waveguide, intersecting with the first region and extending in the second direction are formed on an upper surface of the semiconductor laser device, and a thickness of the semiconductor layer on the first region is smaller than a thickness of the semiconductor layer on a region other than the first region.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: June 5, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryoji Hiroyama, Daijiro Inoue, Yasuyuki Bessho, Masayuki Hata
  • Patent number: 8188573
    Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: May 29, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Yih-Der Guo, Suh-Fang Lin, Wei-Hung Kuo
  • Patent number: 8173469
    Abstract: Provided is a method for fabricating a light emitting device. The method for fabricating the light emitting device includes forming a buffer layer including a compound semiconductor in which a rare-earth element is doped on a substrate, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, which are successively stacked on the buffer layer, forming a first electrode layer on the light emitting structure, removing the substrate, and forming a second electrode layer under the light emitting structure.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: May 8, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Kyung Wook Park, Myung Hoon Jung
  • Publication number: 20120100698
    Abstract: The method is adapted for forming an aluminum nitride thin film having a high density and a high resistance to thermal shock by a chemical vapor deposition process and includes steps of mixing a gas containing aluminum atoms (Al) and a gas containing nitrogen atoms (N) with a gas containing oxygen atoms (O) and feeding the mixture to a member to be covered by an aluminum nitride thin film.
    Type: Application
    Filed: July 22, 2011
    Publication date: April 26, 2012
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Koji Kato, Shoji Kano, Waichi Yamamura
  • Patent number: 8163573
    Abstract: InyGa1-yN (0<y<1) layers whose principal surface is a non-polar plane or a semi-polar plane are formed by an MOCVD under different growth conditions. Then, the relationship between the growth temperature and the In supply mole fraction in a case where the pressure and the growth rate are constant is determined based on a growth condition employed for formation of InxGa1-xN (0<x<1) layers whose emission wavelengths are equal among the InyGa1-yN layers. Then, a saturation point is determined on a curve representing the relationship between the growth temperature and the In supply mole fraction, the saturation point being between a region where the growth temperature monotonically increases according to an increase of the In supply mole fraction and a region where the growth temperature saturates. Under a growth condition corresponding to this saturation point, an InxGa1-xN layer is grown.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: April 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Shunji Yoshida, Ryou Kato, Toshiya Yokogawa
  • Patent number: 8158497
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: April 17, 2012
    Assignee: The Regents of the University of California
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Patent number: 8158490
    Abstract: A method for producing a Group III nitride-based compound semiconductor device includes, before bonding a support substrate to an epitaxial layer formed on an epitaxial growth substrate, forming trenches in such a manner as to extend from the top surface of a stacked structure including the epitaxial layer to at least the interface between the epitaxial growth substrate and the bottom surface of the epitaxial layer. The trenches divide the epitaxial layer into extended device areas which encompass respective product device structures, and stress relaxation areas. A plurality of laser irradiations are performed for laser lift-off such that, after each laser irradiation, the expanded device areas and the stress relaxation areas are formed by a laser-irradiated area and a laser-unirradiated area, and a strip-shaped laser-unirradiated stress relaxation area is formed at a boundary between the laser-irradiated area and the laser-unirradiated area.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: April 17, 2012
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Umemura, Masahiro Ohashi
  • Patent number: 8154034
    Abstract: In a method for fabricating a vertical light emitting device, the separation or lift-off of the substrate from the light emitting diode structure formed thereon is facilitated by forming voids at the interface between the substrate and the light emitting diode structure where the separation or lift-off occurs. A substrate assembly contains a substrate and an epitaxial layer, and voids are formed at the interface between the substrate and the epitaxial layer in a controlled manner. A light emitting diode structure is then formed on the epitaxial layer, followed by attaching the light emitting diode structure to a superstrate, separating the substrate from the epitaxial layer, and forming a conductive layer and a contact pad in place of the substrate, so as to form a vertical light emitting device.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: April 10, 2012
    Assignee: Invenlux Limited
    Inventors: Jianping Zhang, Chunhui Yan
  • Patent number: 8148241
    Abstract: One embodiment of depositing a gallium nitride (GaN) film on a substrate comprises providing a source of indium (In) and gallium (Ga) and depositing a monolayer of indium (In) on the surface of the gallium nitride (GaN) film. The monolayer of indium (In) acts as a surfactant to modify the surface energy and facilitate the epitaxial growth of the film by suppressing three dimensional growth and enhancing or facilitating two dimensional growth. The deposition temperature is kept sufficiently high to enable the indium (In) to undergo absorption and desorption on the gallium nitride (GaN) film without being incorporated into the solid phase gallium nitride (GaN) film. The gallium (Ga) and indium (In) can be provided by a single source or separate sources.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: April 3, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Jie Su, Olga Kryliouk
  • Patent number: 8143646
    Abstract: A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev, Amy W. K. Liu
  • Patent number: 8133806
    Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: March 13, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Christiaan J. Werkhoven
  • Patent number: 8129208
    Abstract: This invention provides a self supporting substrate which consists of a n-type conductive aluminum nitride semiconductor crystal and is useful for manufacturing the vertical conductive type AlN semiconductor device. The n-type conductive aluminum nitride semiconductor crystal, by which the self supporting substrate is made up, contains Si atom at a concentration of 1×1018 to 5×1020 cm?3 is substantially free of halogen atoms and substantially does not absorb the light having the energy of not more than 5.9 eV. The self supporting substrate can be obtained by a method comprising the steps of forming an AlN crystal layer on a single crystal substrate such as a sapphire by the HVPE method, preheating the obtained substrate having the AlN crystal layer to a temperature of 1,200° C. or more, forming a second layer consisting of the n-type conductive aluminum nitride semiconductor crystal is formed on the AlN crystal layer in high rate by the HVPE method and separating the second layer from the obtained laminate.
    Type: Grant
    Filed: February 2, 2008
    Date of Patent: March 6, 2012
    Assignees: Tokuyama Corporation, Tokyo University of Agriculture and Technology
    Inventors: Akinori Koukitu, Yoshinao Kumagai, Toru Nagashima, Kazuya Takada, Hiroyuki Yanagi
  • Patent number: 8129260
    Abstract: A semiconductor substrate includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is formed of II-VI-group semiconductor material, III-V-group semiconductor material, or II-VI-group semiconductor material and III-V-group semiconductor material. At least one amorphous region and at least one crystalloid region are formed in the first semiconductor layer. The second semiconductor layer is formed on the first semiconductor layer and is crystal-grown from the at least one crystalloid region. A method of manufacturing a semiconductor substrate includes preparing a growth substrate; crystal-growing the first semiconductor layer on the growth substrate; forming the at least one amorphous region and the at least one crystalloid region in the first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer using the at least one amorphous region as a mask and the at least one crystalloid region as a seed.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: March 6, 2012
    Assignee: Samsung LED Co., Ltd.
    Inventors: Ho-sun Paek, Youn-joon Sung, Kyoung-ho Ha, Joong-kon Son, Sung-nam Lee