Abstract: An SOI substrate comprising a carrier substrate, a dielectric layer and a semiconductor layer. A continuous pn junction is realized in the semiconductor layer, which pn junction can be produced by applying differently doped partial layers on the SOI substrate. In this way, it is possible to use an SOI substrate for producing semiconductor components and, in particular, rear side diodes.

Abstract: To obtain a semiconductor substrate having a high-quality Ge-based epitaxial film in a large area, a SiGe mixed crystal buffer layer and a Ge epitaxial film is grown on a main surface of a Si substrate 10. Although high-density defects are introduced in the Ge epitaxial film 11 from an interface between the Ge epitaxial film 11 and the Si substrate 10, the Ge epitaxial film is subjected to a heat treatment at a temperature of not less than 700° C. and not more than 900° C. to cause threading dislocations 12 to change into dislocation-loop defects 12? near the interface between the Ge epitaxial film 11 and the Si substrate.

Abstract: By performing at least one additional wet chemical etch process in the edge region and in particular on the bevel of a substrate during the formation of a metallization layer, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. Moreover, an additional wet chemical etch process may be performed after the deposition of the metal to remove any unwanted metal and barrier material from the edge region and the bevel. Accordingly, defect issues and contamination of substrates and process tools may be efficiently reduced.

Abstract: Methods and apparatus provide for: a semiconductor wafer; at least one porous layer in the semiconductor wafer; an epitaxial semiconductor layer directly or indirectly on the porous layer; and a glass substrate bonded to the epitaxial semiconductor layer via electrolysis.

Abstract: A photosensitive device having at least an insulator layer including a plurality of photoreceiving regions disposed on a substrate. A plurality of conductive patterns is disposed on the insulator layer without covering the photoreceiving regions. A flattened dielectric layer is disposed on the conductive patterns and the insulator layer, wherein a surface of the dielectric layer is higher than a surface of the conductive patterns in a range between 2000 ? to 4000 ?.

Abstract: Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.

Abstract: A method for producing a semiconductor structure that includes at least one useful layer on a substrate.

Abstract: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

Abstract: A semiconductor device is provided. The semiconductor device includes an element; a mounting board; and a single film made of a conductive material directly coupling the element with the mounting board.

Abstract: A method of manufacturing a coaxial trace (100) within a surrounding material (190) includes: providing a first substrate (191, 410) and a second substrate (192, 1010) composed of the surrounding material; forming a first portion (101, 601) of the coaxial trace in the first substrate; forming a second portion (102, 1001) of the coaxial trace in the second substrate; aligning the first portion of the coaxial trace with the second portion of the coaxial trace; and bonding the first portion of the coaxial trace to the second portion of the coaxial trace.

Abstract: A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of the device in the second layer, forming temporary anchors in the first layer, and bonding the first wafer to a second wafer, with the second layer facing the second wafer. After bonding the first wafer and the second wafer together, second supporting parts and second operative parts of said device are formed in the first layer. The temporary anchors are removed from the first layer to free the operative parts formed therein.

Abstract: A partially completed multi-layered substrate, e.g., silicon on silicon. The substrate has a thickness of material from a first substrate. The thickness of material comprises a first face region. The substrate has a second substrate having a second face region. Preferably, the first face region of the thickness of material is joined to the second face region of the second substrate. The substrate has an interface region formed between the first face region of the thickness of material and the second face region of the second substrate. A plurality of particles are implanted within a portion of the thickness of the material and a portion of the interface region to electrically couple a portion of the thickness of material to a portion of the second substrate.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A method for producing Microelectromechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer includes providing an SOI wafer, performing a mesa etch to at least partially define the MEMS device, bonding the SOI wafer to an interposer by direct boding, removing the handle layer of the SOI wafer, removing the oxide layer of the SOI wafer, and further etching the device layer of the SOI wafer to define the MEMS device. A structure manufactured according to the above described processes includes an interposer comprising an SOI wafer and a MEMS device mounted on the interposer. The MEMS device comprises posts extending from a silicon plate. The MEMS device is directly mounted to the interposer by bonding the posts of the MEMS device to the device layer of the interposer.

Abstract: A method of making a circuitized substrate and an electrical assembly utilizing same in which the substrate is comprised of at least two sub-composites in which the dielectric material of at least one of these sub-composites is heated during bonding (e.g., lamination) to the other sufficiently to cause the dielectric material to flow into and substantially fill openings in a conductive layer for the bonded structure. Conductive thru-holes are formed within the bonded structure to couple selected ones of the structure's conductive layers. Formation of an electrical assembly is possible by positioning one or more electrical components (e.g., semiconductor chips or chip carriers) on the final structure and electrically coupling these to the structure's external circuitry.

Abstract: Embodiments of the present invention provide a method for reclaiming and reusing a wafer. In one embodiment, a method for reclaiming a wafer comprises providing a used, nonproductive wafer having a semiconductor substrate and a polysilicon layer formed on the semiconductor substrate; oxidizing a first part of the polysilicon layer to form a first oxide layer; removing the first oxide layer; and oxidizing a second part of the polysilicon layer to form a second oxide layer on the used wafer which is to be used as a reclaimed wafer. The nonproductive wafer is used to improve the quality of a deposition process of the polysilicon layer on one or more productive wafers.

Abstract: The object of the invention is to provide a method for manufacturing an SOI layer which is devoid of damages, has a reduced variation in thickness, and is uniform in thickness.

Abstract: Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.

Abstract: The object of the invention is to provide a method for manufacturing an SOI layer which is devoid of damages, has a reduced variation in thickness, and is uniform in thickness.

Abstract: A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded Si1-xGex buffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop Si1-yGey layer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop S1-yGey layer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed.

Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

Abstract: A Method for manufacturing an optical disc substrate comprises a first substrate with at least one structured surface, on which an anti-adhesive layer, preferably carbon, is deposited and first layer on top of said anti-adhesive layer. On a second substrate with a structured surface also a layer is deposited. Both substrates are bonded together with the layers facing each other. The separation now easily can take place afterwards alongside the adhesive layer. This way the first layer from the first substrate is being transferred to the second substrate.

Abstract: A process for bonding oxide-free silicon substrate pairs and other substrates at low temperature. This process involves modifying the surface of the silicon wafers to create defect regions, for example by plasma-treating the surface to be bonded with a or boron-containing plasmas such as a B2H6 plasma. The surface defect regions may also be created by ion implantation, preferably using boron. The surfaces may also be amorphized. The treated surfaces are placed together, thus forming an attached pair at room temperature in ambient air. The bonding energy reaches approximately 400 mJ/m2 at room temperature, 900 mJ/m2 at 150° C., and 1800 mJ/m2 at 250° C. The bulk silicon fracture energy of 2500 mJ/m2 was achieved after annealing at 350-400° C. The release of hydrogen from B—H complexes and the subsequent absorption of the hydrogen by the plasma induced modified layers on the bonding surfaces at low temperature is most likely responsible for the enhanced bonding energy.

Abstract: Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed herein. A method of manufacturing a substrate in accordance with one embodiment of the invention includes forming a conductive trace on a first side of a sheet of non-conductive material, and forming a via through the non-conductive material from a second side of the sheet to the conductive trace. The method further includes removing a section of the non-conductive material to form an edge of the non-conductive material extending across at least a portion of the via. In one embodiment, forming the edge across the via exposes at least a portion of the second conductive trace for subsequent attachment to a terminal on a microelectronic die.

Abstract: An alloying method includes the steps of forming a metal layer on a semiconductor having been transferred to a material having a low thermal conductivity, and alloying an interface between the semiconductor and the metal layer by irradiating the interface with a laser beam having a wavelength absorbable in at least one of the semiconductor and the metal layer. The irradiation energy of the laser beam is set in a range of 20 to 100 mJ/cm2. The material having a low thermal conductivity is a resin or amorphous silicon. According to the alloying method using laser irradiation, since the entire semiconductor is not heated and only a necessary portion is locally heated, the necessary portion can be readily alloyed to be converted into an ohmic contact without exerting adverse effect on characteristics of the semiconductor device.

Abstract: It is an object of the invention to provide a peeling method which does not damage a peeling layer, and to perform peeling not only a peeling layer having a small-size area but also an entire peeling layer having a large-size area with a preferable yield. In the invention, after pasting a fixing substrate, a part of a glass substrate is removed by scribing or performing laser irradiation on the glass substrate which leads to providing a trigger. Then, peeling is performed with a preferable yield by performing peeling from the removed part. In addition, a crack is prevented by covering the entire face except for a connection portion of a terminal electrode (including a periphery region of the terminal electrode) with a resin.

Abstract: Provided herein is a substrate processing system, which comprises a cassette load station; a load lock chamber; a centrally located transfer chamber; and one or more process chambers located about the periphery of the transfer chamber. The load lock chamber comprises double dual slot load locks constructed at same location. Such system may be used for processing substrates for semiconductor manufacturing.

Abstract: A technique is described in which a layer to be transferred is easily peeled and transferred to a transferred body that is pliable or flexible. Also, a method of fabricating a semiconductor device using these peeling and transfer techniques, and electronic equipment fabricated with the semiconductor device is described. A transfer method in which a layer to be transferred formed on a substrate is transferred to a transfer body that is pliable or flexible includes the first step of forming a layer to be transferred on a substrate; the second step of bonding the layer to be transferred formed on the substrate to a transfer body that is pliable or flexible fixed on a fixture; and the third step of peeling the layer to be transferred from the substrate and transferring the layer to be transferred to the transfer body.

Abstract: Method of making an integrated passive, such as a high quality decoupling capacitor, includes providing a first temporary support, a silicon capacitor wafer, and providing an oxide layer and a conductive layer on it. Then, a second temporary support, such as a handle wafer, may be attached to the capacitor wafer (i.e., to the oxide layer on it) by an adhesive bond. The capacitor wafer may then be destructively removed. A second conductive layer is then provided on an exposed backside of the oxide layer. The addition of a second electrode on the second conductive layer yields the desired high quality capacitor. Further processing steps, such as solder bumping, may be carried out while the capacitor wafer is still attached to the handle wafer. When the desired processing steps are complete, the handle wafer is removed, and the relatively thin high quality integrated capacitor wafer results.

Abstract: A MEMS article is made by forming a MEMS device on a first substrate, providing a second substrate, depositing a layer of etchable dielectric material, forming at least one lateral post-bond release-etch port by a damascene process using a sacrificial material, and bonding the two substrates together.

Abstract: A method for manufacturing a semiconductor chip package may include screen printing an adhesive on a substrate using a screen printing mask. The adhesive may be heated during a first curing process. A semiconductor chip may be attached to the adhesive on the substrate. The adhesive may be heated during a second curing process. The physical property of the adhesive may be transformed before and after a screen printing process to improve the operational performance and/or quality of the adhesive.

Abstract: The present invention provides a manufacturing method for an SOI wafer with a high productivity in which generation of a void is suppressed in manufacturing the SOI wafer. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers each with no line defect on a surface thereof are used. In a manufacturing method for an SOI wafer of the present invention in which two starting wafers are prepared, an insulating layer is formed on at least one of the two starting wafers and the one wafer is adhered to the other wafer without using an adhesive agent, the starting wafers are subjected to a high temperature heat treatment in advance.

Abstract: Provided is a method of manufacturing a silicon on insulator (SOI) substrate, which includes the steps of (a) forming a buried oxidation layer to a predetermined depth of a first wafer and forming an oxidation layer on a surface of the first wafer; (b) bonding a second wafer onto the first wafer; (c) selectively removing the oxidation layer so as to expose a bottom surface of the first wafer; (d) selectively removing the exposed bottom silicon layer of the first wafer using the buried oxidation layer as an etch stop layer; and (e) removing the buried oxidation layer to expose a top surface of the first wafer, and thinning the exposed top surface of the first wafer to a predetermined thickness, so that a process can be relatively simple and can be readily carried out, thereby manufacturing an SOI substrate having a uniform silicon thickness of high quality and an ultra thin characteristic.

Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface, implanting atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer, and bonding the free surface of the second layer to a host wafer. The method also includes supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer, conducting a bond strengthening step on the structure after detachment at a temperature of less than about 800° C. to improve the strength of the bond between the second layer and the host wafer, and selectively etching the first layer portion to remove it from the structure and to expose a surface of the second layer.

Abstract: The invention encompasses a method of forming a semiconductor-on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon, fluorine, bromine, chlorine, iodine and germanium.

Abstract: The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

Abstract: The present invention discloses a semiconductor device having a pad structure for preventing a stress of a silicon nitride film. The semiconductor device includes a semiconductor substrate, a lower structure formed on the semiconductor substrate, a first insulation film formed on the lower structure, a first metal layer coupled to the lower structure through a first metal contact in the first insulation film, a second metal layer formed on the first metal layer, and a plurality of dummy gates having a concentric square structure formed at the lower portion of the pad region on the second metal layer.

Abstract: A method for forming dislocation-free strained silicon thin film includes the step of providing two curved silicon substrates. One substrate is curved by the presence of silicon dioxide on a back surface. The other substrate is curved by the presence of a silicon nitride layer. One of the substrates is subject to hydrogen implantation and the two substrates are bonded to one another in an annealing process. The two substrates are separated, thereby leaving a layer of strained silicon on a front side of one of the substrates. A back side layer of silicon dioxide or silicon nitride is then removed to restore the substrate to a substantially planar state. The method may be employed to form dislocation-free strained silicon thin films. The films may be under tensile or compressive strain.

Abstract: A technique is described in which a layer to be transferred is easily peeled and transferred to a transferred body that is pliable or flexible. Also, a method of fabricating a semiconductor device using these peeling and transfer techniques, and electronic equipment fabricated with the semiconductor device is described. A transfer method in which a layer to be transferred formed on a substrate is transferred to a transfer body that is pliable or flexible includes the first step of forming a layer to be transferred on a substrate; the second step of bonding the layer to be transferred formed on the substrate to a transfer body that is pliable or flexible fixed on a fixture; and the third step of peeling the layer to be transferred from the substrate and transferring the layer to be transferred to the transfer body.

Abstract: A method for forming dislocation-free strained silicon thin film includes the step of providing two curved silicon substrates. One substrate is curved by the presence of silicon dioxide on a back surface. The other substrate is curved by the presence of a silicon nitride layer. One of the substrates is subject to hydrogen implantation and the two substrates are bonded to one another in an annealing process. The two substrates are separated, thereby leaving a layer of strained silicon on a front side of one of the substrates. A back side layer of silicon dioxide or silicon nitride is then removed to restore the substrate to a substantially planar state. The method may be employed to form dislocation-free strained silicon thin films. The films may be under tensile or compressive strain.

Abstract: A method for forming a dopant in a substrate, by accumulating at least one dopant species in an asher chamber and forming the accumulated dopant species on an exposed portion of the substrate. A target concentration for the plasma chamber dopant species is determined by test or measurement. The asher is used to form the dopant species on the substrate, and the dopant species is driven into the substrate. A threshold voltage is measured on the substrate to verify or confirm that a proper dopant level has been achieved.

Abstract: Methods for preparing a semiconductor assembly are disclosed. In an implementation, the technique includes providing a support substrate and a bonding surface thereon, providing a donor substrate having a weakened zone that defines a useful layer and a bonding surface on the useful layer, and providing an interface layer of a predetermined material on the bonding surface of either the support substrate or the useful layer to provide a bonding surface thereon. The method also includes molecularly bonding the bonding surface of the interface layer to the bonding surface of the other of the support substrate or the useful layer to form a separable bonding interface therebetween, and to thus form the semiconductor assembly, and heat treating the semiconductor assembly to a temperature of at least 1000 to 1100° C.

Abstract: A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between the semiconductor structure and the layer of gate material and closer to the first side of the second wafer than the semiconductor structure. The method further includes bonding the first side of the second wafer to the first wafer and cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a second storage layer over the layer of the semiconductor structure and forming a top gate over the second storage layer.

Abstract: External energy is fed to N-[3-{3,5-bis{3,5-bis[3,5-bis(4-mercaptobenzylthio)benzylthio]benzylthio}benzyloxy}-propionyl-4-nitro-1-naphthylamine (18a) being a molecule capable of photosensitization as an intermediate excitation medium, fixed on support (12) of a metal, so as to photosensitized molecule of excited triplet state (18b), thereby inducing an excited triplet energy transfer from this photosensitized molecule to first molecule (28a) having a residue capable of bonding. The first molecule (28b) having thus been excited by the excited triplet energy transfer is bonded with second molecule (30) having a residue capable of bonding which is a bonding object to be bonded with the first molecule.

Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.

Abstract: It is an object of the invention to provide a peeling method which does not damage a peeling layer, and to perform peeling not only a peeling layer having a small-size area but also an entire peeling layer having a large-size area with a preferable yield. In the invention, after pasting a fixing substrate, a part of a glass substrate is removed by scribing or performing laser irradiation on the glass substrate which leads to providing a trigger. Then, peeling is performed with a preferable yield by performing peeling from the removed part. In addition, a crack is prevented by covering the entire face except for a connection portion of a terminal electrode (including a periphery region of the terminal electrode) with a resin.

Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.