Bonding Of Semiconductor Wafer To Insulating Substrate Or To Semic Onducting Substrate Using An Intermediate Insulating Layer (epo) Patents (Class 257/E21.122)
  • Publication number: 20070128825
    Abstract: A method for bonding of substrates has a steps of irradiating surfaces of the substrates respectively in a vacuum with both an inert gas beam and a metal beam thereby forming island shaped thin metal films on the surfaces of the substrates, and surface-activated bonding of the substrates through the island shaped thin metal films by contacting the surfaces of the substrates each other.
    Type: Application
    Filed: December 2, 2005
    Publication date: June 7, 2007
    Applicants: Tadatomo Suga, Ayumi Industry Co., Ltd.
    Inventors: Tadatomo Suga, Mohammad Howlader, Tomoyuki Abe
  • Patent number: 7214554
    Abstract: A method for making an OLED device includes providing a substrate having one or more test regions and one or more device regions, moving the substrate into a least one deposition chamber for deposition of at least one organic layer, and depositing the at least one organic layer through a shadowmask selectively onto the at least one device region and at least one test region on the substrate. The method also includes measuring a property of the at least one organic layer in the at least one test region, and adjusting the deposition process in accordance with the measured property.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: May 8, 2007
    Assignee: Eastman Kodak Company
    Inventors: Dustin L. Winters, Michele L. Ricks, Nancy J. Armstrong, Robert S. Cupello
  • Patent number: 7205210
    Abstract: A first semiconductor structure has a silicon substrate, a first silicon germanium layer grown on the silicon, a second silicon germanium layer on the first silicon germanium layer, and a strained silicon layer on the second silicon germanium layer. A second semiconductor structure has a silicon substrate and an insulating top layer. The silicon layer of the first semiconductor structure is bonded to the insulator layer to form a third semiconductor structure. The second silicon germanium layer is cut to separate most of the first semiconductor structure from the third semiconductor structure. The silicon germanium layer is removed to expose the strained silicon layer where transistors are subsequently formed, which is then the only layer remaining from the first semiconductor structure. The transistors are oriented along the <100> direction and at a 45 degree angle to the <100> direction of the base silicon layer of the second silicon.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: April 17, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alexander L. Barr, Dejan Jovanovic, Bich-Yen Nguyen, Mariam G. Sadaka, Voon-Yew Thean, Ted R. White
  • Patent number: 7192842
    Abstract: A first wafer is provided, and a photosensitive masking-and-bonding pattern is formed on the surface of the first wafer. Then, an etching process using the photosensitive masking-and-bonding pattern as a hard mask is performed to form a wafer pattern on the surface of the first wafer. Finally, the first wafer is bonded to a second wafer with the photosensitive masking-and-bonding pattern.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: March 20, 2007
    Assignee: Touch Micro-Systems Technology Inc.
    Inventors: Shih-Feng Shao, Hsin-Ya Peng, Chen-Hsiung Yang
  • Patent number: 7186628
    Abstract: When an SOI wafer is produced by using a bond wafer made of silicon single crystal to form an SOI layer and a base wafer made of silicon single crystal to be a support substrate, one silicon wafer selected from a group consisting of an epitaxial wafer, an FZ wafer, a nitrogen doped wafer, a hydrogen annealed wafer, an intrinsic gettering wafer, a nitrogen doped and annealed wafer, and an entire N-region wafer is used as the bond wafer. Thereby, even where a thin insulator film or a thin SOI layer is formed in the SOI wafer, COPs are hardly detected in inspection of the SOI layer after the SOI wafer was completed, and a high quality SOI wafer is provided.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: March 6, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Masatake Nakano
  • Patent number: 7183656
    Abstract: A method for connecting a microelectronic device to a wirebond comprises providing a substrate having a microelectronic circuit therein and forming a wiring layer over the substrate. The wiring layer includes a bilayer wiring structure comprising upper and lower electrically conductive layers separated by a protective electrically conductive layer. The lower layer of the bilayer structure is at the level of the wiring layer and the upper layer of the bilayer structure extends above the level of the wiring layer. The bilayer wiring structure is formed by depositing the upper and lower electrically conductive layers separated by a protective electrically conductive layer over the substrate, etching the upper electrically conductive layer and a portion of the protective electrically conductive layer, and thereafter separately etching the lower electrically conductive layer to form the wiring layer over the substrate. The method also includes connecting a wirebond to the upper layer of the bilayer structure.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: February 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Stephen E. Luce, Thomas L. McDevitt, Anthony K. Stamper
  • Patent number: 7176107
    Abstract: A hybrid substrate, i.e., a substrate fabricated from different materials, and method for fabricating the same are presented. The hybrid substrate is configured for fabricating more than two different devices thereon, has a high thermal conductivity, and is configured for patterning interconnects thereon for interconnecting the different devices fabricated on the hybrid substrate.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: February 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Li-Kong Wang
  • Publication number: 20070032042
    Abstract: A peeling method is provided which does not cause damage to a layer to be peeled, and the method enables not only peeling of the layer to be peeled having a small area but also peeling of the entire layer to be peeled having a large area at a high yield. Further, there are provided a semiconductor device, which is reduced in weight through adhesion of the layer to be peeled to various base materials, and a manufacturing method thereof. In particular, there are provided a semiconductor device, which is reduced in weight through adhesion of various elements, typically a TFT, to a flexible film, and a manufacturing method thereof. A metal layer or nitride layer is provided on a substrate; an oxide layer is provided contacting with the metal layer or nitride layer; then, a base insulating film and a layer to be peeled containing hydrogen are formed; and heat treatment for diffusing hydrogen is performed thereto at 410° C. or more.
    Type: Application
    Filed: October 4, 2006
    Publication date: February 8, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno, Takuya Tsurume, Hideaki Kuwabara
  • Patent number: 7170098
    Abstract: Processes are described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. The die has a diamond layer which primarily serves to spread heat from hot spots of an integrated circuit in the die.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: January 30, 2007
    Assignee: Intel Corporation
    Inventors: Gregory M. Chrysler, Abhay A. Watwe, Sairam Agraharam, Kramadhati V. Ravi, Michael C. Garner
  • Publication number: 20070020873
    Abstract: The invention provides a method of manufacturing a composite wafer structure. In particular, the method, according to the invention, is based on the fracture mechanics theory to actively control fracture induced during the manufacture of the composite wafer structure and to further protect from undesired edge damage. Thereby, the method, according to the invention, can enhance the yield rate of industrial mass production regarding the composite wafer structure.
    Type: Application
    Filed: October 7, 2005
    Publication date: January 25, 2007
    Inventors: Jer-Liang Yeh, Jing-Yi Huang, Wen-Ching Hsu, Ya-Lan Ho, Sung-Lin Hsu, Jung-Tsung Wang
  • Patent number: 7160791
    Abstract: A method for forming a standoff structure for packaging devices, e.g., optical devices, integrated circuit devices. The method includes providing a substrate, e.g., silicon wafer. The substrate includes a first surface region, a second surface region, and a thickness defined between the first surface region and the second surface region. The method includes protecting selected portions of the first surface region using a masking layer while leaving a plurality of unprotected regions. Preferably, each of the unprotected regions is to be associated with an opening through the thickness of the substrate. The method causes removal of the plurality of unprotected regions to form a plurality of openings through the thickness of the substrate to provide a resulting patterned substrate. Each of the openings is bordered by a portion of the selected portions of the first surface region. Preferably, etching techniques, such as wet etch or dry etching, can be used, depending upon the embodiment.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: January 9, 2007
    Assignee: Miradia Inc.
    Inventor: Xiao Charles Yang
  • Publication number: 20060286770
    Abstract: A method for producing a semiconductor structure that includes at least one useful layer on a substrate.
    Type: Application
    Filed: August 24, 2006
    Publication date: December 21, 2006
    Applicants: S.O.I.Tec Silicon on Insulator Technologies S.A., Commissariat à l'Energie Atomique (CEA)
    Inventors: Bruno Ghyselen, Cecile Aulnette, Benoit Bataillou, Carlos Mazure, Hubert Moriceau
  • Patent number: 7151052
    Abstract: Described are methods and structures for mitigating the effects of mechanical stresses placed on the layers of semiconductor devices, and specifically disclosed are methods and structures for mitigating the diminished chemical bonds between etch-stop layers and other semiconductor device layers. The disclosed methods and structures use different structures and/or processes for some of the etch-stop layers in a device.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: December 19, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Hsiang Yao, Kuan-Shou Chi, Chin-Chiu Hsia, Mong-Song Liang
  • Patent number: 7148121
    Abstract: An SOI architecture is provided that comprises an inner substrate 10 which has a buried conductor layer 12 formed on an outer surface thereof. A bonding layer 14 is used to provide a cohesive bond with a buried insulator layer 18. The semiconductor device layer 20 is formed on the outer surface of buried insulator layer 18. An inductive well 22 can be formed to provide a platform for the formation of inductive devices 34 within an inductive region 26.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: December 12, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 7145212
    Abstract: A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: December 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Lijuan Huang, Fenton R. McFeely, Paul M. Solomon, Hon-Sum Philip Wong
  • Patent number: 7122445
    Abstract: A peeling method is provided which does not cause damage to a layer to be peeled, and the method enables not only peeling of the layer to be peeled having a small area but also peeling of the entire layer to be peeled having a large area at a high yield. Further, there are provided a semiconductor device, which is reduced in weight through adhesion of the layer to be peeled to various base materials, and a manufacturing method thereof. In particular, there are provided a semiconductor device, which is reduced in weight through adhesion of various elements, typically a TFT, to a flexible film, and a manufacturing method thereof. A metal layer or nitride layer is provided on a substrate; an oxide layer is provided contacting with the metal layer or nitride layer; then, a base insulating film and a layer to be peeled containing hydrogen are formed; and heat treatment for diffusing hydrogen is performed thereto at 410° C. or more.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: October 17, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno, Takuya Tsurume, Hideaki Kuwabara
  • Patent number: 7122452
    Abstract: A method of producing a semiconductor device on a silicon on insulator (SOI) substrate is disclosed. In one aspect, the method comprises providing a device with a monocrystalline semiconductor layer on an insulating layer; providing a mask on the semiconductor layer to provide first shielded portions and first unshielded portions, amorphizing the first unshielded portions to yield first amorphized portions of the monocrystalline semiconductor layer, implanting a first dopant in the first amorphized portions, applying a first solid phase epitaxial regrowth action to the semiconductor device while using the first shielded portions as monocrystalline seeds.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: October 17, 2006
    Assignees: Interuniversitair Microelektronica Centrum (IMEC) vzw, Koninklijke Philips Electronics
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 7115481
    Abstract: A method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate. The method includes providing an initial structure that includes a useful layer having a front face on a support substrate. Atomic species are implanted into the useful layer to a controlled mean implantation depth to form a zone of weakness within the useful layer that defines first and second useful layers. Next, a stiffening substrate is bonded to the front face of the initial structure. The first useful layer is then detached from the second useful layer along the zone of weakness to obtain a pair of semiconductor structures with a first structure including the stiffening substrate and the first useful layer and a second structure including the support substrate and the second useful layer. The structures obtained can be used in the fields of electronics, optoelectronics or optics.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: October 3, 2006
    Assignees: S.O.I.Tec Silicon on Insulator Technologies S.A., Commissariat à l'Energie Atomique (CEA)
    Inventors: Bruno Ghyselen, Cécile Aulnette, Benoit Bataillou, Carlos Mazure, Hubert Moriceau
  • Patent number: 7094664
    Abstract: Multilayer films (2 to 7 ) containing a light absorption layer (4) are formed on a GaAs substrate. After laminating the GaAs substrate (1) and a glass substrate (8) so that an uppermost surface film (7) of the multilayer film and the glass substrate (8) may come into contact with each other, by pressurizing between the GaAs substrate (1) and the glass substrate (8) and heating them together, both substrates (1) and (8) are fusion-bonded. Next, the GaAs substrate (1) and the buffer layer (2) are first removed, and then the etch stop layer (3) is removed. Then, while coming into contact with the light absorption layer (4), comb-type Schottky electrodes (10) and (11), which are mutually apart, are formed.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: August 22, 2006
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Minoru Niigaki, Kazutoshi Nakajima
  • Patent number: 7078262
    Abstract: A wafer formed thin through a back grinding process is placed on a support table included in an alignment stage. When a faulty suction is caused by a warp of the wafer, a surface of wafer is pressed by a pressing plate to be corrected and held by suction. The wafer held by suction is transported, along with the alignment stage, to a mount frame preparing unit at the next step. The wafer is received while being held by suction by a chuck table contacting the surface of wafer.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: July 18, 2006
    Assignee: Nitto Denko Corporation
    Inventors: Masayuki Yamamoto, Takao Matsushita
  • Patent number: 7071077
    Abstract: A method for preparing a bonding surface of a semiconductor layer of a wafer is described. The method includes treating the bonding surface to oxidize contaminants, and then cleaning the bonding surface to remove essentially all remaining contaminants. Ozone is then used to oxidize the bonding surface to improve the hydrophilic properties of the bonding surface. In an implementation, two wafers are prepared and then bonded together to form a structure.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: July 4, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Christophe Maleville, Corinne Maunand Tussot
  • Patent number: 6995691
    Abstract: Environmental sensors and other bodies, together with associated lead wires, are mounted to a oxidizable substrate for high temperature applications by means of a reacted borosilicate mixture (RBM) that secures the body relative to the substrate via of an oxide interface formed between the RBM and substrate during a high temperature reaction process. An oxide interface is also formed with oxidizable bodies to provide further mounting strength. The RBM is a B2O3—SiO2 mixture, with the B2O3 portion a function of the reaction temperature and desired bonding strength and viscosity.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: February 7, 2006
    Assignee: Heetronix
    Inventor: James D. Parsons
  • Patent number: 6936497
    Abstract: A process is described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. A thin diamond layer is formed on a sacrificial wafer, and an integrated circuit is then formed on the thin diamond layer. The sacrificial wafer is then removed to expose the thin diamond layer. The resulting combination wafer is subsequently diced into individual dies. Each die has an exposed diamond layer forming the majority of the die and serving to conduct heat from the integrated circuit to a backside of the die, from where the heat can convect or be conducted away from the die.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: August 30, 2005
    Assignee: Intel Corporation
    Inventors: Kramadhati V. Ravi, Gregory M. Chrysler
  • Patent number: 6747298
    Abstract: Bonding of flip-chip mounted light emitting devices having an irregular configuration is provided. Light emitting diodes having a shaped substrate are bonded to a submount by applying forces to the substrate an a manner such that shear forces within the substrate do not exceed a failure threshold of the substrate. Bonding a light emitting diode to a submount may be provided by applying force to a surface of a substrate of the light emitting diode that is oblique to a direction of motion of the light emitting diode to thermosonically bond the light emitting diode to the submount. Collets for use in bonding shaped substrates to a submount and systems for bonding shaped substrates to a submount are also provided.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: June 8, 2004
    Assignee: Cree, Inc.
    Inventors: David B. Slater, Jr., Jayesh Bharathan, John Edmond, Mark Raffetto, Anwar Mohammed, Peter S. Andrews, Gerald H. Negley