Abstract: A thickness of silicon oxide film of a wafer for active layer is controlled to be thinner than that of buried silicon oxide film. Consequently, uniformity in film thickness of the active layer of a bonded wafer is improved even if a variation in the in-plane thickness of the silicon oxide film is large at a time of ion implantation. Furthermore, since the silicon oxide film is rather thinner and thereby the ion implantation depth is relatively deeper, damages to the active layer and the buried silicon oxide film caused by the ion implantation can be reduced.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: A method for minimizing or avoiding contamination of a receiving handle wafer during transfer of a thin layer from a donor wafer. This method includes one step of providing a donor wafer and a receiving handle wafer, each having a first surface prepared for bonding and a second surface, with the donor layer including a zone of weakness that defines a thin layer of donor wafer material to be transferred to the receiving handle wafer. Next, at least one of the first surfaces is treated to provide increased bonding energy when the first surfaces are bonded together; the surfaces are then bonded together to form an intermediate multilayer structure; and the thin layer is transferred to the receiving handle wafer to form a final multilayer structure by detachment at the zone of weakness and removal of remaining material of the donor wafer.

Abstract: A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and lower surfaces, and providing the second surface of the wafer or the upper surface of the supporting substrate with void features in an amount sufficient to enable a connecting bond therebetween to form a construct wherein the bond is formed at an interface between the wafer and the substrate and is suitable to maintain the wafer and supporting substrate in association while forming or applying electronic devices to the first surface of the wafer, but which connecting bond is severable at the interface due to the void features to separate the substrate from the wafer so that the substrate can be reused.

Abstract: The invention relates to a recyclable donor wafer that includes a substrate and a formed layer thereon, wherein the formed layer has a thickness sufficient to provide (a) at least two useful layers for detachment therefrom and (b) additional material that can be removed to planarize exposed surfaces of the useful layers prior to detachment from the donor wafer.

Abstract: The invention relates to a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).

Abstract: A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate. The bonding regions are preferably formed by a thick layer of a material chosen from among aluminum, copper and nickel, covered by a thin layer of a material chosen from between palladium and platinum. Spacing regions ensure exact spacing between the two wafers.

Abstract: The present invention relates to a flexible single-crystal film and a method of manufacturing the same from a single-crystal wafer. That is, the present invention can manufacture a silicon-on-insulator (SOI) wafer comprising a base wafer, one or more buried insulator layers, and a single-crystal layer into a flexible single-crystal film with a desired thickness by employing various wafer thinning techniques. The method for manufacturing a flexible film comprises the steps of (i) providing a SOI wafer comprising a base wafer, one or more buried insulator layers on the base wafer, and a single-crystal layer on said one or more buried insulator layers, (ii) forming one or more protective insulator layers on said single-crystal layer, (iii) removing said base wafer, and (iv) removing one or more of the insulator layers.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.

Abstract: A spatial light modulator is fabricated by bonding a capping layer over a wafer bearing active reflecting surfaces utilizing a low temperature bonding agent capable of providing a hermetic seal, such as a glass frit. The low temperature bonding agent may be B-stage cured after application to the capping layer, prior to any exposure to the substrate bearing the reflecting surfaces. In accordance with one embodiment of the present invention, the capping layer may comprise a glass wafer pre-bonded with an interposer spacer layer to provide sufficient stand-off between the capping layer and the underlying reflecting structures. In accordance with an alternative embodiment of the present invention, the capping layer may comprise a glass wafer alone, and the bonding agent may include additional materials such as beads or balls to provide the necessary stand-off between the capping layer and the underlying reflective structures.

Abstract: A method of manufacturing an integrated circuit including a first isolated chip electrically and mechanically connected via wafer bonding to a second isolated chip, wherein the active faces of the chips face one another, includes: forming metallic contact zones on active faces of first and second wafers, positioning and fixing the wafers one above another at a predetermined distance such that the active faces of the wafers face one another and the contact zones are aligned, placing the fixed wafers in a bath for electroless metal deposition onto the contact zones; and removing the fixed wafers in the event that the metal layers growing on the aligned contact zones of the first and second wafers have grown together.

Abstract: An adhesive bonding sheet having an optically transmitting supporting substrate and an adhesive bonding layer, and being used in both a dicing step and a semiconductor element adhesion step, wherein the adhesive bonding layer comprises: a polymer component (A) having a weight average molecular weight of 100,000 or more including functional groups; an epoxy resin (B); a phenolic epoxy resin curing agent (C); a photoreactive monomer (D), wherein the Tg of the cured material obtained by ultraviolet light irradiation is 250° C. or more; and a photoinitiator (E) which generates a base and a radical by irradiation with ultraviolet light of wavelength 200-450 nm.

Abstract: A method of fabricating a hybrid substrate by direct bonding of donor and receiver substrates where each substrate has a respective front face and surface, with the front face of the receiver substrate having a semiconductor material near the surface, and the donor substrate including a zone of weakness that defines a layer to be transferred. The method includes preparing the substrate surfaces by exposing the surface of the receiver substrate to a temperature from about 900° C. to about 1200° C. in an inert atmosphere for at least 30 sec; directly bonding together the front faces of the prepared substrates to form a composite substrate; heat treating the composite substrate to increase bonding strength between the front surfaces of the donor and receiver substrates; and transferring the layer from the donor substrate by detaching the remainder of the donor substrate at the zone of weakness.

Abstract: A method positions a first wafer with respect to a second wafer such that key studs on the first wafer are fit (positioned) within lock openings in the second wafer. The key studs contact conductors within the second wafer. The edges of the first wafer are tacked to the edges of the second wafer. Then the wafers are pressed together and heat is applied to bond the wafers together. One feature of embodiments herein is that because the lock openings extend through an outer oxide (instead of a polyimide) the first wafer can be attached to the second wafer by using processing that occurs in the middle-of-the-line (MOL).

Abstract: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.

Abstract: A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between the semiconductor structure and the layer of gate material and closer to the first side of the second wafer than the semiconductor structure. The method further includes bonding the first side of the second wafer to the first wafer and cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a second storage layer over the layer of the semiconductor structure and forming a top gate over the second storage layer.

Abstract: The present invention provides a SOI wafer produced by an ion implantation delamination method wherein a width of a SOI island region in a terrace portion generated in an edge portion of the SOI wafer where a surface of a base wafer is exposed is narrower than 1 mm and a density of pit-shaped defects having a size of 0.19 ?m or more existing in a surface of a SOI layer detected by a LPD inspection is 1 counts/cm2 or less, and also provides a method for producing the SOI wafer. Thereby, there is provided a SOI wafer produced by an ion implantation delamination method wherein generation of SOI islands generated in delamination can be suppressed and a defect density of LPDs existing in a surface of the SOI wafer can be reduced, and a method for producing the same, so that device failure can be reduced.

Abstract: A method of forming a gate stack for semiconductor electronic devices utilizing wafer bonding of at least one structure containing a high-k dielectric material is provided. The method of the present invention includes a step of first selecting a first and second structure having a major surface respectively. In accordance with the present invention, at least one, or both, of the first and second structures includes at least a high-k dielectric material. Next, the major surfaces of the first and second structures are bonded together to provide a bonded structure containing at least the high-k dielectric material of a gate stack.

Abstract: An object of the present invention is to provide a method of forming a light-emitting element at a lower cost than a conventional cost with suppressing the deterioration of the substrate due to thermal distortion in comparison with a conventional method of recycling a substrate and further having an effect equal to that of the method of recycling a substrate.

Abstract: A method for bonding of substrates has a steps of irradiating surfaces of the substrates respectively in a vacuum with both an inert gas beam and a metal beam thereby forming island shaped thin metal films on the surfaces of the substrates, and surface-activated bonding of the substrates through the island shaped thin metal films by contacting the surfaces of the substrates each other.

Abstract: A method for temporary wafer bonding employs an addition reaction curable adhesive composition. The adhesive composition may include (A) a polyorganosiloxane containing an average of at least two silicon-bonded unsaturated organic groups per molecule, (B) an organosilicon compound containing an average of at least two silicon-bonded hydrogen atoms per molecule in an amount sufficient to cure the composition, (C) a catalytic amount of a hydrosilylation catalyst, and (D) a solvent. The film prepared by curing the composition is removable with an etching solution.

Abstract: A method of producing an optoelectronic substrate by detaching a thin layer from a semi-conducting nitride substrate and transferring it to an auxiliary substrate to provide at least one semi-conducting nitride layer thereon, metallizing at least a portion of the surface of the auxiliary substrate that includes the transferred nitride layer, bonding to a final substrate the metallized surface portion of the transferred nitrate layer of the auxiliary substrate, and removing the auxiliary substrate to provide an optoelectronic substrate comprising a semi-conducting nitride surface layer over a subjacent metallized portion and a supporting final substrate. Resultant optoelectronic substrates having low dislocation densities are also included.

Abstract: A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench (14), which reaches down to the insulator (11) and surrounds a region (13?) of the monocrystalline silicon (13) of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer region (17?) on a portion of the monocrystalline silicon region, forming a doped silicon layer region (18) on the insulating layer region (17?), and forming an insulating outside sidewall spacer (61) on the monocrystalline silicon region, where the outside sidewall spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon region. The monocrystalline silicon region (13?), the insulating layer region (17?), and the doped silicon layer region (18) constitute a lower electrode, a dielectric, and an upper electrode of the capacitor.

Abstract: A process for preparing a semiconductor wafer with a strained layer having an elevated critical thickness.

Abstract: Methods for fabricating compound material wafers are described. An embodiment of the method includes providing a donor substrate having a surface, forming a weakened zone in the donor substrate to define a transfer layer that includes the donor substrate surface, bonding the surface of the transfer layer to a handle substrate, and detaching the donor substrate at the weakened zone to transfer the transfer layer onto the handle substrate. Consequently, a compound material wafer is formed, and the transfer layer detached donor wafer provides a remainder substrate having a surface where the transfer layer was detached. Next, an additional layer is deposited onto a surface of the remainder substrate to increase its thickness and to form a reconditioned substrate, and the reconditioned substrate is recycled as a donor substrate for fabricating additional compound material wafers.

Abstract: A silicon-on-insulator (SOI) substrate is anodically bonded to a glass substrate in a MEMS structure with or without electrically bypassing the insulator layer by electrically comprising the silicon layers. The insulator layer serves as an etch stop to create a well-defined, thin silicon membrane for a sensor. A second glass substrate is anodically bonded to the other side of the SOI substrate, and debonding of the existing anodic bond prevented by eliminating any potential drop across the existing bonded surface.

Abstract: A method for producing a direct bonded wafer comprising: forming a thermal oxide film or a CVD oxide film on a surface of at least one of a bond wafer and a base wafer, and bonding the wafer to the other wafer via the oxide film; subsequently thinning the bond wafer to prepare a bonded wafer; and thereafter conducting a process of annealing the bonded wafer under an atmosphere including any one of an inert gas, hydrogen and a mixed gas of an inert gas and hydrogen so that the oxide film between the bond wafer and the base wafer is removed to bond the bond wafer directly to the base wafer. Thereby, there is provided a method for producing a direct bonded wafer in which generation of voids is reduced, and a direct bonded wafer with a low void count.

Abstract: A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.

Abstract: A method of forming a stack of thin wafers provides a wafer level stack to greatly reduce process time compared to a method where individually separated chips are stacked after a wafer is sawed. A rigid planar wafer support member stabilizes and planarizes each wafer while it is thin or its thickness is reduced and during subsequent wafer processing. Thinned wafers are stacked and the external support members are removed by applying heat or ultraviolet (UV) light to an expandable adhesive layer between the support members and the thin wafers. The stacked wafers then can be further processed and packaged without thin-wafer warping, cracking or breaking. A wafer level package made in accordance with the invented method also is disclosed.

Abstract: An object of the present invention is to provide a structure of a thin film circuit portion and a method for manufacturing a thin film circuit portion by which an electrode for connecting to an external portion can be easily formed under a thin film circuit. A stacked body including a first insulating film, a thin film circuit formed over one surface of the first insulating film, a second insulating film formed over the thin film circuit, an electrode formed over the second insulating film, and a resin film formed over the electrode, is formed. A conductive film is formed adjacent to the other surface of the first insulating film of the stacked body to be overlapped with the electrode. The conductive film is irradiated with a laser.

Abstract: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).

Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.

Abstract: A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

Abstract: A technique is described in which a layer to be transferred is easily peeled and transferred to a transferred body that is pliable or flexible. Also, a method of fabricating a semiconductor device using these peeling and transfer techniques, and electronic equipment fabricated with the semiconductor device is described. A transfer method in which a layer to be transferred formed on a substrate is transferred to a transfer body that is pliable or flexible includes the first step of forming a layer to be transferred on a substrate; the second step of bonding the layer to be transferred formed on the substrate to a transfer body that is pliable or flexible fixed on a fixture; and the third step of peeling the layer to be transferred from the substrate and transferring the layer to be transferred to the transfer body.

Abstract: The invention relates to a method for fabricating a composite structure having heat dissipation properties greater than a bulk single crystal silicon structure having the same dimensions. The structure includes a support substrate, a top layer and an oxide layer between the support substrate and the top layer.

Abstract: A method of manufacturing a photodetecting device, by providing a first wafer that includes a photosensitive layer made of a semiconductor material and a second wafer that includes a circuit layer of electronic components, with one of the photosensitive layer or the circuit layer incorporating a field isolation layer; bonding the first and second wafers to form a structure comprising successively the circuit layer, the field isolation layer and the photosensitive layer; and forming electrically conductive vias to electrically connect the photosensitive layer to at least some of the electronic components of the circuit layer. Also, photodetecting devices prepared by these methods.

Abstract: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

Abstract: A patterned ground shield (PGS) (130) in a vertically-integrated structure includes a patterned conductor (e.g., a metallic layer) provided between a first substrate (110) having a first semiconductor device (1120 formed therein and a second substrate (120) having a second device (122) formed therein. A bonding layer (140) is used to bond the vertically-integrated die and/or wafers. The PGS may be formed on a surface (e.g., the backside) of the second (topmost) substrate, or may be formed over the first semiconductor device—for example, on a dielectric layer formed over the first semiconductor device. The PGS may consist of parallel stripes in various patterns, or may be spiral-shaped, lattice-shaped, or the like.

Abstract: The invention relates to a treatment method of a structure comprising a thin Ge layer on a substrate, said layer having been previously bonded with the substrate, the method comprising a treatment to improve the electrical properties of the layer and/or the interface of the Ge layer with the underlying layer, characterised in that said treatment is a heat treatment applied at a temperature between 500° C. and 600° C. for not more than 3 hours.

Abstract: In a process of forming a single-crystalline semiconductor layer bonded to a glass substrate by low-temperature heat treatment, before a bonding and separation step in which the single-crystalline semiconductor layer is bonded to the glass substrate, the glass substrate is heated at a temperature higher than a heat temperature in the bonding and separation step. In a bonding step between the single-crystalline semiconductor layer and the glass substrate, the single-crystalline semiconductor layer is heated at a temperature close to a strain point of the glass substrate, specifically at a temperature in a range from minus 50° C. to plus 50° C. of a strain point. Accordingly, the glass substrate is subjected to heat treatment in advance at a temperature higher than the temperature close to the strain point, specifically, at a temperature higher than the temperature in a range from minus 50° C. to plus 50° C. of the strain point.

Abstract: A silicon direct bonding (SDB) method by which void formation caused by gases is suppressed. The SDB method includes: preparing two silicon substrates having corresponding bonding surfaces; forming trenches having a predetermined depth in at least one bonding surface of the two silicon substrates; forming gas discharge outlets connected to the trenches on at least one of the two silicon substrates to vertically penetrate the bonding surface; cleaning the two silicon substrates; closely contacting the two silicon substrates to each other; and thermally treating the two substrates to bond them to each other. The trenches are formed along at least a part of a plurality of dicing lines, and both ends of the trenches are clogged. Gases generated during a thermal treatment process can be smoothly and easily discharged through the trenches and the gas discharge outlet such that a void is prevented from being formed in the junctions of the two silicon substrates due to the gases.

Abstract: The present invention provides a semiconducting structure including a substrate having an UTSOI region and a bulk-Si region, wherein the UTSOI region and the bulk-Si region have a same crystallographic orientation; an isolation region separating the UTSOI region from the bulk-Si region; and at least one first device located in the UTSOI region and at least one second device located in the bulk-Si region. The UTSOI region has an SOI layer atop an insulating layer, wherein the SOI layer has a thickness of less than about 40 nm. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects.

Abstract: A method of fabricating wafer level package is provided. The method includes the following steps. Firstly, a wafer having a front surface and a rear surface is provided, and the front surface has several conductive pads. Next, a supporting material is attached on the front surface. Then, several holes are formed on the wafer, and the holes run from the rear surface to the front surface. A first substrate is attached on the rear surface. The first substrate has several conductive pillars correspondingly inserted into the holes. Afterwards, the supporting material is removed to expose the conductive pillars on the front surface, and a patterned circuit is formed on the front surface. Next, a second substrate is attached on the patterned circuit. Then, several conductive structures are formed on the first substrate.

Abstract: A plurality of wafers are aligned and stacked on a thermally variable rotary table, the table and stack are rotated, and an underfill material is disposed and cured between wafers in the stack, bonding the wafers. Corresponding wafer portions of the plurality of wafers in the stack may be singulated from the stack, and may comprise semiconductor device packages either individually or when coupled with a substrate.

Abstract: A method for fabricating a mixed substrate that include insulating material layer portions buried in a substrate of semiconductor material. The method includes providing a support substrate made of semiconductor material and having a front face that includes open cavities; providing a layer of an insulating material upon the front face of the support substrate and into the cavities; polishing the layer to provide a perfectly planar surface; bonding a source substrate to the planar surface of the support substrate; withdrawing a portion of the source substrate to provide an assembly having a thin useful or active layer upon the insulating layer of the support substrate; and heat treating the assembly in a selected atmosphere at a temperature and for a time sufficient to diffuse atoms from the insulating layer and through the thin layer to reduce the thickness of the insulating layer while retaining the insulating material in the cavities of the support substrate.

Abstract: A peeling method is provided which does not cause damage to a layer to be peeled, and the method enables not only peeling of the layer to be peeled having a small area but also peeling of the entire layer to be peeled having a large area at a high yield. Further, there are provided a semiconductor device, which is reduced in weight through adhesion of the layer to be peeled to various base materials, and a manufacturing method thereof. In particular, there are provided a semiconductor device, which is reduced in weight through adhesion of various elements, typically a TFT, to a flexible film, and a manufacturing method thereof. A metal layer or nitride layer is provided on a substrate; an oxide layer is provided contacting with the metal layer or nitride layer; then, a base insulating film and a layer to be peeled containing hydrogen are formed; and heat treatment for diffusing hydrogen is performed thereto at 410° C. or more.

Abstract: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.

Abstract: A thickness of silicon oxide film of a wafer for active layer is controlled to be thinner than that of buried silicon oxide film. Consequently, uniformity in film thickness of the active layer of a bonded wafer is improved even if a variation in the in-plane thickness of the silicon oxide film is large at a time of ion implantation. Furthermore, since the silicon oxide film is rather thinner and thereby the ion implantation depth is relatively deeper, damages to the active layer and the buried silicon oxide film caused by the ion implantation can be reduced.