Abstract: A semiconductor processing system including a semiconductor processing apparatus and a gas supply apparatus for supplying a process gas into the semiconductor processing apparatus includes a control section configured to control an operation of a pressure adjusting mechanism for adjusting the pressure inside a vaporizing chamber. The control section is preset to cause the pressure inside the vaporizing chamber to fall within a predetermined pressure range with reference to a pressure detection value obtained by a pressure detector. The predetermined pressure range is defined by an upper limit lower than a first limit value, at which vaporization of the liquid material starts being inhibited due to an increase in the pressure, and a lower limit higher than a second limit value, at which vaporization of the liquid material starts being unstable and the pressure inside the vaporizing chamber starts pulsating movement due to a decrease in the pressure.

Abstract: A method of forming a micromechanical structure, wherein at least one micromechanical structural layer is provided above a substrate. The micromechanical structural layer is sustained between a lower sacrificial silicon layer and an upper sacrificial silicon layer, wherein a metal silicide layer is formed between the lower and upper sacrificial silicon layers to increase interface adhesion therebetween. The upper sacrificial silicon layer, the metal silicide layer and the lower sacrificial silicon layer are then removed to release the micromechanical structural layer.

Abstract: A high-quality dielectric film is formed by generating plasma of a high electron density by a method such as diluting a rare gas or raising a frequency of a power supplier, and generating oxygen atoms or nitrogen atoms of a high density. The dielectric film contains silicon oxide in which the composition ratio of silicon and oxygen is between (1:1.94) and (1:2) both inclusive, silicon nitride in which the composition ratio of silicon and nitrogen is between (1:1.94) and (1:2) both inclusive, or silicon oxynitride in which the composition ratio of silicon and nitrogen is between (3:3.84) and (3:4) both inclusive.

Abstract: The present invention relates to a method for forming a metal silicon nitride film according to a cyclic film deposition under plasma atmosphere with a metal amide, a silicon precursor, and a nitrogen source gas as precursors. The deposition method for forming a metal silicon nitride film on a substrate comprises steps of: pulsing a metal amide precursor; purging away the unreacted metal amide; introducing nitrogen source gas into reaction chamber under plasma atmosphere; purging away the unreacted nitrogen source gas; pulsing a silicon precursor; purging away the unreacted silicon precursor; introducing nitrogen source gas into reaction chamber under plasma atmosphere; and purging away the unreacted nitrogen source gas.

Abstract: A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer over an initial sub-layer, and wherein the transition sub-layer has a composition that gradually changes from a lower portion to an upper portion. A low-k dielectric layer is formed on the adhesion layer. Damascene openings are formed in the low-k dielectric layer. A top portion of the transition sub-layer has a composition substantially similar to a composition of the low-k dielectric layer. A bottom portion of the transition sub-layer has a composition substantially similar to a composition of the initial sub-layer.

Abstract: A compact large density memory piezoactuated storage device and process for its fabrication provides an integrated microelectromechanical (MEMS) and/or nanoelectromechanical (NEMS) system and structure that features an integrated large density array of nanotips made of wear-resistant conductive ultrananocrystalline diamond (UNCD) in which the tips are actuated via a piezoelectric thin film integrated with the UNCD tips. The tips of the special piezoactuated storage device effectively contact an underlying metal layer (top electrode) deposited on a polarizable ferroelectric layer that is grown on top of another metal layer (bottom electrode) to form a ferroelectric capacitor. Information is imprinted in the ferroelectric layer by the polarization induced by the application of a voltage pulse between the top and bottom electrodes through the conductive UNCD tips.

Abstract: Methods and compositions for the deposition of a transition metal containing film in a semiconductor manufacturing process. A first vaporized metal precursor is introduced into a reaction chamber along with a second precursor mixture which comprises at least one carbon source.

Abstract: A method for patching up thin-film transistor (TFT) circuit patterns on a display panel comprises the following steps. Firstly, a mask having an opening is placed above the display panel and the opening corresponds to the location of the cracks of the circuits on the display panel. Subsequently, a plasma sputtering procedure is performed to deposit a metal thin film through the opening of the mask on the display panel so as to connect the broken circuits. When the metal thin film is covered on a plurality of the circuits, a laser cut-out procedure is performed to cut apart the metal thin film on the plurality of the circuits so as to prevent the different circuits from short circuits.

Abstract: A method of forming (and apparatus for forming) a tantalum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and a tantalum precursor compound that includes alkoxide ligands, for example.

Abstract: Contacting materials and methods for forming ohmic contact to the N-face polarity surfaces of Group-III nitride based semiconductor materials, and devices fabricated using the methods. One embodiment of a light emitting diode (LED) a Group-III nitride active epitaxial region between two Group-III nitride oppositely doped epitaxial layers. The oppositely doped layers have alternating face polarities from the Group III and nitrogen (N) materials, and at least one of the oppositely doped layers has an exposed surface with an N-face polarity. A first contact layer is included on and forms an ohmic contact with the exposed N-face polarity surface. In one embodiment, the first contact layer comprises indium nitride.

Abstract: The invention includes deposition methods and apparatuses which can be utilized during atomic layer deposition or chemical vapor deposition. A heated surface is provided between a stack of semiconductor substrates and a precursor inlet, and configured so that problematic side reactions occur proximate the heated surface rather than proximate the semiconductor substrates. The precursor inlet can be one of a plurality of precursor inlets, and the heated surface can be one of a plurality of heated surfaces.

Abstract: The present invention provides a semiconductor memory device having a tunnel insulating film that does not degrade the endurance characteristics when writing/erasing is repeated, even if the tunnel insulating film is made thinner. The semiconductor memory device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate, and including a silicon oxynitride film and a silicon-rich silicon oxide film formed on the silicon oxynitride film, the silicon oxynitride film having a stacked structure formed with a first silicon oxynitride layer, a silicon nitride layer, and a second silicon oxynitride layer in order; a charge storage layer formed on the first insulating film; a second insulating film formed on the charge storage layer; and a control gate formed on the second insulating film.

Abstract: A method for fabricating a semiconductor device includes forming a first recess in a substrate, forming a plasma oxide layer over the substrate including first recess, etching the plasma oxide layer to have a portion of the plasma oxide layer remain on sidewalls of the first recess, and forming a second recess by isotropically etching a bottom portion of the first recess, wherein the second recess has a width greater than a width of the first recess.

Abstract: The semiconductor device fabrication method comprises the step of forming a first porous insulation film 38 over a semiconductor substrate 10; the step of forming a second insulation film 40 whose density is higher than that of the first porous insulation film 38; and the step of applying electron beams, UV rays or plasmas with the second insulation film 40 present to the first porous insulation film 38 to cure the first porous insulation film 38. The electron rays, etc. are applied to the first porous insulation film 38 through the denser second insulation film 40, whereby the first porous insulation film 38 can be cured without being damaged. The first porous insulation film 38 can be kept from being damaged, whereby the moisture absorbency and density increase can be prevented, and resultantly the dielectric constant increase can be prevented. Thus, the present invention can provide a semiconductor device including an insulation film of low dielectric constant and high mechanical strength.

Abstract: An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.

Abstract: A method for forming a gate dielectric layer is described. A silicon oxide layer is formed on a semiconductor substrate. Then, a first and a second nitrogen doping processes are performed in sequence to the silicon oxide layer using plasma comprising inert gas and gaseous nitrogen to form a gate dielectric layer. The first nitrogen doping process is performed at a lower power, a lower pressure and a higher inert gas to nitrogen gas ratio than those at the second nitrogen doping process. The combination of the deeper nitrogen distribution of the first nitrogen doping process and the shallower nitrogen distribution of the second nitrogen doping process produces a flatter total nitrogen distribution profile so that leakage current from electron tunneling through the gate dielectric layer can be reduced.

Abstract: A technique for more efficiently forming conductive elements, such as conductive layers and electrodes, using chemical vapor deposition. A conductive precursor gas, such as a platinum precursor gas, having organic compounds to improve step coverage is introduced into a chemical vapor deposition chamber. A reactant is also introduced into the chamber that reacts with residue organic compounds on the conductive element so as to remove the organic compounds from the nucleating sites to thereby permit more efficient subsequent chemical vapor deposition of conductive elements.

Abstract: A densified dielectric film is formed on a substrate by a process that involves annealing a film deposited on the substrate by application of a localized energy pulse, such as a laser pulse, for example one of about 10 to 100 ns in duration from an excimer laser, that raises the temperature of the film above 1000° C. without raising the substrate temperature sufficiently to modify its properties (e.g., the substrate temperature remains below 550° C. or preferably in many applications below 400° C.). The dielectric deposition may be by any suitable process, for example CVD, SOG (spin-on glass), ALD, or catalyzed PDL. The resulting film is densified without detrimentally impacting underlying substrate layers. The invention enables dielectric gap fill and film densification at low temperature to the 45 nm technology node and beyond, while maintaining oxide film properties.

Abstract: A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.