Deposition From Gas Or Vapor (epo) Patents (Class 257/E21.274)
  • Patent number: 7531468
    Abstract: A method of forming a dielectric stack on a pre-treated surface. The method comprises pre-cleaning a semiconductor wafer to remove native oxide, such as by applying hydrofluoric acid to form an HF-last surface, pre-treating the HF-last surface with ozonated deionized water, forming a dielectric stack on the pre-treated surface and providing a flow of NH3 in a process zone surrounding the wafer. Alternately, the method includes pre-treating the HF-last surface with NH3, forming the stack after the pre-treating, and providing a flow of N2 in a process zone surrounding the wafer after the forming. The method also includes pre-treating the HF-last surface using an in-situ steam generation process, forming the stack on the pre-treated surface, and annealing the wafer after the forming.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: May 12, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Craig R. Metzner, Shreyas S. Kher, Shixue Han
  • Patent number: 7528037
    Abstract: A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be deposited using evaporation techniques or atomic layer deposition techniques. The floating gate is formed on top of the high-k dielectric layer with an oxide gate insulator on top of that. A polysilicon control gate is formed on the top gate insulator.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: May 5, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 7528059
    Abstract: By forming a capping layer after a CMP process for planarizing the surface topography of an ILD layer, any surface irregularities may be efficiently sealed, thereby reducing the risk for forming conductive surface irregularities during the further processing. Consequently, yield loss effects caused by leakage paths or short circuits in the first metallization layer may be significantly reduced.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: May 5, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Sandra Bau, Johannes Groschopf
  • Patent number: 7524741
    Abstract: A method of forming a low temperature-grown buffer layer having the steps of: placing a Ga2O3 substrate in a MOCVD apparatus; providing a H2 atmosphere in the MOCVD apparatus and setting a buffer layer growth condition having an atmosphere temperature of 350° C. to 550° C.; and supplying a source gas having two or more of TMG, TMA and NH3 onto the Ga2O3 substrate in the buffer layer growth condition to form the low temperature-grown buffer layer on the Ga2O3 substrate.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 28, 2009
    Assignees: Toyoda Gosei Co., Ltd., Koha Co., Ltd.
    Inventors: Yasuhisa Ushida, Daisuke Shinoda, Daisuke Yamazaki, Koji Hirata, Yuhei Ikemoto, Naoki Shibata, Kazuo Aoki, Encarnacion Antonia Garcia Villora, Kiyoshi Shimamura
  • Publication number: 20090092856
    Abstract: A solid film-formation material feeding apparatus includes a supercritical fluid supply source for supplying supercritical fluid; and a column which is connected to the supercritical fluid supply source, and has a hollow part which is filled with a filler which is inactive for the supercritical fluid, wherein the hollow part can be further filled with a solid film-formation material which is soluble in the supercritical fluid. A column assembly which includes a plurality of the columns which may be connected in parallel to each other.
    Type: Application
    Filed: October 7, 2008
    Publication date: April 9, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hiroyuki ODE
  • Patent number: 7514375
    Abstract: During bottom filling of high aspect ratio gaps and trenches in an integrated circuit substrate using HDP-CVD, a pulsed HF bias is applied to the substrate. In some embodiments, pulsed HF bias is applied to the substrate during etching operations. The pulsed bias typically has a pulse frequency in a range of about from 500 Hz to 20 kHz and a duty cycle in a range of about from 0.1 to 0.95.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: April 7, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Sunil Shanker, Chi-I Lang
  • Patent number: 7510983
    Abstract: Embodiments of an electronic apparatus and embodiments for methods of forming the electronic apparatus include a conductive layer having an iridium-based layer, where the conductive layer is disposed on a dielectric layer containing zirconium oxide. In various embodiments, each of the zirconium oxide layer and the iridium-based layer may be structured as one or more monolayers. In various embodiments, each of the iridium-based layer and the zirconium oxide layer may be formed using atomic layer deposition.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: March 31, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20090053906
    Abstract: Disclosed is a producing method of a semiconductor device including: loading at least one substrate into a processing chamber; forming a metal oxide film or a silicon oxide film on a surface of the substrate by repeatedly supplying a metal compound or a silicon compound, each of which is a first material, an oxide material which is a second material including an oxygen atom, and a hydride material which is a third material, into the processing chamber predetermined times; and unloading the substrate from the processing chamber.
    Type: Application
    Filed: July 19, 2007
    Publication date: February 26, 2009
    Inventors: Hironobu Miya, Kazuhiro Hirahara, Yoshitaka Hamada, Atsuhiko Suda
  • Patent number: 7494937
    Abstract: A method for forming a strained metal silicon nitride film and a semiconductor device containing the strained metal silicon nitride film. The method includes exposing a substrate to a gas containing a metal precursor, exposing a substrate to a gas containing a silicon precursor, exposing the substrate to a gas containing a first nitrogen precursor configured to react with the metal precursor or the silicon precursor with a first reactivity characteristic, and exposing the substrate to a gas pulse containing a second nitrogen precursor configured to react with the metal precursor or the silicon precursor with a second reactivity characteristic different than the first reactivity characteristic such that a property of the metal silicon nitride film formed on the substrate changes to provide a strained metal silicon nitride film.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 24, 2009
    Assignee: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Patent number: 7482286
    Abstract: Method for producing a metal silicon (oxy)nitride by introducing a carbon-free silicon source (for example, (SiH3)3N), a metal precursor with the general formula MXn (for example, Hf(NEt2)4), and an oxidizing agent (for example, O2) into a CVD chamber and reacting same at the surface of a substrate. MsiN, MSIo and/or MSiON films may be obtained. These films are useful are useful as high k dielectrics films.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: January 27, 2009
    Assignee: L'Air Liquide, Societe Anonyme A Directoire et Conseil de Surveillance pour l'Etude et l'Exploitation des Procedes Georges Claude
    Inventors: Ashutosh Misra, Matthew Fisher, Benjamin Jurcik, Christian Dussarrat, Eri Tsukada, Jean-Marc Girard
  • Publication number: 20080318439
    Abstract: A semiconductor wafer is placed in a chamber of a film-deposition apparatus, and gas in the chamber is exhausted from a gas exhaust outlet. Then, with interrupting the exhaust, an inert gas is introduced into the chamber so that the chamber has a pressure of 133 Pa or higher and lower than 101325 Pa, and then a mixed gas of an inert gas and a source gas for depositing a metal oxide film is introduced into the chamber. Then, after exhausting the gas in the chamber, an oxidation gas is introduced into the chamber to react with the molecules of the source gas absorbed on the semiconductor wafer to form a metal oxide film on the semiconductor wafer. By repeating these steps, a metal oxide film having a desired film thickness is deposited on the semiconductor wafer with a film-thickness distribution by an ALD method.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 25, 2008
    Inventors: Hiromi Ito, Yuuichi Kamimuta, Yukimune Watanabe, Shinji Migita
  • Patent number: 7465679
    Abstract: A silicon oxide film is formed to cover an island non-monocrystalline silicon region by plasma CVD using an organic silane having ethoxy groups (e.g., TEOS) and oxygen as raw materials, while hydrogen chloride or a chlorine-containing hydrocarbon (e.g., trichloroethylene) of a fluorine-containing gas is added to the plasma CVD atmosphere, preferably in an amount of from 0.01 to 1 mol % of the atmosphere so as to reduce the alkali elements from the silicon oxide film formed and to improve the reliability of the film. Prior to forming the silicon oxide film, the silicon region may be treated in a plasma atmosphere containing oxygen and hydrogen chloride or a chlorine-containing hydrocarbon. The silicon oxide film is obtained at low temperatures and this has high reliability usable as a gate-insulating film in a semiconductor device.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: December 16, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takeshi Fukada, Mitsunori Sakama, Yukiko Uehara, Hiroshi Uehara
  • Patent number: 7459390
    Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: December 2, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Reima Tapani Laaksonen
  • Publication number: 20080293256
    Abstract: A bismuth titanium silicon oxide having a pyrochlore phase, a thin film formed of the bismuth titanium silicon oxide, a method for forming the bismuth-titanium-silicon oxide thin film, a capacitor and a transistor for a semiconductor device including the bismuth-titanium-silicon oxide thin film, and an electronic device employing the capacitor and/or the transistor are provided. The bismuth titanium silicon oxide has good dielectric properties and is thermally and chemically stable. The bismuth-titanium-silicon oxide thin film can be effectively used as a dielectric film of a capacitor or as a gate dielectric film of a transistor in a semiconductor device. Various electronic devices having good electrical properties can be manufactured using the capacitor and/or the transistor having the bismuth-titanium-silicon oxide film.
    Type: Application
    Filed: May 14, 2008
    Publication date: November 27, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jin Cho, Yo-sep Min, Young-soo Park, Jung-hyun Lee, June-key Lee, Yong-kyun Lee
  • Publication number: 20080286983
    Abstract: Methods and compositions for depositing high-k films are disclosed herein. In general, the disclosed methods utilize precursor compounds comprising Ta or Nb. More specifically, the disclosed precursor compounds utilize certain ligands coupled to Ta and/or Nb such as 1-methoxy-2-methyl-2-propanolate (mmp) to increase volatility. Furthermore, methods of depositing Ta or Nb compounds are disclosed in conjunction with use of Hf and/or Zr precursors to deposit Ta-doped or Nb-doped Hf and/or Zr films. The methods and compositions may be used in CVD, ALD, or pulsed CVD deposition processes.
    Type: Application
    Filed: April 7, 2008
    Publication date: November 20, 2008
    Inventor: Christian DUSSARRAT
  • Publication number: 20080268657
    Abstract: The application of oxynitriding treatment to electronic appliances involve the problem that N2 ions are formed to thereby damage any oxynitride film. It is intended to provide a method of plasma treatment capable of realizing high-quality oxynitriding and to provide a process for producing an electronic appliance in which use is made of the method of plasma treatment. There is provided a method of plasma treatment, comprising generating plasma with a gas for plasma excitation and introducing a treating gas in the plasma to thereby treat a treatment subject, wherein the treating gas contains nitrous oxide gas, this nitrous oxide gas introduced in a plasma of <2.24 eV electron temperature, so that the generation of ions tending to damage any insulating film is reduced to thereby realize high-quality oxynitriding. Further, there is provided a process for producing an electronic appliance in which use is made of the method of plasma treatment.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 30, 2008
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Yamauchi, Yukio Hayakawa
  • Patent number: 7442654
    Abstract: A method of forming a dielectric layer structure on a supporting semiconductor structure having a first surface comprises providing a first beam of oxide; depositing a first layer of oxide on the first surface of the supporting semiconductor structure using the first beam of oxide, wherein the first layer of oxide has a second surface; terminating the first beam of oxide, and concurrently providing a second beam of oxide, a beam of metal and a beam of oxygen, wherein the first and second beams of oxide are separate and distinct beams of oxide; and depositing a second layer of oxide on the second surface simultaneously using the second beam of oxide, the beam of metal, and the beam of oxygen.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 28, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindranath Droopad, Matthias Passlack
  • Patent number: 7442633
    Abstract: Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the capacitor includes a substrate, a high K dielectric layer doped with nano crystals disposed on the substrate, and a top plate layer disposed on the high K dielectric layer. According to one embodiment, the high K dielectric layer includes Al2O3. According to other embodiments, the nano crystals include gold nano crystals and gold nano crystals. One capacitor embodiment includes a MIS (metal-insulator-silicon) capacitor fabricated on silicon substrate, and another capacitor embodiment includes a MIM (metal-insulator-metal) capacitor fabricated between the interconnect layers above silicon substrate. The structure of the capacitor is useful for reducing a resonance impedance and a resonance frequency for an integrated circuit chip. Other aspects are provided herein.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: October 28, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7416994
    Abstract: The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one ?-diketiminate ligand. Such systems and methods can be useful for depositing metal-containing layers on substrates.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: August 26, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Timothy A. Quick
  • Patent number: 7408225
    Abstract: A thin-film formation apparatus possesses a reaction chamber to be evacuated, a placing portion on which a substrate is placed inside the reaction chamber, a gas-dispersion guide installed over the placing portion for supplying a gas onto a substrate surface, a gas-supply port for introducing the gas into the gas-dispersion guide, a gas-dispersion plate disposed on the side of the substrate of the gas-dispersion guide and having multiple gas-discharge pores, a first exhaust port for exhausting, downstream of the gas-dispersion plate, the gas supplied onto the substrate surface from the gas-dispersion plate, and a second exhaust port for exhausting, upstream of the gas-dispersion plate, a gas inside the gas-dispersion guide via a space between the gas-dispersion guide and the gas-dispersion plate.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: August 5, 2008
    Assignee: ASM Japan K.K.
    Inventors: Hiroshi Shinriki, Baiei Kawano, Akira Shimizu
  • Publication number: 20080160647
    Abstract: A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick oxide on the wafer backside so that at least pre-selected oxide thickness remains after back end of line processing is complete and performing the back end of line processing of the memory device.
    Type: Application
    Filed: February 22, 2007
    Publication date: July 3, 2008
    Inventor: Nhan Hanh Anderson
  • Patent number: 7390756
    Abstract: A dielectric layer containing an atomic layer deposited zirconium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. Embodiments include forming zirconium silicates as dielectric layers in devices in an integrated circuit. In an embodiment, a zirconium silicon oxide film is formed by atomic layer deposition using a zirconium precursor containing silicon and a silicon precursor. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing an atomic layer deposited zirconium silicon oxide film, and methods for forming such structures.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: June 24, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20080132084
    Abstract: To improve a step coverage and a loading effect, without inviting a deterioration of throughput and an increase of cost, in a method for forming a thin film by alternately flowing a raw material and alcohol to a processing chamber.
    Type: Application
    Filed: November 7, 2007
    Publication date: June 5, 2008
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Hironobu Miya, Norikazu Mizuno, Masanori Sakai, Shinya Sasaki, Hirohisa Yamazaki
  • Publication number: 20080128833
    Abstract: A high-dielectric-constant film including hafnium, wherein the above-mentioned high-dielectric-constant film includes deuterium at a ratio higher than the ratio of deuterium to hydrogen present in nature. In a field-effect transistor provided with the high-dielectric-constant film including hafnium, the interface state density at the interface between a silicon substrate and a gate dielectric film decreases and carrier mobility in the gate dielectric film increases. In the present invention, a high-dielectric-constant constant second dielectric film, which is a thin film including hafnium such as HfSiON or HfAlOx and including deuterium at a ratio higher than the ratio of deuterium to hydrogen present in nature, is used as the gate dielectric film of the field-effect transistor.
    Type: Application
    Filed: August 25, 2005
    Publication date: June 5, 2008
    Inventors: Takaaki Kawahara, Kazuyoshi Torii, Minoru Inoue, Satoshi Hasaka
  • Patent number: 7319068
    Abstract: A method is provided for processing a substrate including providing a processing gas comprising an organosilicon compound comprising a phenyl group to the processing chamber, and reacting the processing gas to deposit a low k silicon carbide barrier layer useful as a barrier layer in damascene or dual damascene applications with low k dielectric materials.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: January 15, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Ping Xu, Louis Yang
  • Patent number: 7312165
    Abstract: Methods of film deposition using metals and metal oxides. A thin film of germanium oxide and an oxide of a non-germanium metal is deposited by ALD by alternating deposition of first and second precursor compounds, wherein the first precursor compound includes a metal other than germanium, and the second precursor compound includes germanium.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: December 25, 2007
    Inventors: Gregory M. Jursich, Ronald S. Inman
  • Patent number: 7312127
    Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: December 25, 2007
    Assignee: LSI Corporation
    Inventors: Wai Lo, Verne Hornback, Wilbur G. Catabay, Wei-Jen Hsia, Sey-Shing Sun
  • Patent number: 7304004
    Abstract: A method of forming a dielectric stack on a pre-treated surface. The method comprises pre-cleaning a semiconductor wafer to remove native oxide, such as by applying hydroflouric acid to form an HF-last surface, pre-treating the HF-last surface with ozonated deionized water, forming a dielectric stack on the pre-treated surface and providing a flow of NH3 in a process zone surrounding the wafer. Alternately, the method includes pre-treating the HF-last surface with NH3, forming the stack after the pre-treating, and providing a flow of N2 in a process zone surrounding the wafer after the forming. The method also includes pre-treating the HF-last surface using an in-situ steam generation process, forming the stack on the pre-treated surface, and annealing the wafer after the forming.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: December 4, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Craig R. Metzner, Shreyas S. Kher, Shixue Han
  • Patent number: 7238629
    Abstract: The present invention relates to a deposition method of a low dielectric constant insulating film, which comprises the steps of generating a first deposition gas containing at least one silicon source selecting from the group consisting of silicon containing organic compound having siloxane bond and silicon containing organic compound having CH3 group, and an oxidizing agent consisting of oxygen containing organic compound having alkoxyl group (OR: O is oxygen and R is CH3 or C2H5), and applying electric power to the first deposition gas to generate plasma and then causing reaction to form a low dielectric constant insulating film on a substrate.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: July 3, 2007
    Assignee: Semiconductor Process Laboratory Co., Ltd.
    Inventors: Yoshimi Shioya, Kazuo Maeda
  • Patent number: 7202183
    Abstract: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D2, HD, DT, T2 and TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing H2 under otherwise substantially identical conditions.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: April 10, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Neal R. Rueger, William Budge, Weimin Li, Gurtej S. Sandhu
  • Patent number: 7186663
    Abstract: A method is provided for forming a Si and Si—Ge thin films. The method comprises: providing a low temperature substrate material of plastic or glass; supplying an atmosphere; performing a high-density (HD) plasma process, such as an HD PECVD process using an inductively coupled plasma (ICP) source; maintaining a substrate temperature of 400 degrees C., or less; and, forming a semiconductor layer overlying the substrate that is made from Si or Si-germanium. The HD PECVD process is capable of depositing Si at a rate of greater than 100 ? per minute. The substrate temperature can be as low as 50 degrees C. Microcrystalline Si, a-Si, or a polycrystalline Si layer can be formed over the substrate. Further, the deposited Si can be either intrinsic or doped. Typically, the supplied atmosphere includes Si and H. For example, an atmosphere can be supplied including SiH4 and H2, or comprising H2 and Silane with H2/Silane ratio in the range of 0–100.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: March 6, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Pooran Chandra Joshi, Apostolos T. Voutsas, John W. Hartzell
  • Patent number: 7166541
    Abstract: A method of forming a dielectric layer using a plasma enhanced atomic layer deposition technique includes: loading a semiconductor substrate having a three-dimensional structure into a reaction chamber; and repeatedly performing the following steps until a dielectric layer with a desired thickness is formed: supplying a source gas into the reaction chamber; stopping the supply of the source gas and purging the source gas remaining inside the reaction chamber; and supplying oxygen gas into the reaction chamber after purging the source gas, and applying RF power for oxygen plasma treatment, a level of the applied RF power and a partial pressure of the oxygen gas being increased concurrently with an increased aspect ratio of the three-dimensional structure.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: January 23, 2007
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Min-Woo Song, Seok-Jun Won, Yong-Kuk Jeong, Dae-Jin Kwon, Weon-Hong Kim
  • Patent number: 7163901
    Abstract: A method is provided for forming a thin film layer on a substrate. The method includes the steps of doping a thin surface layer on the substrate with low energy ions of a dopant material, and heating the thin surface layer sufficiently to produce a reaction between the dopant material and the surface layer. The heating step is performed simultaneously with at least part of the doping step. The doping step may utilize plasma doping of the thin surface layer. In one embodiment, the doping step includes plasma doping of a silicon oxide layer with nitrogen ions. The heating step may utilize thermal conduction or heating with radiation, such as heating with optical energy. The process may be used for forming dielectric layers having a thickness of 50 angstroms or less.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: January 16, 2007
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Daniel F. Downey
  • Patent number: 7160821
    Abstract: A silicon oxide layer is produced by plasma enhanced decomposition of an organosilicon compound to deposit films having a carbon content of at least 1% by atomic weight. An optional carrier gas may be introduced to facilitate the deposition process at a flow rate less than or equal to the flow rate of the organosilicon compounds. An oxygen rich surface may be formed adjacent the silicon oxide layer by temporarily increasing oxidation of the organosilicon compound.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: January 9, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Tzu-Fang Huang, Yung-Cheng Lu, Li-Qun Xia, Ellie Yieh, Wai-Fan Yau, David W. Cheung, Ralf B. Willecke, Kuowei Liu, Ju-Hyung Lee, Farhad K. Moghadam, Yeming Jim Ma
  • Patent number: 7153786
    Abstract: Methods of fabricating a lanthanum oxide layer, and methods of fabricating a MOSFET and/or a capacitor especially adapted for semiconductor applications using such a lanthanum oxide layer are disclosed. The methods include a preliminary step of disposing a semiconductor substrate into a chamber. Tris(bis(trimethylsilyl)amino)Lanthanum as a lanthanum precursor is then injected into the chamber such that the lanthanum precursor is chemisorbed on the semiconductor substrate. Then, after carrying out a first purge of the chamber, at least one oxidizer is injected into the chamber such that the oxidizer is chemisorbed with the lanthanum precursor on the semiconductor substrate. Then, the chamber is purged a second time.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: December 26, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Jong-Pyo Kim, Jung-Hyun Lee, Bum-Seok Seo, Jung-Hyoung Lee
  • Patent number: 7125813
    Abstract: A method is provided for processing a substrate including providing a processing gas comprising an organosilicon compound comprising a phenyl group to the processing chamber, and reacting the processing gas to deposit a low k silicon carbide barrier layer useful as a barrier layer in damascene or dual damascene applications with low k dielectric materials.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: October 24, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Ping Xu, Louis Yang
  • Patent number: 6900481
    Abstract: A method for forming a transistor includes forming a gate dielectric layer over a portion of a semiconductor substrate, the substrate being substantially free of silicon; defining a gate electrode over a portion of the gate dielectric layer; and introducing ions into the substrate proximate the gate electrode to define source and drain regions. A transistor includes a semiconductor substrate that is substantially free of silicon and a gate dielectric layer over a portion of the substrate. The transistor can also include a gate electrode over a portion of the gate dielectric layer and introduce ions proximate the gate electrode, defining source and drain regions.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: May 31, 2005
    Assignee: Intel Corporation
    Inventors: Been-Yih Jin, Reza Arghavani, Robert Chau
  • Patent number: 6846757
    Abstract: A semiconductor device includes a low dielectric constant insulating film exhibiting an Si—H Fourier Transform Infrared (FTIR) doublet defined by a first and a second peak, wherein the first peak is located at a higher wave number than the second peak, and wherein the ratio of the first peak to the second peak is greater than unity. A method of producing such a semiconductor device includes depositing a dielectric layer over a substrate and treating the dielectric layer in a hydrogen containing plasma such that the dielectric layer exhibits an Si—H Fourier Transform Infrared (FTIR) doublet defined by a first and a second peak, wherein the first peak is located at a higher wave number than the second peak, and wherein the ratio of the first peak to the second peak is greater than unity.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: January 25, 2005
    Assignee: Trikon Holdings Limited
    Inventor: John MacNeil